- Timestamp:
- Jan 28, 2013, 1:59:32 PM (11 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
r289 r291 54 54 #include "mapping_table.h" 55 55 #include "int_tab.h" 56 #include "generic_llsc_global_table.h" 56 57 #include "mem_cache_directory_v4.h" 57 58 #include "xram_transaction_v4.h" … … 422 423 CacheData m_cache_data; // data array[set][way][word] 423 424 HeapDirectory m_heap; // heap for copies 425 GenericLLSCGlobalTable 426 < 427 32 , // desired number of slots 428 4096, // number of processors in the system 429 8000, // registratioçn life span (in # of LL operations) 430 typename vci_param::fast_addr_t // address type 431 > 432 m_llsc_table; // ll/sc global registration table 424 433 425 434 // adress masks … … 491 500 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 492 501 sc_signal<bool> r_read_last_free; // Last free entry 502 sc_signal<typename vci_param::fast_addr_t> 503 r_read_ll_key; // LL key returned by the llsc_global_table 493 504 494 505 // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) … … 505 516 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response 506 517 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response 518 sc_signal<typename vci_param::fast_addr_t> 519 r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table 507 520 508 521 /////////////////////////////////////////////////////////////// … … 533 546 sc_signal<size_t> r_write_trt_index; // index in Transaction Table 534 547 sc_signal<size_t> r_write_upt_index; // index in Update Table 548 sc_signal<bool> r_write_sc_fail; // sc command failed 549 sc_signal<bool> r_write_pending_sc; // sc command pending in WRITE fsm 535 550 536 551 // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) 537 sc_signal<bool> r_write_to_tgt_rsp_req; // valid request 538 sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid 539 sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid 540 sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid 552 sc_signal<bool> r_write_to_tgt_rsp_req; // valid request 553 sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid 554 sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid 555 sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid 556 sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed 541 557 542 558 // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) … … 721 737 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response 722 738 sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester 739 sc_signal<typename vci_param::fast_addr_t> 740 r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table 723 741 724 742 // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
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