Changeset 330 for branches

Timestamp:

Mar 20, 2013, 10:55:39 AM (12 years ago)

Author:

joannou

Message:

• Commented debug in dspin_local_ring_fast_c
• Added test on plen value in case of LL command in mem cache (vci_mem_cache and vci_mem_cache_dspin_coherence)
• Removed coherence handling in *CACHE_MISS_DATA_UPDT states, in vci_cc_vcache_wrapper_dspin_coherence component

Location:

branches/v5/modules

Files:

• dspin_local_ring_fast_c/caba/source/include/dspin_half_gateway_initiator_fast_c.h (modified) (1 diff)
• dspin_local_ring_fast_c/caba/source/include/dspin_half_gateway_target_fast_c.h (modified) (1 diff)
• dspin_local_ring_fast_c/caba/source/include/dspin_local_ring_initiator_fast_c.h (modified) (1 diff)
• dspin_local_ring_fast_c/caba/source/include/dspin_local_ring_target_fast_c.h (modified) (1 diff)
• vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (2 diffs)
• vci_mem_cache/caba/source/src/vci_mem_cache.cpp (modified) (1 diff)
• vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache.cpp (modified) (1 diff)

branches/v5/modules/dspin_local_ring_fast_c/caba/source/include/dspin_half_gateway_initiator_fast_c.h

@@ -34 +34 @@
 
 #define  BRDCST_TGT_MASK  0xFFFFFFFFE1ULL
-#define  HI_DEBUG
+//#define  HI_DEBUG
 
 namespace soclib { namespace caba {

branches/v5/modules/dspin_local_ring_fast_c/caba/source/include/dspin_half_gateway_target_fast_c.h

@@ -33 +33 @@
 #include "dspin_interface.h"
 
-#define HT_DEBUG
+//#define HT_DEBUG
 
 namespace soclib { namespace caba {

branches/v5/modules/dspin_local_ring_fast_c/caba/source/include/dspin_local_ring_initiator_fast_c.h

@@ -88 +88 @@
 
 #define  BRDCST_TGT_MASK  0xFFFFFFFFE1ULL
-#define I_DEBUG
+//#define I_DEBUG
 
 namespace soclib { namespace caba {

branches/v5/modules/dspin_local_ring_fast_c/caba/source/include/dspin_local_ring_target_fast_c.h

@@ -33 +33 @@
 #include "dspin_interface.h"
 
-#define T_DEBUG
+//#define T_DEBUG
 
 namespace soclib { namespace caba {

branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -1610 +1610 @@
     {
         if ( m_ireq.valid ) m_cost_ins_miss_frz++;
-
-        // coherence interrupt
-        if ( r_cc_receive_icache_req.read() )
-        {
-            r_icache_fsm = ICACHE_CC_CHECK;
-            r_icache_fsm_save = r_icache_fsm.read();
-            break;
-        }
 
         if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
@@ -4039 +4031 @@
         if ( m_dreq.valid) m_cost_data_miss_frz++;
 
-        // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() )
-        {
-            r_dcache_fsm = DCACHE_CC_CHECK;
-            r_dcache_fsm_cc_save = r_dcache_fsm.read();
-            break;
-        }
-
         if ( not r_dcache_miss_clack.read() )  // waiting cleanup acknowledge
         {

branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

@@ -916 +916 @@
         exit(0);
       }
+      if((p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ) && (p_vci_tgt.plen.read() != 8))
+      {
+        std::cout
+            << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
+            << std::endl;
+        std::cout
+            << " ll command packets must have a plen of 8"
+            << std::endl;
+        exit(0);
+      }
 
       if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() )

branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache.cpp

@@ -980 +980 @@
         exit(0);
       }
+      if((p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ) && (p_vci_tgt.plen.read() != 8))
+      {
+        std::cout
+            << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
+            << std::endl;
+        std::cout
+            << " ll command packets must have a plen of 8"
+            << std::endl;
+        exit(0);
+      }
 
       if(p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok())