- Timestamp:
- Mar 22, 2013, 5:40:44 PM (12 years ago)
- Location:
- branches/v5/modules
- Files:
-
- 2 edited
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- Unmodified
- Added
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branches/v5/modules/vci_cc_vcache_wrapper_dspin_coherence/caba/source/src/vci_cc_vcache_wrapper_dspin_coherence.cpp
r331 r333 5273 5273 // a request of the other, then update the client // 5274 5274 /////////////////////////////////////////////////////// 5275 // r_cc_send_last_client : 0 dcache 1 icache5276 bool update_last_client ;5275 // r_cc_send_last_client : 0 dcache / 1 icache 5276 bool update_last_client = r_cc_send_last_client.read(); 5277 5277 if ( r_cc_send_last_client.read() == 0 ) // last client was dcache 5278 5278 { 5279 if (r_icache_cc_send_req.read()) // request from icache5279 if (r_icache_cc_send_req.read()) // request from icache 5280 5280 update_last_client = 1; // update last client to icache 5281 5281 } 5282 5282 else // last client was icache 5283 5283 { 5284 if (r_dcache_cc_send_req.read()) // request from dcache5284 if (r_dcache_cc_send_req.read()) // request from dcache 5285 5285 update_last_client = 0; // update last client to dcache 5286 5286 } … … 5308 5308 case CC_SEND_CLEANUP_1: 5309 5309 { 5310 /**/ 5311 #if DEBUG_DCACHE 5312 if ( m_debug_dcache_fsm ) 5313 { 5314 std::cout << " <PROC " << name() 5315 << " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl; 5316 } 5317 #endif 5310 5318 // wait for the first flit to be consumed 5311 if (p_dspin_out.read.read())5319 if (p_dspin_out.read.read()) 5312 5320 r_cc_send_fsm = CC_SEND_CLEANUP_2; 5313 5321 … … 5316 5324 /////////////////////////// 5317 5325 case CC_SEND_CLEANUP_2: 5326 /**/ 5327 #if DEBUG_DCACHE 5328 if ( m_debug_dcache_fsm ) 5329 { 5330 std::cout << " <PROC " << name() 5331 << " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl; 5332 } 5333 #endif 5318 5334 { 5319 5335 assert( p_dspin_out.read.read() and … … 5321 5337 5322 5338 // wait for the second flit to be consumed 5323 if (p_dspin_out.read.read())5324 { 5325 if (r_cc_send_last_client.read() == 0) // dcache active request5339 if (p_dspin_out.read.read()) 5340 { 5341 if (r_cc_send_last_client.read() == 0) // dcache active request 5326 5342 r_dcache_cc_send_req = false; // reset dcache request 5327 5343 else // icache active request -
branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache_dspin_coherence.cpp
r331 r333 518 518 { 519 519 std::cout << " MEMC Write Monitor : " << buf << " Address = " << std::hex << addr 520 << " / Data = " << data << std::endl;520 << " / Data = " << data << " at cycle " << std::dec << m_cpt_cycles << std::endl; 521 521 } 522 522 } … … 4151 4151 // It must be freed and the copy registered in directory 4152 4152 // must point to the next copy in heap 4153 if(match_heap)4153 else if(match_heap) 4154 4154 { 4155 4155 dir_entry.ptr = heap_entry.next; … … 4164 4164 r_cleanup_fsm = CLEANUP_HEAP_FREE; 4165 4165 } 4166 4166 4167 // The matching copy is in the heap, but is not the first copy 4167 4168 // The directory entry must be modified to decrement count
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