- Timestamp:
- Mar 29, 2013, 6:56:36 PM (12 years ago)
- Location:
- branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source
- Files:
-
- 2 edited
-
include/vci_mem_cache_dspin_coherence.h (modified) (5 diffs)
-
src/vci_mem_cache_dspin_coherence.cpp (modified) (54 diffs)
Legend:
- Unmodified
- Added
- Removed
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branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/include/vci_mem_cache_dspin_coherence.h
r336 r346 326 326 327 327 // debug variables (for each FSM) 328 size_t m_debug_start_cycle;329 bool m_debug_ok;330 328 bool m_debug_global; 331 329 bool m_debug_tgt_cmd_fsm; … … 379 377 soclib::caba::VciTarget<vci_param> p_vci_tgt; 380 378 soclib::caba::VciInitiator<vci_param> p_vci_ixr; 381 382 379 soclib::caba::DspinInput<33> p_dspin_in; 383 380 soclib::caba::DspinOutput<40> p_dspin_out; … … 385 382 VciMemCache( 386 383 sc_module_name name, // Instance Name 387 const soclib::common::MappingTable &mtp, // Mapping table for primary requets 388 const soclib::common::MappingTable &mtc, // Mapping table for coherence requets 389 const soclib::common::MappingTable &mtx, // Mapping table for XRAM 390 const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator) 391 const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator) 392 const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) 393 const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup 394 size_t nways, // Number of ways per set 395 size_t nsets, // Number of sets 396 size_t nwords, // Number of words per line 397 size_t heap_size=1024, // Size of the heap 398 size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT 399 size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT 400 size_t debug_start_cycle=0, 401 bool debug_ok=false); 384 const soclib::common::MappingTable &mtp, // Mapping table for direct network 385 const soclib::common::MappingTable &mtx, // Mapping table for external network 386 const soclib::common::IntTab &srcid_x, // global index on external network 387 const soclib::common::IntTab &tgtid_d, // global index on direct network 388 const size_t cc_global_id, // global index on cc network 389 const size_t nways, // Number of ways per set 390 const size_t nsets, // Number of sets 391 const size_t nwords, // Number of words per line 392 const size_t max_copies, // max number of copies in heap 393 const size_t heap_size=1024, // number of heap entries 394 const size_t trt_lines=TRANSACTION_TAB_LINES, 395 const size_t upt_lines=UPDATE_TAB_LINES, 396 const size_t debug_start_cycle=0, 397 const bool debug_ok=false ); 402 398 403 399 ~VciMemCache(); … … 417 413 418 414 // Component attributes 419 std::list<soclib::common::Segment> m_seglist; // memory cached into the cache 420 std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache 421 422 const size_t m_initiators; // Number of initiators 423 const size_t m_heap_size; // Size of the heap 424 const size_t m_ways; // Number of ways in a set 425 const size_t m_sets; // Number of cache sets 426 const size_t m_words; // Number of words in a line 427 const size_t m_srcid_ixr; // Srcid for requests to XRAM 428 const size_t m_srcid_ini; // Srcid for requests to processors 429 430 uint32_t m_transaction_tab_lines; 431 TransactionTab m_transaction_tab; // xram transaction table 432 uint32_t m_update_tab_lines; 433 UpdateTab m_update_tab; // pending update & invalidate 434 CacheDirectory m_cache_directory; // data cache directory 435 CacheData m_cache_data; // data array[set][way][word] 436 HeapDirectory m_heap; // heap for copies 415 std::list<soclib::common::Segment> m_seglist; // segments allocated to memcache 416 size_t m_nseg; // number of segments 417 soclib::common::Segment **m_seg; // array of segments pointers 418 const size_t m_srcid_x; // global index on external network 419 const size_t m_initiators; // Number of initiators 420 const size_t m_heap_size; // Size of the heap 421 const size_t m_ways; // Number of ways in a set 422 const size_t m_sets; // Number of cache sets 423 const size_t m_words; // Number of words in a line 424 const size_t m_cc_global_id; // global_index on cc network 425 size_t m_debug_start_cycle; 426 bool m_debug_ok; 427 uint32_t m_trt_lines; 428 TransactionTab m_trt; // xram transaction table 429 uint32_t m_upt_lines; 430 UpdateTab m_upt; // pending update & invalidate 431 CacheDirectory m_cache_directory; // data cache directory 432 CacheData m_cache_data; // data array[set][way][word] 433 HeapDirectory m_heap; // heap for copies 434 size_t m_max_copies; // max number of copies in heap 437 435 GenericLLSCGlobalTable 438 < 439 32 , // desired number of slots 440 4096, // number of processors in the system 441 8000, // registratioçn life span (in # of LL operations) 442 typename vci_param::fast_addr_t // address type 443 > 444 m_llsc_table; // ll/sc global registration table 436 < 32 , // number of slots 437 4096, // number of processors in the system 438 8000, // registratioçn life span (in # of LL operations) 439 typename vci_param::fast_addr_t > // address type 440 m_llsc_table; // ll/sc global registration table 445 441 446 442 // adress masks 447 const soclib::common::AddressMaskingTable<vci_addr_t> m_x;448 const soclib::common::AddressMaskingTable<vci_addr_t> m_y;449 const soclib::common::AddressMaskingTable<vci_addr_t> m_z;450 const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;443 const soclib::common::AddressMaskingTable<vci_addr_t> m_x; 444 const soclib::common::AddressMaskingTable<vci_addr_t> m_y; 445 const soclib::common::AddressMaskingTable<vci_addr_t> m_z; 446 const soclib::common::AddressMaskingTable<vci_addr_t> m_nline; 451 447 452 448 // broadcast address 453 uint32_t m_broadcast_address; 454 455 ////////////////////////////////////////////////// 456 // Others registers 457 ////////////////////////////////////////////////// 458 sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line 459 sc_signal<size_t> xxx_count; 449 uint32_t m_broadcast_address; 460 450 461 451 ////////////////////////////////////////////////// … … 495 485 sc_signal<int> r_tgt_cmd_fsm; 496 486 497 size_t m_nseg;498 size_t m_ncseg;499 soclib::common::Segment **m_seg;500 soclib::common::Segment **m_cseg;501 487 /////////////////////////////////////////////////////// 502 488 // Registers controlled by the READ fsm -
branches/v5/modules/vci_mem_cache_dspin_coherence/caba/source/src/vci_mem_cache_dspin_coherence.cpp
r339 r346 1 1 /* -*- c++ -*- 2 * 2 3 * File : vci_mem_cache.cpp 3 4 * Date : 30/10/2008 … … 275 276 VciMemCache<vci_param> 276 277 277 using soclib::common::uint32_log2;278 using namespace soclib::common; 278 279 279 280 //////////////////////////////// … … 282 283 283 284 tmpl(/**/) ::VciMemCache( 284 sc_module_name name, 285 const soclib::common::MappingTable &mtp, 286 const soclib::common::MappingTable &mtc, 287 const soclib::common::MappingTable &mtx, 288 const soclib::common::IntTab &vci_ixr_index, 289 const soclib::common::IntTab &vci_ini_index, 290 const soclib::common::IntTab &vci_tgt_index, 291 const soclib::common::IntTab &vci_tgt_index_cleanup, 292 size_t nways, // number of ways per set 293 size_t nsets, // number of cache sets 294 size_t nwords, // number of words in cache line 295 size_t heap_size, // number of heap entries 296 size_t transaction_tab_lines, // number of TRT entries 297 size_t update_tab_lines, // number of UPT entries 298 size_t debug_start_cycle, 299 bool debug_ok) 285 sc_module_name name, 286 const MappingTable &mtp, // mapping table for direct network 287 const MappingTable &mtx, // mapping table for external network 288 const IntTab &srcid_x, // global index on external network 289 const IntTab &tgtid_d, // global index on direct network 290 const size_t cc_global_id, // global index on cc network 291 const size_t nways, // number of ways per set 292 const size_t nsets, // number of associative sets 293 const size_t nwords, // number of words in cache line 294 const size_t max_copies, // max number of copies in heap 295 const size_t heap_size, // number of heap entries 296 const size_t trt_lines, // number of TRT entries 297 const size_t upt_lines, // number of UPT entries 298 const size_t debug_start_cycle, 299 const bool debug_ok) 300 300 301 301 : soclib::caba::BaseModule(name), 302 302 303 m_debug_start_cycle(debug_start_cycle), 304 m_debug_ok(debug_ok), 305 306 p_clk("clk"), 307 p_resetn("resetn"), 308 p_vci_tgt("vci_tgt"), 309 p_vci_ixr("vci_ixr"), 310 p_dspin_in("dspin_tgt"), 311 p_dspin_out("cc_send"), 312 313 m_seglist(mtp.getSegmentList(vci_tgt_index)), 314 m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)), 315 316 m_initiators(1 << vci_param::S), 317 m_heap_size(heap_size), 318 m_ways(nways), 319 m_sets(nsets), 320 m_words(nwords), 321 m_srcid_ixr(mtx.indexForId(vci_ixr_index)), 322 m_srcid_ini(mtc.indexForId(vci_ini_index)), 323 m_transaction_tab_lines(transaction_tab_lines), 324 m_transaction_tab(transaction_tab_lines, nwords), 325 m_update_tab_lines(update_tab_lines), 326 m_update_tab(update_tab_lines), 303 p_clk( "p_clk" ), 304 p_resetn( "p_resetn" ), 305 p_vci_tgt( "p_vci_tgt" ), 306 p_vci_ixr( "p_vci_ixr" ), 307 p_dspin_in( "p_dspin_in" ), 308 p_dspin_out( "p_dspin_out" ), 309 310 m_seglist( mtp.getSegmentList(tgtid_d) ), 311 m_nseg( 0 ), 312 m_srcid_x( mtx.indexForId(srcid_x) ), 313 m_initiators( 1 << vci_param::S ), 314 m_heap_size( heap_size ), 315 m_ways( nways ), 316 m_sets( nsets ), 317 m_words( nwords ), 318 m_cc_global_id( cc_global_id ), 319 m_debug_start_cycle( debug_start_cycle ), 320 m_debug_ok( debug_ok ), 321 m_trt_lines(trt_lines), 322 m_trt(trt_lines, nwords), 323 m_upt_lines(upt_lines), 324 m_upt(upt_lines), 327 325 m_cache_directory(nways, nsets, nwords, vci_param::N), 328 326 m_cache_data(nways, nsets, nwords), 329 327 m_heap(m_heap_size), 328 m_max_copies( max_copies ), 330 329 m_llsc_table(), 331 330 … … 368 367 r_tgt_cmd_fsm("r_tgt_cmd_fsm"), 369 368 370 m_nseg(0),371 m_ncseg(0),372 373 369 r_read_fsm("r_read_fsm"), 374 370 … … 416 412 r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") 417 413 { 418 assert(IS_POW_OF_2(nsets));419 assert(IS_POW_OF_2(nwords));420 assert(IS_POW_OF_2(nways));421 assert(nsets);422 assert(nwords);423 assert(nways);424 425 // check Transaction table size426 assert((uint32_log2(transaction_tab_lines) <= vci_param::T) and414 assert(IS_POW_OF_2(nsets)); 415 assert(IS_POW_OF_2(nwords)); 416 assert(IS_POW_OF_2(nways)); 417 assert(nsets); 418 assert(nwords); 419 assert(nways); 420 421 // check Transaction table size 422 assert((uint32_log2(trt_lines) <= vci_param::T) and 427 423 "Need more bits for VCI TRDID field"); 428 424 429 // Get the segments associated to the MemCache 430 std::list<soclib::common::Segment>::iterator seg; 431 size_t i; 432 433 for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) 434 { 435 m_nseg++; 436 } 437 for(seg = m_cseglist.begin(); seg != m_cseglist.end() ; seg++) 438 { 439 m_ncseg++; 440 } 441 442 m_seg = new soclib::common::Segment*[m_nseg]; 443 444 i = 0; 445 for(seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++) 446 { 447 m_seg[i] = & (*seg); 448 i++; 449 } 450 451 m_cseg = new soclib::common::Segment*[m_ncseg]; 452 453 i = 0; 454 for(seg = m_cseglist.begin() ; seg != m_cseglist.end() ; seg++) 455 { 456 m_cseg[i] = & (*seg); 457 i++; 458 } 459 460 // Allocation for IXR_RSP FSM 461 r_ixr_rsp_to_xram_rsp_rok = new sc_signal<bool>[m_transaction_tab_lines]; 462 463 // Allocation for XRAM_RSP FSM 464 r_xram_rsp_victim_data = new sc_signal<data_t>[nwords]; 465 r_xram_rsp_to_tgt_rsp_data = new sc_signal<data_t>[nwords]; 466 r_xram_rsp_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 467 468 // Allocation for READ FSM 469 r_read_data = new sc_signal<data_t>[nwords]; 470 r_read_to_tgt_rsp_data = new sc_signal<data_t>[nwords]; 471 472 // Allocation for WRITE FSM 473 r_write_data = new sc_signal<data_t>[nwords]; 474 r_write_be = new sc_signal<be_t>[nwords]; 475 r_write_to_cc_send_data = new sc_signal<data_t>[nwords]; 476 r_write_to_cc_send_be = new sc_signal<be_t>[nwords]; 477 r_write_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 478 479 // Allocation for CAS FSM 480 r_cas_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 481 r_cas_data = new sc_signal<data_t>[nwords]; 482 r_cas_rdata = new sc_signal<data_t>[2]; 483 484 485 // Simulation 486 487 SC_METHOD(transition); 488 dont_initialize(); 489 sensitive << p_clk.pos(); 490 491 SC_METHOD(genMoore); 492 dont_initialize(); 493 sensitive << p_clk.neg(); 425 // Get the segments associated to the MemCache 426 std::list<soclib::common::Segment>::iterator seg; 427 size_t i = 0; 428 429 for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) 430 { 431 m_nseg++; 432 } 433 434 m_seg = new soclib::common::Segment*[m_nseg]; 435 436 for(seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++) 437 { 438 m_seg[i] = & (*seg); 439 i++; 440 } 441 442 // Allocation for IXR_RSP FSM 443 r_ixr_rsp_to_xram_rsp_rok = new sc_signal<bool>[m_trt_lines]; 444 445 // Allocation for XRAM_RSP FSM 446 r_xram_rsp_victim_data = new sc_signal<data_t>[nwords]; 447 r_xram_rsp_to_tgt_rsp_data = new sc_signal<data_t>[nwords]; 448 r_xram_rsp_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 449 450 // Allocation for READ FSM 451 r_read_data = new sc_signal<data_t>[nwords]; 452 r_read_to_tgt_rsp_data = new sc_signal<data_t>[nwords]; 453 454 // Allocation for WRITE FSM 455 r_write_data = new sc_signal<data_t>[nwords]; 456 r_write_be = new sc_signal<be_t>[nwords]; 457 r_write_to_cc_send_data = new sc_signal<data_t>[nwords]; 458 r_write_to_cc_send_be = new sc_signal<be_t>[nwords]; 459 r_write_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 460 461 // Allocation for CAS FSM 462 r_cas_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 463 r_cas_data = new sc_signal<data_t>[nwords]; 464 r_cas_rdata = new sc_signal<data_t>[2]; 465 466 467 SC_METHOD(transition); 468 dont_initialize(); 469 sensitive << p_clk.pos(); 470 471 SC_METHOD(genMoore); 472 dont_initialize(); 473 sensitive << p_clk.neg(); 494 474 } // end constructor 495 475 … … 580 560 std::cout << "----------------------------------" << std::dec << std::endl; 581 561 std::cout 582 << "MEM_CACHE " << m_srcid_ini<< " / Time = " << m_cpt_cycles << std::endl562 << "MEM_CACHE " << name() << " / Time = " << m_cpt_cycles << std::endl 583 563 << "- READ RATE = " << (double) m_cpt_read/m_cpt_cycles << std::endl 584 564 << "- READ TOTAL = " << m_cpt_read << std::endl … … 666 646 667 647 // Initializing Tables 668 m_tr ansaction_tab.init();669 m_up date_tab.init();648 m_trt.init(); 649 m_upt.init(); 670 650 m_llsc_table.init(); 671 651 … … 728 708 #endif 729 709 730 for(size_t i=0; i<m_tr ansaction_tab_lines ; i++)710 for(size_t i=0; i<m_trt_lines ; i++) 731 711 { 732 712 r_ixr_rsp_to_xram_rsp_rok[i] = false; … … 748 728 r_alloc_dir_reset_cpt = 0; 749 729 r_alloc_heap_reset_cpt = 0; 750 751 r_copies_limit = 3;752 730 753 731 // Activity counters … … 835 813 std::cout 836 814 << "---------------------------------------------" << std::dec << std::endl 837 << "MEM_CACHE " << m_srcid_ini815 << "MEM_CACHE " << name() 838 816 << " ; Time = " << m_cpt_cycles << std::endl 839 817 << " - TGT_CMD FSM = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()] << std::endl … … 1139 1117 (DspinDhccpParam::dspin_get(flit, DspinDhccpParam::FROM_L1_EOP) == 0x1); 1140 1118 1141 if(updt_index >= m_up date_tab.size())1119 if(updt_index >= m_upt.size()) 1142 1120 { 1143 1121 std::cout … … 1147 1125 << std::dec 1148 1126 << " / UPT index = " << updt_index 1149 << " / UPT size = " << m_up date_tab.size()1127 << " / UPT size = " << m_upt.size() 1150 1128 << std::endl; 1151 1129 … … 1188 1166 // decrement the number of expected responses 1189 1167 size_t count = 0; 1190 bool valid = m_up date_tab.decrement(r_multi_ack_upt_index.read(), count);1168 bool valid = m_upt.decrement(r_multi_ack_upt_index.read(), count); 1191 1169 1192 1170 if(not valid) … … 1237 1215 } 1238 1216 1239 r_multi_ack_srcid = m_up date_tab.srcid(r_multi_ack_upt_index.read());1240 r_multi_ack_trdid = m_up date_tab.trdid(r_multi_ack_upt_index.read());1241 r_multi_ack_pktid = m_up date_tab.pktid(r_multi_ack_upt_index.read());1242 r_multi_ack_nline = m_up date_tab.nline(r_multi_ack_upt_index.read());1243 bool need_rsp = m_up date_tab.need_rsp(r_multi_ack_upt_index.read());1217 r_multi_ack_srcid = m_upt.srcid(r_multi_ack_upt_index.read()); 1218 r_multi_ack_trdid = m_upt.trdid(r_multi_ack_upt_index.read()); 1219 r_multi_ack_pktid = m_upt.pktid(r_multi_ack_upt_index.read()); 1220 r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read()); 1221 bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read()); 1244 1222 1245 1223 // clear the UPT entry 1246 m_up date_tab.clear(r_multi_ack_upt_index.read());1224 m_upt.clear(r_multi_ack_upt_index.read()); 1247 1225 1248 1226 if(need_rsp) … … 1570 1548 { 1571 1549 // enter counter mode when we reach the limit of copies or the heap is full 1572 bool go_cnt = (r_read_count.read() >= r_copies_limit.read()) || m_heap.is_full();1550 bool go_cnt = (r_read_count.read() >= m_max_copies) || m_heap.is_full(); 1573 1551 1574 1552 // read data in the cache … … 1813 1791 size_t index = 0; 1814 1792 vci_addr_t addr = (vci_addr_t) m_cmd_read_addr_fifo.read(); 1815 bool hit_read = m_tr ansaction_tab.hit_read(m_nline[addr], index);1816 bool hit_write = m_tr ansaction_tab.hit_write(m_nline[addr]);1817 bool wok = !m_tr ansaction_tab.full(index);1793 bool hit_read = m_trt.hit_read(m_nline[addr], index); 1794 bool hit_write = m_trt.hit_write(m_nline[addr]); 1795 bool wok = !m_trt.full(index); 1818 1796 1819 1797 if(hit_read || !wok || hit_write) // missing line already requested or no space … … 1848 1826 if(r_alloc_trt_fsm.read() == ALLOC_TRT_READ) 1849 1827 { 1850 m_tr ansaction_tab.set(r_read_trt_index.read(),1828 m_trt.set(r_read_trt_index.read(), 1851 1829 true, 1852 1830 m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())], … … 2301 2279 size_t way = r_write_way.read(); 2302 2280 2303 wok = m_up date_tab.set(true, // it's an update transaction2281 wok = m_upt.set(true, // it's an update transaction 2304 2282 false, // it's not a broadcast 2305 2283 true, // it needs a response … … 2620 2598 size_t wok_index = 0; 2621 2599 vci_addr_t addr = (vci_addr_t) r_write_address.read(); 2622 bool hit_read = m_tr ansaction_tab.hit_read(m_nline[addr], hit_index);2623 bool hit_write = m_tr ansaction_tab.hit_write(m_nline[addr]);2624 bool wok = !m_tr ansaction_tab.full(wok_index);2600 bool hit_read = m_trt.hit_read(m_nline[addr], hit_index); 2601 bool hit_write = m_trt.hit_write(m_nline[addr]); 2602 bool wok = !m_trt.full(wok_index); 2625 2603 2626 2604 if(hit_read) // register the modified data in TRT … … 2672 2650 data_vector.push_back(r_write_data[i]); 2673 2651 } 2674 m_tr ansaction_tab.set(r_write_trt_index.read(),2652 m_trt.set(r_write_trt_index.read(), 2675 2653 true, // read request to XRAM 2676 2654 m_nline[(vci_addr_t)(r_write_address.read())], … … 2709 2687 data_vector.push_back(r_write_data[i]); 2710 2688 } 2711 m_tr ansaction_tab.write_data_mask(r_write_trt_index.read(),2689 m_trt.write_data_mask(r_write_trt_index.read(), 2712 2690 be_vector, 2713 2691 data_vector); … … 2718 2696 { 2719 2697 std::cout << " <MEMC " << name() << ".WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl; 2720 m_tr ansaction_tab.print(r_write_trt_index.read());2698 m_trt.print(r_write_trt_index.read()); 2721 2699 } 2722 2700 #endif … … 2752 2730 { 2753 2731 size_t wok_index = 0; 2754 bool wok = !m_tr ansaction_tab.full(wok_index);2732 bool wok = !m_trt.full(wok_index); 2755 2733 if(wok) // set a new entry in TRT 2756 2734 { … … 2787 2765 size_t nb_copies = r_write_count.read(); 2788 2766 2789 wok =m_up date_tab.set(false, // it's an inval transaction2767 wok =m_upt.set(false, // it's an inval transaction 2790 2768 true, // it's a broadcast 2791 2769 true, // it needs a response … … 2830 2808 2831 2809 // register a write request to XRAM in TRT 2832 m_tr ansaction_tab.set(r_write_trt_index.read(),2810 m_trt.set(r_write_trt_index.read(), 2833 2811 false, // write request to XRAM 2834 2812 m_nline[(vci_addr_t)(r_write_address.read())], … … 3160 3138 if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) 3161 3139 { 3162 m_tr ansaction_tab.erase(r_ixr_rsp_trt_index.read());3140 m_trt.erase(r_ixr_rsp_trt_index.read()); 3163 3141 r_ixr_rsp_fsm = IXR_RSP_IDLE; 3164 3142 … … 3184 3162 assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-1))) || p_vci_ixr.rerror.read()) 3185 3163 and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM"); 3186 m_tr ansaction_tab.write_rsp(index,3164 m_trt.write_rsp(index, 3187 3165 r_ixr_rsp_cpt.read(), 3188 3166 data, … … 3238 3216 { 3239 3217 size_t ptr = r_xram_rsp_trt_index.read(); 3240 size_t lines = m_tr ansaction_tab_lines;3218 size_t lines = m_trt_lines; 3241 3219 for(size_t i=0 ; i<lines ; i++) 3242 3220 { … … 3272 3250 size_t index = r_xram_rsp_trt_index.read(); 3273 3251 3274 TransactionTabEntry trt_entry(m_tr ansaction_tab.read(index));3252 TransactionTabEntry trt_entry(m_trt.read(index)); 3275 3253 r_xram_rsp_trt_buf.copy(trt_entry); // TRT entry local buffer 3276 3254 … … 3352 3330 { 3353 3331 size_t index; 3354 if(m_up date_tab.search_inval(r_xram_rsp_trt_buf.nline, index))3332 if(m_upt.search_inval(r_xram_rsp_trt_buf.nline, index)) 3355 3333 { 3356 3334 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; … … 3361 3339 std::cout << " <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT," 3362 3340 << " but an invalidation is already registered at this address" << std::endl; 3363 m_up date_tab.print();3341 m_upt.print(); 3364 3342 } 3365 3343 #endif 3366 3344 3367 3345 } 3368 else if(m_up date_tab.is_full() && r_xram_rsp_victim_inval.read())3346 else if(m_upt.is_full() && r_xram_rsp_victim_inval.read()) 3369 3347 { 3370 3348 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; … … 3375 3353 std::cout << " <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT," 3376 3354 << " but the table is full" << std::endl; 3377 m_up date_tab.print();3355 m_upt.print(); 3378 3356 } 3379 3357 #endif … … 3463 3441 size_t count_copies = r_xram_rsp_victim_count.read(); 3464 3442 3465 bool wok = m_up date_tab.set(false, // it's an inval transaction3443 bool wok = m_upt.set(false, // it's an inval transaction 3466 3444 brdcast, // set brdcast bit 3467 3445 false, // it does not need a response … … 3501 3479 // If the victim is not dirty, we don't need another XRAM put transaction, 3502 3480 // and we canwe erase the TRT entry 3503 if(!r_xram_rsp_victim_dirty.read()) m_tr ansaction_tab.erase(r_xram_rsp_trt_index.read());3481 if(!r_xram_rsp_victim_dirty.read()) m_trt.erase(r_xram_rsp_trt_index.read()); 3504 3482 3505 3483 // Next state … … 3515 3493 if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) 3516 3494 { 3517 m_tr ansaction_tab.set(r_xram_rsp_trt_index.read(),3495 m_trt.set(r_xram_rsp_trt_index.read(), 3518 3496 false, // write to XRAM 3519 3497 r_xram_rsp_victim_nline.read(), // line index … … 3740 3718 case XRAM_RSP_ERROR_ERASE: // erase TRT entry in case of error 3741 3719 { 3742 m_tr ansaction_tab.erase(r_xram_rsp_trt_index.read());3720 m_trt.erase(r_xram_rsp_trt_index.read()); 3743 3721 3744 3722 // Next state … … 4435 4413 bool match_inval; 4436 4414 4437 match_inval = m_up date_tab.search_inval(r_cleanup_nline.read(), index);4415 match_inval = m_upt.search_inval(r_cleanup_nline.read(), index); 4438 4416 4439 4417 // no pending inval … … 4458 4436 4459 4437 // pending inval 4460 r_cleanup_write_srcid = m_up date_tab.srcid(index);4461 r_cleanup_write_trdid = m_up date_tab.trdid(index);4462 r_cleanup_write_pktid = m_up date_tab.pktid(index);4463 r_cleanup_write_need_rsp = m_up date_tab.need_rsp(index);4438 r_cleanup_write_srcid = m_upt.srcid(index); 4439 r_cleanup_write_trdid = m_upt.trdid(index); 4440 r_cleanup_write_pktid = m_upt.pktid(index); 4441 r_cleanup_write_need_rsp = m_upt.need_rsp(index); 4464 4442 r_cleanup_index = index; 4465 4443 … … 4497 4475 4498 4476 size_t count = 0; 4499 m_up date_tab.decrement(r_cleanup_index.read(), count);4477 m_upt.decrement(r_cleanup_index.read(), count); 4500 4478 4501 4479 // invalidation transaction finished … … 4539 4517 } 4540 4518 4541 m_up date_tab.clear(r_cleanup_index.read());4519 m_upt.clear(r_cleanup_index.read()); 4542 4520 4543 4521 if(r_cleanup_write_need_rsp.read()) … … 4919 4897 size_t nb_copies = r_cas_count.read(); 4920 4898 4921 wok = m_up date_tab.set(true, // it's an update transaction4899 wok = m_upt.set(true, // it's an update transaction 4922 4900 false, // it's not a broadcast 4923 4901 true, // it needs a response … … 5125 5103 } 5126 5104 size_t wok_index = 0; 5127 bool wok = !m_tr ansaction_tab.full(wok_index);5105 bool wok = !m_trt.full(wok_index); 5128 5106 if(wok) 5129 5107 { … … 5158 5136 5159 5137 // register a broadcast inval transaction in UPT 5160 wok = m_up date_tab.set(false, // it's an inval transaction5138 wok = m_upt.set(false, // it's an inval transaction 5161 5139 true, // it's a broadcast 5162 5140 true, // it needs a response … … 5216 5194 { 5217 5195 // set TRT 5218 m_tr ansaction_tab.set(r_cas_trt_index.read(),5196 m_trt.set(r_cas_trt_index.read(), 5219 5197 false, // PUT request to XRAM 5220 5198 m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())], … … 5361 5339 { 5362 5340 size_t index = 0; 5363 bool hit_read = m_tr ansaction_tab.hit_read(5341 bool hit_read = m_trt.hit_read( 5364 5342 m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()],index); 5365 bool hit_write = m_tr ansaction_tab.hit_write(5343 bool hit_write = m_trt.hit_write( 5366 5344 m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()]); 5367 bool wok = !m_tr ansaction_tab.full(index);5345 bool wok = !m_trt.full(index); 5368 5346 5369 5347 #if DEBUG_MEMC_CAS … … 5405 5383 } 5406 5384 5407 m_tr ansaction_tab.set(r_cas_trt_index.read(),5385 m_trt.set(r_cas_trt_index.read(), 5408 5386 true, // read request 5409 5387 m_nline[(vci_addr_t) m_cmd_cas_addr_fifo.read()], … … 7162 7140 p_vci_ixr.be = 0xF; 7163 7141 p_vci_ixr.pktid = 0; 7164 p_vci_ixr.srcid = m_srcid_ ixr;7142 p_vci_ixr.srcid = m_srcid_x; 7165 7143 p_vci_ixr.cons = false; 7166 7144 p_vci_ixr.wrap = false; … … 7288 7266 // Response signals on the p_vci_tgt port 7289 7267 //////////////////////////////////////////////////// 7268 7290 7269 switch(r_tgt_rsp_fsm.read()) 7291 7270 { … … 7384 7363 // Initiator command signals on the p_dspin_out port (CC_SEND FSM) 7385 7364 //////////////////////////////////////////////////////////////////// 7365 7386 7366 p_dspin_out.write = false; 7387 7367 p_dspin_out.data = 0; … … 7389 7369 switch(r_cc_send_fsm.read()) 7390 7370 { 7371 7391 7372 case CC_SEND_XRAM_RSP_IDLE: 7392 7373 case CC_SEND_WRITE_IDLE: … … 7463 7444 DspinDhccpParam::dspin_set( 7464 7445 flit, 7465 m_ srcid_ini,7446 m_cc_global_id, 7466 7447 DspinDhccpParam::MULTI_INVAL_SRCID); 7467 7448 … … 7516 7497 DspinDhccpParam::dspin_set( 7517 7498 flit, 7518 m_ srcid_ini,7499 m_cc_global_id, 7519 7500 DspinDhccpParam::BROADCAST_SRCID); 7520 7501 … … 7613 7594 DspinDhccpParam::dspin_set( 7614 7595 flit, 7615 m_ srcid_ini,7596 m_cc_global_id, 7616 7597 DspinDhccpParam::MULTI_UPDT_SRCID); 7617 7598 … … 7717 7698 DspinDhccpParam::dspin_set( 7718 7699 flit, 7719 m_ srcid_ini,7700 m_cc_global_id, 7720 7701 DspinDhccpParam::MULTI_UPDT_SRCID); 7721 7702
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