Changeset 351
- Timestamp:
- Apr 4, 2013, 2:36:54 PM (12 years ago)
- Location:
- branches/v5
- Files:
-
- 7 deleted
- 13 edited
- 6 copied
- 4 moved
Legend:
- Unmodified
- Added
- Removed
-
branches/v5/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd
r350 r351 2 2 # -*- python -*- 3 3 4 Module('caba:vci_cc_vcache_wrapper _dspin_coherence',4 Module('caba:vci_cc_vcache_wrapper', 5 5 classname = 'soclib::caba::VciCcVCacheWrapper', 6 6 … … 10 10 ], 11 11 12 header_files = [ '../source/include/vci_cc_vcache_wrapper _dspin_coherence.h' ],12 header_files = [ '../source/include/vci_cc_vcache_wrapper.h' ], 13 13 14 implementation_files = [ '../source/src/vci_cc_vcache_wrapper _dspin_coherence.cpp' ],14 implementation_files = [ '../source/src/vci_cc_vcache_wrapper.cpp' ], 15 15 16 16 uses = [ -
branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r350 r351 30 30 #include <cassert> 31 31 #include "arithmetics.h" 32 #include "../include/vci_cc_vcache_wrapper _dspin_coherence.h"32 #include "../include/vci_cc_vcache_wrapper.h" 33 33 34 34 #define DEBUG_DCACHE 1 -
branches/v5/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd
r350 r351 5 5 __version__ = "$Revision: 295 $" 6 6 7 Module('caba:vci_mem_cache _dspin_coherence',7 Module('caba:vci_mem_cache', 8 8 classname = 'soclib::caba::VciMemCache', 9 9 … … 13 13 14 14 header_files = [ 15 '../source/include/vci_mem_cache _dspin_coherence.h',15 '../source/include/vci_mem_cache.h', 16 16 '../source/include/xram_transaction.h', 17 17 '../source/include/mem_cache_directory.h', … … 19 19 ], 20 20 21 implementation_files = [ '../source/src/vci_mem_cache _dspin_coherence.cpp' ],21 implementation_files = [ '../source/src/vci_mem_cache.cpp' ], 22 22 23 23 uses = [ -
branches/v5/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r350 r351 31 31 */ 32 32 33 #include "../include/vci_mem_cache _dspin_coherence.h"33 #include "../include/vci_mem_cache.h" 34 34 35 35 ////// debug services /////////////////////////////////////////////////////// … … 1208 1208 std::cout 1209 1209 << "VCI_MEM_CACHE ERROR " << name() 1210 << " MULTI_ACK_UPT_ LOCKstate"1210 << " MULTI_ACK_UPT_CLEAR state" 1211 1211 << " bad UPT allocation" 1212 1212 << std::endl; -
branches/v5/platforms/tsar_generic_mmu/soclib.conf
r342 r351 5 5 #config.addDescPath("path/to/tsar/branches/v5/modules/") 6 6 #config.addDescPath("path/to/tsar/branches/v5/communication/") 7 #config.addDescPath("path/to/tsar/branches/v5/platforms/tsar_generic_mmu_dspin_coherence/") -
branches/v5/platforms/tsar_generic_mmu/top.cpp
r342 r351 424 424 std::cout << maptabd << std::endl; 425 425 426 // coherence network427 // - tgtid_c_proc = srcid_c_proc = local procid428 // - tgtid_c_memc = srcid_c_memc = NB_PROCS_MAX429 MappingTable maptabc(address_width,430 IntTab(x_width + y_width, srcid_width - x_width - y_width),431 IntTab(x_width + y_width, srcid_width - x_width - y_width),432 0x00FF0000);433 434 for (size_t x = 0; x < CLUSTER_X; x++)435 {436 for (size_t y = 0; y < CLUSTER_Y; y++)437 {438 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);439 440 // cleanup requests must be routed to the memory cache441 std::ostringstream sh;442 sh << "c_seg_memc_" << x << "_" << y;443 maptabc.add(Segment(sh.str(), (NB_PROCS_MAX << (address_width - srcid_width)) + offset,444 0x10, IntTab(cluster(x,y), NB_PROCS_MAX), false));445 446 // update & invalidate requests must be routed to the proper processor447 for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++)448 {449 std::ostringstream sp;450 sp << "c_seg_proc_" << x << "_" << y << "_" << p;451 maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset ,452 0x10 , IntTab(cluster(x,y), p) , false));453 }454 }455 }456 std::cout << maptabc << std::endl;457 426 458 427 // external network … … 557 526 cluster(x,y), 558 527 maptabd, 559 maptabc,560 528 maptabx, 561 529 x_width, 562 530 y_width, 531 4, //local_id_width 563 532 MEMC_TGTID, 564 533 XICU_TGTID, … … 724 693 std::cout << " ************************************************" << std::endl; 725 694 726 //clusters[0][0]->proc[0]->print_trace();695 // clusters[0][0]->proc[0]->print_trace(); 727 696 // clusters[0][0]->proc[1]->print_trace(); 728 clusters[0][0]->proc[2]->print_trace();697 // clusters[1][0]->proc[2]->print_trace(); 729 698 // clusters[0][0]->proc[3]->print_trace(); 730 clusters[0][0]->memc->print_trace();699 // clusters[0][0]->memc->print_trace(); 731 700 // trace proc[debug_proc_id] 732 /*733 701 if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) 734 702 { … … 739 707 740 708 clusters[proc_x][proc_y]->signal_vci_ini_d_proc[0].print_trace("proc_ini_d"); 741 clusters[proc_x][proc_y]->signal_ vci_ini_c_proc[0].print_trace("proc_ini_c");742 clusters[proc_x][proc_y]->signal_ vci_tgt_c_proc[0].print_trace("proc_tgt_c");709 clusters[proc_x][proc_y]->signal_dspin_c_from_proc[0].print_trace("from_proc_c"); 710 clusters[proc_x][proc_y]->signal_dspin_c_to_proc[0].print_trace("to_proc_c"); 743 711 } 744 712 … … 752 720 753 721 clusters[memc_x][memc_y]->signal_vci_tgt_d_memc.print_trace("memc_tgt_d"); 754 clusters[memc_x][memc_y]->signal_ vci_ini_c_memc.print_trace("memc_ini_c");755 clusters[memc_x][memc_y]->signal_ vci_tgt_c_memc.print_trace("memc_tgt_c");722 clusters[memc_x][memc_y]->signal_dspin_c_from_memc.print_trace("from_memc_c"); 723 clusters[memc_x][memc_y]->signal_dspin_c_to_memc.print_trace("to_memc_c"); 756 724 } 757 725 … … 776 744 // clusters[1][1]->signal_vci_tgt_d_mdma.print_trace("mdma_1_1_tgt_d "); 777 745 // clusters[1][1]->signal_vci_ini_d_mdma.print_trace("mdma_1_1_ini_d "); 778 */779 746 } 780 747 -
branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/metadata/tsar_cluster_mmu.sd
r342 r351 15 15 Uses('common:mapping_table'), 16 16 Uses('common:iss2'), 17 Uses('caba:vci_cc_vcache_wrapper _dspin_coherence',17 Uses('caba:vci_cc_vcache_wrapper', 18 18 iss_t = 'common:gdb_iss', 19 19 gdb_iss_t = 'common:mips32el'), 20 Uses('caba:vci_mem_cache _dspin_coherence'),20 Uses('caba:vci_mem_cache'), 21 21 Uses('caba:vci_simple_ram'), 22 22 Uses('caba:vci_xicu'), -
branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/source/include/tsar_cluster_mmu.h
r342 r351 32 32 #include "vci_framebuffer.h" 33 33 #include "vci_multi_dma.h" 34 #include "vci_mem_cache _dspin_coherence.h"35 #include "vci_cc_vcache_wrapper _dspin_coherence.h"34 #include "vci_mem_cache.h" 35 #include "vci_cc_vcache_wrapper.h" 36 36 37 37 namespace soclib { … … 128 128 size_t cluster, // y + ymax*x 129 129 const soclib::common::MappingTable &mtd, // direct mapping table 130 const soclib::common::MappingTable &mtc, // coherence mapping table131 130 const soclib::common::MappingTable &mtx, // xram mapping table 132 131 size_t x_width, // x field number of bits 133 132 size_t y_width, // y field number of bits 133 size_t l_width, // l field number of bits 134 134 size_t tgtid_memc, 135 135 size_t tgtid_xicu, … … 150 150 size_t xfb, // frame buffer pixels 151 151 size_t yfb, // frame buffer lines 152 char* disk_name, // virtual disk namefor BDEV152 char* disk_name, // virtual disk for BDEV 153 153 size_t block_size, // block size for BDEV 154 154 size_t nic_channels, // number of channels -
branches/v5/platforms/tsar_generic_mmu/tsar_cluster_mmu/caba/source/src/tsar_cluster_mmu.cpp
r343 r351 42 42 size_t cluster_id, 43 43 const soclib::common::MappingTable &mtd, 44 const soclib::common::MappingTable &mtc,45 44 const soclib::common::MappingTable &mtx, 46 45 size_t x_width, 47 46 size_t y_width, 47 size_t l_width, 48 48 size_t tgtid_memc, 49 49 size_t tgtid_xicu, … … 106 106 cluster_id*nb_procs + p, 107 107 mtd, // Mapping Table Direct 108 mtc, // Mapping Table Coherence109 108 IntTab(cluster_id,p), // SRCID_D 110 IntTab(cluster_id,p), // SRCID_C 111 IntTab(cluster_id,p), // TGTID_C 109 (cluster_id << l_width) + p, // CC_GLOBAL_ID 112 110 8, // ITLB ways 113 111 8, // ITLB sets … … 120 118 x_width, 121 119 y_width, 122 nb_procs, // MEMC local index123 120 frozen_cycles, // max frozen cycles 124 121 debug_start_cycle, … … 132 129 memc = new VciMemCache<vci_param>( 133 130 smemc.str().c_str(), 134 mtd, mt c, mtx,131 mtd, mtx, 135 132 IntTab(cluster_id), // SRCID_X 136 IntTab(cluster_id, nb_procs), // SRCID_C137 133 IntTab(cluster_id, tgtid_memc), // TGTID_D 138 IntTab(cluster_id, nb_procs), // TGTID_C134 (cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID 139 135 memc_ways, memc_sets, 16, // CACHE SIZE 140 //4096, // HEAP SIZE136 3, // MAX NUMBER OF COPIES 141 137 256, // HEAP SIZE 142 138 8, // TRANSACTION TABLE DEPTH … … 205 201 sc << "ringc_" << x_id << "_" << y_id; 206 202 //ringc = new soclib::caba::DspinLocalRingFastC<vci_param, 40, 33>(sc.str().c_str(),mtc, IntTab(cluster_id), 2, 2, 2, nb_procs + 1, x_width, y_width); 207 ringc = new soclib::caba::DspinLocalRingFastC<vci_param, 40, 33>(sc.str().c_str(),mtc, IntTab(cluster_id), 2, 2, 1, nb_procs, x_width, y_width); 203 // 204 // coherence network 205 // - tgtid_c_proc = srcid_c_proc = local procid 206 // - tgtid_c_memc = srcid_c_memc = NB_PROCS_MAX 207 #define address_width 32 208 #define srcid_width 14 209 #include "../../../../giet_vm/hard_config.h" 210 #define cluster(x,y) (y + CLUSTER_Y*x) 211 MappingTable maptabc(address_width, 212 IntTab(x_width + y_width, srcid_width - x_width - y_width), 213 IntTab(x_width + y_width, srcid_width - x_width - y_width), 214 0x00FF0000); 215 216 for (size_t x = 0; x < CLUSTER_X; x++) 217 { 218 for (size_t y = 0; y < CLUSTER_Y; y++) 219 { 220 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 221 222 // cleanup requests must be routed to the memory cache 223 std::ostringstream sh; 224 sh << "c_seg_memc_" << x << "_" << y; 225 maptabc.add(Segment(sh.str(), (NB_PROCS_MAX << (address_width - srcid_width)) + offset, 226 0x10, IntTab(cluster(x,y), NB_PROCS_MAX), false)); 227 228 // update & invalidate requests must be routed to the proper processor 229 for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++) 230 { 231 std::ostringstream sp; 232 sp << "c_seg_proc_" << x << "_" << y << "_" << p; 233 maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , 234 0x10 , IntTab(cluster(x,y), p) , false)); 235 } 236 } 237 } 238 std::cout << maptabc << std::endl; 239 // 240 // 241 // 242 ringc = new soclib::caba::DspinLocalRingFastC<vci_param, 40, 33>(sc.str().c_str(),maptabc, IntTab(cluster_id), 2, 2, 1, nb_procs, x_width, y_width); 208 243 209 244 std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; … … 405 440 proc[p]->p_clk (this->p_clk); 406 441 proc[p]->p_resetn (this->p_resetn); 407 proc[p]->p_vci _ini_d(signal_vci_ini_d_proc[p]);442 proc[p]->p_vci (signal_vci_ini_d_proc[p]); 408 443 proc[p]->p_dspin_in (signal_dspin_c_to_proc[p]); 409 444 proc[p]->p_dspin_out (signal_dspin_c_from_proc[p]); -
branches/v5/platforms/tsar_mono_mmu/soclib.conf
r316 r351 1 1 config.default.toolchain.set("cflags", config.default.toolchain.cflags + ['-DI_WANT_ILLEGAL_VCI']) 2 2 3 #config.addDescPath(" /path/to/tsar/trunk/lib/")4 #config.addDescPath(" /path/to/tsar/trunk/modules/")5 #config.addDescPath(" /path/to/tsar/branches/v5/modules/")6 #config.addDescPath(" /path/to/tsar/branches/v5/communication/")3 #config.addDescPath("path/to/tsar/trunk/lib/") 4 #config.addDescPath("path/to/tsar/trunk/modules/") 5 #config.addDescPath("path/to/tsar/branches/v5/modules/") 6 #config.addDescPath("path/to/tsar/branches/v5/communication/") -
branches/v5/platforms/tsar_mono_mmu/top.cpp
r332 r351 14 14 #include "vci_multi_tty.h" 15 15 #include "vci_vgmn.h" 16 #include "vci_mem_cache _dspin_coherence.h"17 #include "vci_cc_vcache_wrapper _dspin_coherence.h"16 #include "vci_mem_cache.h" 17 #include "vci_cc_vcache_wrapper.h" 18 18 #include "vci_xicu.h" 19 19 #include "vci_simhelper.h" … … 194 194 VciCcVCacheWrapper<vci_param, proc_iss > 195 195 proc("proc", 196 0, // proc_id196 0, // proc_id 197 197 maptabd, // direct space 198 maptabc, // coherence space 199 IntTab(0), // srcid_d 200 IntTab(0), // srcid_c 201 IntTab(0), // tgtid_c 198 0, // srcid_d 199 0, // id_c 202 200 8,8, // itlb size 203 201 8,8, // dtlb size … … 205 203 4,64,16, // dcache size 206 204 4, 4, // wbuf size 207 0, 0, // x, y Width 208 nprocs, // memory cache local id 209 max_frozen, // max frozen cycles 205 0, 0, // x, y Width 206 max_frozen, // max frozen cycles 210 207 from_cycle, trace_ok); 211 208 … … 225 222 memc("memc", 226 223 maptabd, 227 maptabc,228 224 maptabd, 229 IntTab(0), // srcid_x 230 IntTab(1), // srcid_c 231 IntTab(0), // tgtid_d 232 IntTab(1), // tgtid_c 225 0, // srcid_x 226 0, // tgtid_d 227 1, // cc_id 233 228 16,256,16, // cache size 229 3, // MAX NUMBER OF COPIES 234 230 1024, // HEAP size 235 231 4, // TRT size … … 291 287 proc.p_irq[4] (signal_false); 292 288 proc.p_irq[5] (signal_false); 293 proc.p_vci _ini_d(signal_vci_ini_d_proc);289 proc.p_vci (signal_vci_ini_d_proc); 294 290 proc.p_dspin_in (signal_dspin_from_memc); 295 291 proc.p_dspin_out (signal_dspin_from_proc); -
branches/v5/platforms/tsar_mono_mmu/top.desc
r316 r351 4 4 uses = [ 5 5 Uses('common:mapping_table'), 6 Uses('caba:vci_cc_vcache_wrapper _dspin_coherence', iss_t = 'common:mips32el'),6 Uses('caba:vci_cc_vcache_wrapper', iss_t = 'common:mips32el'), 7 7 Uses('caba:vci_simple_ram'), 8 8 Uses('caba:vci_logger'), … … 12 12 Uses('caba:vci_vgmn'), 13 13 Uses('caba:vci_simhelper'), 14 Uses('caba:vci_mem_cache _dspin_coherence'),14 Uses('caba:vci_mem_cache'), 15 15 Uses('common:elf_file_loader'), 16 16 ], -
branches/v5/platforms/tsarv5_generic_mmu/soclib.conf
r344 r351 1 1 config.default.toolchain.set("cflags", config.default.toolchain.cflags + ['-DI_WANT_ILLEGAL_VCI']) 2 2 3 config.addDescPath("/Users/alain/soc/tsar-svn-2013") 4 config.addDescPath("/Users/alain/soc/tsar-svn-2013/branches/v5/modules") 5 config.addDescPath("/Users/alain/soc/tsar-svn-2013/branches/v5/communication") 6 7 config.addDescPath("/Users/alain/soc/tsar-svn-2013/trunk/modules") 3 #config.addDescPath("/path/to/tsar/trunk/lib/") 4 #config.addDescPath("/path/to/tsar/trunk/modules/") 5 #config.addDescPath("/path/to/tsar/branches/v5/modules/") 6 #config.addDescPath("/path/to/tsar/branches/v5/communication/") -
branches/v5/platforms/tsarv5_generic_mmu/top.cpp
r344 r351 155 155 156 156 #define BDEV_SECTOR_SIZE 512 157 #define BDEV_IMAGE_NAME " /Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/display/images.raw"158 159 #define NIC_RX_NAME " /Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/nic/rx_data.txt"160 #define NIC_TX_NAME " /Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/nic/tx_data.txt"157 #define BDEV_IMAGE_NAME "giet_vm/display/images.raw" 158 159 #define NIC_RX_NAME "giet_vm/nic/rx_data.txt" 160 #define NIC_TX_NAME "giet_vm/nic/tx_data.txt" 161 161 #define NIC_TIMEOUT 10000 162 162 … … 165 165 //////////////////////i///////////////////////////////////// 166 166 167 #define BOOT_SOFT_NAME " /Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/soft.elf"167 #define BOOT_SOFT_NAME "giet_vm/soft.elf" 168 168 169 169 //////////////////////////////////////////////////////////// -
branches/v5/platforms/tsarv5_generic_mmu/tsarv5_cluster_mmu/caba/metadata/tsarv5_cluster_mmu.sd
r345 r351 16 16 Uses('common:mapping_table'), 17 17 Uses('common:iss2'), 18 Uses('caba:vci_cc_vcache_wrapper _dspin_coherence',18 Uses('caba:vci_cc_vcache_wrapper', 19 19 iss_t = 'common:gdb_iss', 20 20 gdb_iss_t = 'common:mips32el'), 21 Uses('caba:vci_mem_cache _dspin_coherence'),21 Uses('caba:vci_mem_cache'), 22 22 Uses('caba:vci_simple_ram'), 23 23 Uses('caba:vci_xicu'), -
branches/v5/platforms/tsarv5_generic_mmu/tsarv5_cluster_mmu/caba/source/include/tsarv5_cluster_mmu.h
r345 r351 31 31 #include "vci_framebuffer.h" 32 32 #include "vci_multi_dma.h" 33 #include "vci_mem_cache _dspin_coherence.h"34 #include "vci_cc_vcache_wrapper _dspin_coherence.h"33 #include "vci_mem_cache.h" 34 #include "vci_cc_vcache_wrapper.h" 35 35 36 36 namespace soclib { namespace caba { -
branches/v5/platforms/tsarv5_generic_mmu/tsarv5_cluster_mmu/caba/source/src/tsarv5_cluster_mmu.cpp
r345 r351 126 126 swip << "wi_proc_" << x_id << "_" << y_id; 127 127 wi_proc[p] = new VciDspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 128 swip.str().c_str() ); 128 swip.str().c_str(), 129 x_width + y_width ); 129 130 } 130 131 … … 152 153 swtm << "wt_memc_" << x_id << "_" << y_id; 153 154 wt_memc = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>( 154 swtm.str().c_str() ); 155 swtm.str().c_str(), 156 x_width + y_width ); 155 157 156 158 ///////////////////////////////////////////////////////////////////////////// … … 169 171 swtx << "wt_xram_" << x_id << "_" << y_id; 170 172 wt_xram = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>( 171 swtx.str().c_str() ); 173 swtx.str().c_str(), 174 x_width + y_width ); 172 175 173 176 ///////////////////////////////////////////////////////////////////////////// … … 188 191 swtu << "wt_xicu_" << x_id << "_" << y_id; 189 192 wt_xicu = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>( 190 swtu.str().c_str() ); 193 swtu.str().c_str(), 194 x_width + y_width ); 191 195 192 196 ///////////////////////////////////////////////////////////////////////////// … … 206 210 swta << "wt_mdma_" << x_id << "_" << y_id; 207 211 wt_mdma = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>( 208 swtu.str().c_str() ); 212 swtu.str().c_str(), 213 x_width + y_width ); 209 214 210 215 std::ostringstream swia; 211 216 swia << "wi_mdma_" << x_id << "_" << y_id; 212 217 wi_mdma = new VciDspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 213 swtu.str().c_str() ); 218 swtu.str().c_str(), 219 x_width + y_width ); 214 220 215 221 ///////////////////////////////////////////////////////////////////////////// … … 319 325 loader); 320 326 321 wt_brom = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>("wt_brom"); 327 wt_brom = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>("wt_brom", 328 x_width + y_width ); 322 329 323 330 ///////////////////////////////////////////// … … 330 337 xfb, yfb); 331 338 332 wt_fbuf = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>("wt_fbuf"); 339 wt_fbuf = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>("wt_fbuf", 340 x_width + y_width ); 333 341 334 342 ///////////////////////////////////////////// … … 344 352 64); // burst size 345 353 346 wt_bdev = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>("wt_bdev"); 347 wi_bdev = new VciDspinInitiatorWrapper<vci_param,cmd_width,rsp_width>("wi_bdev"); 354 wt_bdev = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>("wt_bdev", 355 x_width + y_width ); 356 wi_bdev = new VciDspinInitiatorWrapper<vci_param,cmd_width,rsp_width>("wi_bdev", 357 x_width + y_width ); 348 358 349 359 ///////////////////////////////////////////// … … 360 370 0 ); // mac_2 address 361 371 362 wt_mnic = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>("wt_mnic"); 372 wt_mnic = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>("wt_mnic", 373 x_width + y_width ); 363 374 364 375 ///////////////////////////////////////////// … … 378 389 vect_names); 379 390 380 wt_mtty = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>("wt_mtty"); 391 wt_mtty = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>("wt_mtty", 392 x_width + y_width ); 381 393 382 394 }
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