Ignore:
Timestamp:
Apr 5, 2013, 7:21:36 PM (12 years ago)
Author:
joannou
Message:

In vci_cc_vcache_wrapper v5

  • added check for p_dspin_in.write in CC_RECEIVE FSM states
  • removed invalid assert
  • removed some traces
File:
1 edited

Legend:

Unmodified
Added
Removed

  • branches/v5/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r351 r355  
    3434#define DEBUG_DCACHE            1
    3535#define DEBUG_ICACHE            1
    36 #define DEBUG_CLEANUP           0
     36#define DEBUG_CLEANUP           1
    3737
    3838namespace soclib {
    … …  
    14881488        if (m_ireq.valid) m_cost_ins_miss_frz++;
    14891489
    1490         // coherence interrupt
    1491         if ( r_cc_receive_icache_req.read() )
    1492         {
    1493             r_icache_fsm = ICACHE_CC_CHECK;
    1494             r_icache_fsm_save = r_icache_fsm.read();
    1495             break;
    1496         }
    1497 
    14981490#ifdef INSTRUMENTATION
    14991491m_cpt_icache_dir_write++;
    … …  
    17361728#endif
    17371729        }
    1738         else if( ((r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
     1730        else if( ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
     1731                 (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
    17391732                 (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
    17401733                 ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
    … …  
    33043297            {
    33053298                pt_updt                = true;
    3306                 r_dcache_vci_cas_old    = pte_flags;
    3307                 r_dcache_vci_cas_new    = pte_flags | PTE_L_MASK;
     3299                r_dcache_vci_cas_old   = pte_flags;
     3300                r_dcache_vci_cas_new   = pte_flags | PTE_L_MASK;
    33083301                pte_flags              = pte_flags | PTE_L_MASK;
    33093302                        r_dcache_tlb_pte_flags = pte_flags;
    … …  
    33153308            {
    33163309                pt_updt                = true;
    3317                 r_dcache_vci_cas_old    = pte_flags;
    3318                 r_dcache_vci_cas_new    = pte_flags | PTE_R_MASK;
     3310                r_dcache_vci_cas_old   = pte_flags;
     3311                r_dcache_vci_cas_new   = pte_flags | PTE_R_MASK;
    33193312                pte_flags              = pte_flags | PTE_R_MASK;
    33203313                        r_dcache_tlb_pte_flags = pte_flags;
    … …  
    38283821                                  &found,
    38293822                                  &cleanup );
     3823
    38303824            if ( found )
    38313825            {
    … …  
    38703864        if ( m_dreq.valid) m_cost_data_miss_frz++;
    38713865
    3872         // coherence request (from CC_RECEIVE FSM)
    3873         if ( r_cc_receive_dcache_req.read() )
    3874         {
    3875             r_dcache_fsm = DCACHE_CC_CHECK;
    3876             r_dcache_fsm_cc_save = r_dcache_fsm.read();
    3877             break;
    3878         }
    3879 
    38803866        size_t  way   = r_dcache_miss_way.read();
    38813867        size_t  set   = r_dcache_miss_set.read();
    … …  
    39273913    {
    39283914        if ( m_dreq.valid) m_cost_data_miss_frz++;
    3929 
    3930 /**/
    3931 #if DEBUG_DCACHE
    3932 if ( m_debug_dcache_fsm )
    3933 {
    3934         std::cout << "  <PROC " << name()
    3935               << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
    3936         std::cout << "  <PROC " << name()
    3937               << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
    3938 }
    3939 #endif
    39403915
    39413916        // coherence request (from CC_RECEIVE FSM)
    … …  
    40133988        if ( m_dreq.valid) m_cost_data_miss_frz++;
    40143989
    4015 /**/
    4016 #if DEBUG_DCACHE
    4017 if ( m_debug_dcache_fsm )
    4018 {
    4019         std::cout << "  <PROC " << name()
    4020               << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
    4021         std::cout << "  <PROC " << name()
    4022               << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
    4023 }
    4024 #endif
    4025 
    40263990        if ( r_vci_rsp_fifo_dcache.rok() )      // one word available
    40273991        {
    … …  
    40654029        if ( m_dreq.valid) m_cost_data_miss_frz++;
    40664030
    4067 /**/
    4068 #if DEBUG_DCACHE
    4069 if ( m_debug_dcache_fsm )
    4070 {
    4071         std::cout << "  <PROC " << name()
    4072               << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
    4073         std::cout << "  <PROC " << name()
    4074               << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
    4075 }
    4076 #endif
    4077 
    40784031        // coherence request (from CC_RECEIVE FSM)
    40794032        if ( r_cc_receive_dcache_req.read() )
    … …  
    44204373#endif
    44214374        }
    4422         else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
     4375        else if( ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
     4376                  (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
    44234377                  (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
    44244378                  ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
    … …  
    53265280        case CC_SEND_CLEANUP_1:
    53275281        {
    5328 /**/
    5329 #if DEBUG_DCACHE
    5330 if ( m_debug_dcache_fsm )
    5331 {
    5332         std::cout << "  <PROC " << name()
    5333               << " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl;
    5334 }
    5335 #endif
    53365282            // wait for the first flit to be consumed
    53375283            if (p_dspin_out.read.read())
    … …  
    53425288        ///////////////////////////
    53435289        case CC_SEND_CLEANUP_2:
    5344 /**/
    5345 #if DEBUG_DCACHE
    5346 if ( m_debug_dcache_fsm )
    5347 {
    5348         std::cout << "  <PROC " << name()
    5349               << " r_dcache_cc_send_nline = " << r_dcache_cc_send_nline.read() << std::endl;
    5350 }
    5351 #endif
    5352         {
    5353             assert( p_dspin_out.read.read() and
    5354                     "The interconnect should accept the second cleanup flit instantly" );
    5355 
     5290        {
    53565291            // wait for the second flit to be consumed
    53575292            if (p_dspin_out.read.read())
    … …  
    54015336        case CC_RECEIVE_IDLE:
    54025337        {
    5403 /**/
    5404 #if DEBUG_DCACHE
    5405 if ( m_debug_dcache_fsm )
    5406 {
    5407         std::cout << "  <PROC " << name()
    5408               << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
    5409         std::cout << "  <PROC " << name()
    5410               << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
    5411 }
    5412 #endif
    54135338            // a coherence request has arrived
    54145339            if (p_dspin_in.write.read())
    … …  
    54815406        case CC_RECEIVE_BRDCAST_HEADER:
    54825407        {
    5483 /**/
    5484 #if DEBUG_DCACHE
    5485 if ( m_debug_dcache_fsm )
    5486 {
    5487         std::cout << "  <PROC " << name()
    5488               << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
    5489         std::cout << "  <PROC " << name()
    5490               << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
    5491 }
    5492 #endif
    54935408            // no actual data in the HEADER, just skip to second flit
    54945409            r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
    … …  
    54985413        case CC_RECEIVE_BRDCAST_NLINE:
    54995414        {
    5500 /**/
    5501 #if DEBUG_DCACHE
    5502 if ( m_debug_dcache_fsm )
    5503 {
    5504         std::cout << "  <PROC " << name()
    5505               << " r_cc_receive_dcache_req = " << r_cc_receive_dcache_req.read() << std::endl;
    5506         std::cout << "  <PROC " << name()
    5507               << " r_dcache_miss_inval = " << r_dcache_miss_inval.read() << std::endl;
    5508 }
    5509 #endif
    55105415            // initialize dspin received data
    55115416            uint64_t receive_data = p_dspin_in.data.read();
    … …  
    55145419            // not to actually post a request to an available cache => need a
    55155420            // flip_flop to check that ?
    5516             if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
     5421            if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
    55175422            {
    55185423                // request dcache to handle the BROADCAST
    … …  
    55595464            uint64_t receive_data = p_dspin_in.data.read();
    55605465            // for data INVAL, wait for dcache to take the request
    5561             if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
     5466            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
    55625467            {
    55635468                // request dcache to handle the INVAL
    … …  
    55705475            }
    55715476            // for ins INVAL, wait for icache to take the request
    5572             if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
     5477            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
    55735478            {
    55745479                // request icache to handle the INVAL
    … …  
    56145519            // for data INVAL, wait for dcache to take the request and fifo to
    56155520            // be empty
    5616             if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty())
     5521            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
    56175522            {
    56185523                r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
    … …  
    56255530            // for ins INVAL, wait for icache to take the request and fifo to be
    56265531            // empty
    5627             if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty())
     5532            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and r_cc_receive_updt_fifo_be.empty() and (p_dspin_in.write.read()))
    56285533            {
    56295534                r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
    … …  
    56415546        case CC_RECEIVE_UPDT_DATA:
    56425547        {
    5643             if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
     5548            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
    56445549                r_cc_receive_dcache_req = true;
    5645             if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
     5550            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()) and (p_dspin_in.write.read()))
    56465551                r_cc_receive_icache_req = true;
    56475552
    … …  
    56495554            uint64_t receive_data = p_dspin_in.data.read();
    56505555            // wait for the fifo
    5651             if (r_cc_receive_updt_fifo_be.wok())
     5556            if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_in.write.read()))
    56525557            {
    56535558                cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
    … …  
    59805885            p_dspin_out.data  = dspin_send_data;
    59815886            p_dspin_out.write = true;
     5887
    59825888            break;
    59835889        }
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