Changeset 379
- Timestamp:
- Apr 20, 2013, 6:32:32 PM (12 years ago)
- Location:
- trunk/platforms/tsar_generic_xbar
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_xbar/soclib.conf
r378 r379 1 config.default.toolchain.set("cflags", config.default.toolchain.cflags + ['-DI_WANT_ILLEGAL_VCI'])2 1 3 config.addDescPath("/ dsk/l1/misc/joannou/tsar/trunk/")2 config.addDescPath("/Users/alain/soc/tsar-trunk-svn-2013/") -
trunk/platforms/tsar_generic_xbar/top.cpp
r378 r379 16 16 // - It uses the vci_mem_cache 17 17 // - It contains one vci_xicu and one vci_multi_dma per cluster. 18 // - It contains one vci_simple ram per cluster to model the L3 cache. 18 19 // 19 20 // All clusters are identical, but the cluster containing address … … 27 28 // It is build with one single component implementing a cluster: 28 29 // The Tsarv4ClusterMmu component is defined in files 29 // tsar v4_cluster_mmu.* (with * = cpp, h, sd)30 // tsar_xbar_cluster.* (with * = cpp, h, sd) 30 31 // 31 32 // The IRQs are connected to XICUs as follow: … … 157 158 #define BDEV_IMAGE_NAME "giet_vm/display/images.raw" 158 159 159 #define NIC_RX_NAME "giet_vm/nic/rx_ data.txt"160 #define NIC_TX_NAME "giet_vm/nic/tx_ data.txt"160 #define NIC_RX_NAME "giet_vm/nic/rx_packets.txt" 161 #define NIC_TX_NAME "giet_vm/nic/tx_packets.txt" 161 162 #define NIC_TIMEOUT 10000 162 163 … … 426 427 } 427 428 std::cout << maptabd << std::endl; 428 429 /*430 WE DONT NEED any COHERENCE MAPPING TABLE, AS THE DIRECT NETWORK431 USES DIRECT ADRESSING (XID,YID,LID)432 433 // coherence network434 // - tgtid_c_proc = srcid_c_proc = local procid435 // - tgtid_c_memc = srcid_c_memc = NB_PROCS_MAX436 MappingTable maptabc(address_width,437 IntTab(x_width + y_width, srcid_width - x_width - y_width),438 IntTab(x_width + y_width, srcid_width - x_width - y_width),439 0x00FF0000);440 441 for (size_t x = 0; x < CLUSTER_X; x++)442 {443 for (size_t y = 0; y < CLUSTER_Y; y++)444 {445 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width);446 447 // cleanup requests must be routed to the memory cache448 std::ostringstream sh;449 sh << "c_seg_memc_" << x << "_" << y;450 maptabc.add(Segment(sh.str(), (NB_PROCS_MAX << (address_width - srcid_width)) + offset,451 0x10, IntTab(cluster(x,y), NB_PROCS_MAX), false));452 453 // update & invalidate requests must be routed to the proper processor454 for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++)455 {456 std::ostringstream sp;457 sp << "c_seg_proc_" << x << "_" << y << "_" << p;458 maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset ,459 0x10 , IntTab(cluster(x,y), p) , false));460 }461 }462 }463 std::cout << maptabc << std::endl;464 465 */466 429 467 430 // external network … … 601 564 ); 602 565 566 std::cout << std::endl; 603 567 std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; 568 std::cout << std::endl; 569 604 570 #if USE_OPENMP 605 571 } // end critical … … 796 762 clusters[1][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_1"); 797 763 */ 764 // trace proc[debug_proc_id] 765 if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) 766 { 767 size_t l = debug_proc_id % (CLUSTER_X * CLUSTER_Y) ; 768 size_t y = (debug_proc_id / NB_PROCS_MAX) % CLUSTER_Y ; 769 size_t x = debug_proc_id / (CLUSTER_Y * NB_PROCS_MAX) ; 770 771 std::ostringstream signame; 772 signame << "VCI signal PROC_" << x << "_" << y << "_" << l; 773 774 clusters[x][y]->proc[l]->print_trace(); 775 clusters[x][y]->signal_vci_ini_proc[l].print_trace("signame"); 776 } 798 777 /* 799 // trace proc[debug_proc_id] 800 if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) 801 { 802 size_t proc_x = debug_proc_id / CLUSTER_Y; 803 size_t proc_y = debug_proc_id % CLUSTER_Y; 804 805 clusters[proc_x][proc_y]->proc[0]->print_trace(); 806 clusters[proc_x][proc_y]->signal_vci_ini_proc[0].print_trace("proc_0"); 807 } 808 809 // trace memc[debug_memc_id] 810 if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) ) 811 { 812 size_t memc_x = debug_memc_id / CLUSTER_Y; 813 size_t memc_y = debug_memc_id % CLUSTER_Y; 814 815 clusters[memc_x][memc_y]->memc->print_trace(); 816 clusters[memc_x][memc_y]->signal_vci_tgt_memc.print_trace("memc"); 817 } 778 // trace memc[debug_memc_id] 779 if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) ) 780 { 781 size_t x = debug_memc_id / CLUSTER_Y; 782 size_t y = debug_memc_id % CLUSTER_Y; 783 784 std::ostringstream signame; 785 signame << "VCI signal MEMC_" << x << "_" << y; 786 787 clusters[memc_x][memc_y]->memc->print_trace(); 788 clusters[memc_x][memc_y]->signal_vci_tgt_memc.print_trace("signame"); 789 } 818 790 */ 819 // clusters[0][0]->signal_vci_tgt_xicu.print_trace("xicu_0_0"); 820 // clusters[0][1]->signal_vci_tgt_xicu.print_trace("xicu_0_1"); 821 // clusters[1][0]->signal_vci_tgt_xicu.print_trace("xicu_1_0"); 822 // clusters[1][1]->signal_vci_tgt_xicu.print_trace("xicu_1_1"); 823 824 // if ( clusters[1][1]->signal_irq_mdma[0].read() ) 825 // std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl; 826 // if ( clusters[1][1]->signal_proc_it[0].read() ) 827 // std::cout << " IRQ_PROC_1_1 activated" << std::endl << std::endl; 828 829 // trace ioc component 830 // size_t io_x = cluster_io_id / CLUSTER_Y; 831 // size_t io_y = cluster_io_id % CLUSTER_Y; 832 // clusters[io_x][io_y]->bdev->print_trace(); 833 // clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("bdev_tgt "); 834 // clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("bdev_ini "); 835 836 // clusters[1][1]->mdma->print_trace(); 837 // clusters[1][1]->signal_vci_tgt_mdma.print_trace("mdma_1_1_tgt "); 838 // clusters[1][1]->signal_vci_ini_mdma.print_trace("mdma_1_1_ini "); 839 791 // trace external peripherals 792 size_t io_x = cluster_io_id / CLUSTER_Y; 793 size_t io_y = cluster_io_id % CLUSTER_Y; 794 795 clusters[io_x][io_y]->signal_vci_tgt_mtty.print_trace("VCI signal TTY"); 796 /* 797 clusters[io_x][io_y]->bdev->print_trace(); 798 clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("VCI signal BDEV_TGT"); 799 clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("VCI signal BDEV_INI"); 800 */ 840 801 } 841 802 -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp
r378 r379 102 102 { 103 103 std::ostringstream sproc; 104 sproc << "proc_" << x_id << "_" << y_id << "_" <<p;104 sproc << "proc_" << p; 105 105 proc[p] = new VciCcVCacheWrapper<vci_param, iss_t>( 106 106 sproc.str().c_str(), … … 133 133 std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; 134 134 135 std::ostringstream smemc;136 smemc << "memc_" << x_id << "_" << y_id;137 135 memc = new VciMemCache<vci_param>( 138 smemc.str().c_str(),136 "memc", 139 137 mtd, // Mapping Table direct space 140 138 mtx, // Mapping Table external space … … 150 148 memc_debug_ok ); 151 149 152 std::ostringstream swtm;153 swtm << "wt_memc_" << x_id << "_" << y_id;154 150 wt_memc = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>( 155 swtm.str().c_str(),151 "wt_memc", 156 152 x_width + y_width + l_width); 157 153 … … 159 155 std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; 160 156 161 std::ostringstream sxram;162 sxram << "xram_" << x_id << "_" << y_id;163 157 xram = new VciSimpleRam<vci_param>( 164 sxram.str().c_str(),158 "xram", 165 159 IntTab(cluster_id), 166 160 mtx, 167 161 loader, 168 162 xram_latency); 169 /* 170 std::ostringstream swtx; 171 swtx << "wt_xram_" << x_id << "_" << y_id; 172 wt_xram = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>( 173 swtx.str().c_str(), 174 x_width + y_width ); 175 */ 163 176 164 ///////////////////////////////////////////////////////////////////////////// 177 165 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 178 166 179 std::ostringstream sicu;180 sicu << "xicu_" << x_id << "_" << y_id;181 167 xicu = new VciXicu<vci_param>( 182 sicu.str().c_str(),168 "xicu", 183 169 mtd, // mapping table 184 170 IntTab(cluster_id, tgtid_xicu), // TGTID_D … … 188 174 nb_procs); // number of output IRQs 189 175 190 std::ostringstream swtu;191 swtu << "wt_xicu_" << x_id << "_" << y_id;192 176 wt_xicu = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>( 193 swtu.str().c_str(),177 "wt_xicu", 194 178 x_width + y_width + l_width); 195 179 … … 197 181 std::cout << " - building mdma_" << x_id << "_" << y_id << std::endl; 198 182 199 std::ostringstream sdma;200 sdma << "dma_" << x_id << "_" << y_id;201 183 mdma = new VciMultiDma<vci_param>( 202 sdma.str().c_str(),184 "mdma", 203 185 mtd, 204 186 IntTab(cluster_id, nb_procs), // SRCID 205 187 IntTab(cluster_id, tgtid_mdma), // TGTID 206 188 64, // burst size 207 nb_dmas); // number of IRQs 208 209 std::ostringstream swta; 210 swta << "wt_mdma_" << x_id << "_" << y_id; 189 nb_dmas); // number of IRQs 190 211 191 wt_mdma = new VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>( 212 swtu.str().c_str(), 213 x_width + y_width + l_width); 214 215 std::ostringstream swia; 216 swia << "wi_mdma_" << x_id << "_" << y_id; 192 "wt_mdma", 193 x_width + y_width + l_width); 194 217 195 wi_mdma = new VciDspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 218 swtu.str().c_str(),196 "wi_mdma", 219 197 x_width + y_width + l_width); 220 198 … … 230 208 } 231 209 232 std::ostringstream sdcmd;233 sdcmd << "xbar_cmd_d_" << x_id << "_" << y_id;234 210 xbar_cmd_d = new DspinLocalCrossbar<cmd_width>( 235 sdcmd.str().c_str(),211 "xbar_cmd_d", 236 212 mtd, // mapping table 237 213 x_id, y_id, // cluster coordinates … … 246 222 std::cout << " - building xbar_rsp_d_" << x_id << "_" << y_id << std::endl; 247 223 248 std::ostringstream sdrsp;249 sdrsp << "xbar_rsp_d_" << x_id << "_" << y_id;250 224 xbar_rsp_d = new DspinLocalCrossbar<rsp_width>( 251 sdrsp.str().c_str(),225 "xbar_rsp_d", 252 226 mtd, // mapping table 253 227 x_id, y_id, // cluster coordinates … … 262 236 std::cout << " - building xbar_m2p_c" << x_id << "_" << y_id << std::endl; 263 237 264 std::ostringstream sccmd;265 sccmd << "xbar_m2p_c_" << x_id << "_" << y_id;266 238 xbar_m2p_c = new DspinLocalCrossbar<cmd_width>( 267 sccmd.str().c_str(),239 "xbar_m2p_c", 268 240 mtd, // mapping table 269 241 x_id, y_id, // cluster coordinates … … 278 250 std::cout << " - building xbar_p2m_c_" << x_id << "_" << y_id << std::endl; 279 251 280 std::ostringstream scrsp;281 scrsp << "xbar_p2m_c_" << x_id << "_" << y_id;282 252 xbar_p2m_c = new DspinLocalCrossbar<rsp_width>( 283 scrsp.str().c_str(),253 "xbar_p2m_c", 284 254 mtd, // mapping table 285 255 x_id, y_id, // cluster coordinates 286 x_width, y_width, 0, // l_width unused on the network going from proc to memc (only X and Y identifie the cluster)256 x_width, y_width, 0, // l_width unused on p2m network 287 257 nb_procs, // number of local sources 288 258 1, // number of local dests 289 259 2, 2, // fifo depths 290 260 false, // don't use local routing table 291 false ); // no broacast 261 false ); // no broacast 292 262 293 263 ///////////////////////////////////////////////////////////////////////////// 294 264 std::cout << " - building router_cmd_" << x_id << "_" << y_id << std::endl; 295 265 296 std::ostringstream scmdr;297 scmdr << "router_cmd_" << x_id << "_" << y_id;298 266 router_cmd = new VirtualDspinRouter<cmd_width>( 299 scmdr.str().c_str(),267 "router_cmd", 300 268 x_id,y_id, // coordinate in the mesh 301 269 x_width, y_width, // x & y fields width … … 305 273 std::cout << " - building router_rsp_" << x_id << "_" << y_id << std::endl; 306 274 307 std::ostringstream srspr;308 srspr << "router_rsp_" << x_id << "_" << y_id;309 275 router_rsp = new VirtualDspinRouter<rsp_width>( 310 srspr.str().c_str(),276 "router_rsp", 311 277 x_id,y_id, // coordinates in mesh 312 278 x_width, y_width, // x & y fields width
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