Changeset 385 for trunk/modules/vci_mem_cache/caba/source/include
- Timestamp:
- May 1, 2013, 4:13:23 PM (12 years ago)
- Location:
- trunk/modules/vci_mem_cache/caba/source/include
- Files:
-
- 4 edited
-
mem_cache_directory.h (modified) (6 diffs)
-
update_tab.h (modified) (1 diff)
-
vci_mem_cache.h (modified) (15 diffs)
-
xram_transaction.h (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
r307 r385 40 40 //////////////////////////////////////////////////////////////////////// 41 41 class Owner{ 42 typedef uint32_t size_t;43 42 44 43 public: … … 92 91 93 92 typedef uint32_t tag_t; 94 typedef uint32_t size_t;95 93 96 94 public: … … 165 163 void print() 166 164 { 167 std::cout << "Valid = " << valid << " ; IS COUNT = " << is_cnt << " ; Dirty = " << dirty << " ; Lock = " 168 << lock 165 std::cout << "Valid = " << valid 166 << " ; IS COUNT = " << is_cnt 167 << " ; Dirty = " << dirty 168 << " ; Lock = " << lock 169 169 << " ; Tag = " << std::hex << tag << std::dec 170 170 << " ; Count = " << count … … 187 187 typedef uint32_t data_t; 188 188 typedef uint32_t tag_t; 189 typedef uint32_t size_t;190 189 191 190 private: … … 408 407 /////////////////////////////////////////////////////////////////////// 409 408 class HeapEntry{ 410 typedef uint32_t size_t;411 409 412 410 public: … … 472 470 //////////////////////////////////////////////////////////////////////// 473 471 class HeapDirectory{ 474 typedef uint32_t size_t;475 472 476 473 private: -
trunk/modules/vci_mem_cache/caba/source/include/update_tab.h
r307 r385 126 126 class UpdateTab{ 127 127 128 typedef uint32_t size_t;129 128 typedef sc_dt::sc_uint<40> addr_t; 130 129 -
trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r362 r385 58 58 using namespace sc_core; 59 59 60 template<typename vci_param> 60 template<typename vci_param_int, 61 typename vci_param_ext, 62 size_t dspin_in_width, 63 size_t dspin_out_width> 61 64 class VciMemCache 62 65 : public soclib::caba::BaseModule 63 66 { 64 typedef sc_dt::sc_uint<40> addr_t; 65 typedef typename vci_param::fast_addr_t vci_addr_t; 67 typedef typename vci_param_int::fast_addr_t addr_t; 68 69 typedef typename sc_dt::sc_uint<64> wide_data_t; 70 66 71 typedef uint32_t data_t; 67 72 typedef uint32_t tag_t; 68 typedef uint32_t size_t;69 73 typedef uint32_t be_t; 70 74 typedef uint32_t copy_t; … … 343 347 344 348 bool m_monitor_ok; 345 vci_addr_tm_monitor_base;346 vci_addr_tm_monitor_length;349 addr_t m_monitor_base; 350 addr_t m_monitor_length; 347 351 348 352 // instrumentation counters … … 373 377 374 378 public: 375 sc_in<bool> p_clk;376 sc_in<bool> p_resetn;377 soclib::caba::VciTarget<vci_param >p_vci_tgt;378 soclib::caba::VciInitiator<vci_param >p_vci_ixr;379 soclib::caba::DspinInput< 33>p_dspin_in;380 soclib::caba::DspinOutput< 40>p_dspin_out;379 sc_in<bool> p_clk; 380 sc_in<bool> p_resetn; 381 soclib::caba::VciTarget<vci_param_int> p_vci_tgt; 382 soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr; 383 soclib::caba::DspinInput<dspin_in_width> p_dspin_in; 384 soclib::caba::DspinOutput<dspin_out_width> p_dspin_out; 381 385 382 386 VciMemCache( … … 401 405 void print_stats(); 402 406 void print_trace(); 403 void copies_monitor( vci_addr_t addr);404 void start_monitor( vci_addr_t addr, vci_addr_t length);407 void copies_monitor(addr_t addr); 408 void start_monitor(addr_t addr, addr_t length); 405 409 void stop_monitor(); 406 410 … … 409 413 void transition(); 410 414 void genMoore(); 411 void check_monitor( const char *buf, vci_addr_t addr, data_t data); 412 void check_monitor_read( const char *buf, vci_addr_t addr); 415 void check_monitor( const char *buf, addr_t addr, data_t data, bool read); 413 416 414 417 // Component attributes … … 436 439 < 32 , // number of slots 437 440 4096, // number of processors in the system 438 8000, // registratioçn life span (in # of LL operations) 439 typename vci_param::fast_addr_t > // address type 440 m_llsc_table; // ll/sc global registration table 441 8000, // registration life (# of LL operations) 442 addr_t > m_llsc_table; // ll/sc global registration table 441 443 442 444 // adress masks 443 const soclib::common::AddressMaskingTable< vci_addr_t> m_x;444 const soclib::common::AddressMaskingTable< vci_addr_t> m_y;445 const soclib::common::AddressMaskingTable< vci_addr_t> m_z;446 const soclib::common::AddressMaskingTable< vci_addr_t> m_nline;445 const soclib::common::AddressMaskingTable<addr_t> m_x; 446 const soclib::common::AddressMaskingTable<addr_t> m_y; 447 const soclib::common::AddressMaskingTable<addr_t> m_z; 448 const soclib::common::AddressMaskingTable<addr_t> m_nline; 447 449 448 450 // broadcast address … … 454 456 455 457 // Fifo between TGT_CMD fsm and READ fsm 456 GenericFifo< uint64_t>m_cmd_read_addr_fifo;458 GenericFifo<addr_t> m_cmd_read_addr_fifo; 457 459 GenericFifo<size_t> m_cmd_read_length_fifo; 458 460 GenericFifo<size_t> m_cmd_read_srcid_fifo; … … 461 463 462 464 // Fifo between TGT_CMD fsm and WRITE fsm 463 GenericFifo< uint64_t>m_cmd_write_addr_fifo;465 GenericFifo<addr_t> m_cmd_write_addr_fifo; 464 466 GenericFifo<bool> m_cmd_write_eop_fifo; 465 467 GenericFifo<size_t> m_cmd_write_srcid_fifo; … … 470 472 471 473 // Fifo between TGT_CMD fsm and CAS fsm 472 GenericFifo< uint64_t>m_cmd_cas_addr_fifo;474 GenericFifo<addr_t> m_cmd_cas_addr_fifo; 473 475 GenericFifo<bool> m_cmd_cas_eop_fifo; 474 476 GenericFifo<size_t> m_cmd_cas_srcid_fifo; … … 504 506 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 505 507 sc_signal<bool> r_read_last_free; // Last free entry 506 sc_signal<typename vci_param::fast_addr_t> 507 r_read_ll_key; // LL key returned by the llsc_global_table 508 sc_signal<addr_t> r_read_ll_key; // LL key from the llsc_global_table 508 509 509 510 // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) … … 520 521 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response 521 522 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response 522 sc_signal<typename vci_param::fast_addr_t> 523 r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table 523 sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table 524 524 525 525 /////////////////////////////////////////////////////////////// … … 578 578 GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type 579 579 GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids 580 580 581 #if L1_MULTI_CACHE 581 582 GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids … … 703 704 GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type 704 705 GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids 706 705 707 #if L1_MULTI_CACHE 706 708 GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids … … 749 751 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response 750 752 sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester 751 sc_signal<typename vci_param::fast_addr_t> 752 r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table 753 sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table 753 754 754 755 // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches) … … 759 760 GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type 760 761 GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids 762 761 763 #if L1_MULTI_CACHE 762 764 GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids -
trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h
r362 r385 14 14 15 15 class TransactionTabEntry { 16 typedef uint32_t size_t; 16 typedef sc_dt::sc_uint<64> wide_data_t; 17 typedef sc_dt::sc_uint<40> addr_t; 17 18 typedef uint32_t data_t; 18 typedef sc_dt::sc_uint<40> addr_t;19 19 typedef uint32_t be_t; 20 20 … … 138 138 //////////////////////////////////////////////////////////////////////// 139 139 class TransactionTab{ 140 typedef uint32_t size_t;141 typedef uint32_t data_t;142 typedef sc_dt::sc_uint<40> addr_t;143 typedef uint32_t be_t;140 typedef sc_dt::sc_uint<64> wide_data_t; 141 typedef sc_dt::sc_uint<40> addr_t; 142 typedef uint32_t data_t; 143 typedef uint32_t be_t; 144 144 145 145 private: … … 368 368 369 369 ///////////////////////////////////////////////////////////////////// 370 // The write_rsp() function writes a word of the response to an371 // XRAM read transaction.370 // The write_rsp() function writes two 32 bits words of the response 371 // to a XRAM read transaction. 372 372 // The BE field in TRT is taken into account. 373 373 // Arguments : 374 374 // - index : the index of the transaction in the transaction tab 375 375 // - word_index : the index of the data in the line 376 // - data : the data to write376 // - data : a 64 bits value 377 377 // - error : invalid data 378 378 ///////////////////////////////////////////////////////////////////// 379 void write_rsp(const size_t index, 380 const size_t word, 381 const data_t data, 382 const bool rerror) 383 { 379 void write_rsp(const size_t index, 380 const size_t word, 381 const wide_data_t data, 382 const bool rerror) 383 { 384 data_t value; 385 data_t mask; 386 384 387 assert( (index < size_tab) 385 388 && "Selected entry out of range in write_rsp() Transaction Tab"); … … 391 394 && "Selected entry is not an XRAM read transaction in write_rsp()"); 392 395 393 data_t mask = be_to_mask(tab[index].wdata_be[word]); 394 tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask); 396 // first 32 bits word 397 value = (data_t)data; 398 mask = be_to_mask(tab[index].wdata_be[word]); 399 tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (value & ~mask); 400 401 // second 32 bits word 402 value = (data_t)(data>>32); 403 mask = be_to_mask(tab[index].wdata_be[word+1]); 404 tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask); 405 406 // error update 395 407 tab[index].rerror |= rerror; 396 408 }
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