Changeset 395 for trunk/modules/vci_mem_cache/caba/source/include
- Timestamp:
- May 28, 2013, 9:56:06 AM (12 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r385 r395 52 52 #include "dspin_dhccp_param.h" 53 53 54 #define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab 55 #define UPDATE_TAB_LINES 4 // Number of lines in the update tab 54 #define TRT_ENTRIES 4 // Number of entries in TRT 55 #define UPT_ENTRIES 4 // Number of entries in UPT 56 #define HEAP_ENTRIES 1024 // Number of entries in HEAP 56 57 57 58 namespace soclib { namespace caba { 59 58 60 using namespace sc_core; 59 61 … … 83 85 84 86 /* States of the TGT_RSP fsm */ 85 enum tgt_rsp_fsm_state_e{ 87 enum tgt_rsp_fsm_state_e 88 { 86 89 TGT_RSP_READ_IDLE, 87 90 TGT_RSP_WRITE_IDLE, … … 99 102 100 103 /* States of the DSPIN_TGT fsm */ 101 enum cc_receive_fsm_state_e{ 104 enum cc_receive_fsm_state_e 105 { 102 106 CC_RECEIVE_IDLE, 103 107 CC_RECEIVE_CLEANUP, … … 106 110 107 111 /* States of the CC_SEND fsm */ 108 enum cc_send_fsm_state_e{ 112 enum cc_send_fsm_state_e 113 { 109 114 CC_SEND_XRAM_RSP_IDLE, 110 115 CC_SEND_WRITE_IDLE, … … 130 135 131 136 /* States of the MULTI_ACK fsm */ 132 enum multi_ack_fsm_state_e{ 137 enum multi_ack_fsm_state_e 138 { 133 139 MULTI_ACK_IDLE, 134 140 MULTI_ACK_UPT_LOCK, … … 138 144 139 145 /* States of the READ fsm */ 140 enum read_fsm_state_e{ 146 enum read_fsm_state_e 147 { 141 148 READ_IDLE, 142 149 READ_DIR_REQ, … … 155 162 156 163 /* States of the WRITE fsm */ 157 enum write_fsm_state_e{ 164 enum write_fsm_state_e 165 { 158 166 WRITE_IDLE, 159 167 WRITE_NEXT, … … 181 189 182 190 /* States of the IXR_RSP fsm */ 183 enum ixr_rsp_fsm_state_e{ 191 enum ixr_rsp_fsm_state_e 192 { 184 193 IXR_RSP_IDLE, 185 194 IXR_RSP_ACK, … … 189 198 190 199 /* States of the XRAM_RSP fsm */ 191 enum xram_rsp_fsm_state_e{ 200 enum xram_rsp_fsm_state_e 201 { 192 202 XRAM_RSP_IDLE, 193 203 XRAM_RSP_TRT_COPY, … … 208 218 209 219 /* States of the IXR_CMD fsm */ 210 enum ixr_cmd_fsm_state_e{ 220 enum ixr_cmd_fsm_state_e 221 { 211 222 IXR_CMD_READ_IDLE, 212 223 IXR_CMD_WRITE_IDLE, 213 224 IXR_CMD_CAS_IDLE, 214 225 IXR_CMD_XRAM_IDLE, 215 IXR_CMD_READ _NLINE,216 IXR_CMD_WRITE _NLINE,217 IXR_CMD_CAS _NLINE,218 IXR_CMD_XRAM _DATA226 IXR_CMD_READ, 227 IXR_CMD_WRITE, 228 IXR_CMD_CAS, 229 IXR_CMD_XRAM 219 230 }; 220 231 221 232 /* States of the CAS fsm */ 222 enum cas_fsm_state_e{ 233 enum cas_fsm_state_e 234 { 223 235 CAS_IDLE, 224 236 CAS_DIR_REQ, … … 245 257 246 258 /* States of the CLEANUP fsm */ 247 enum cleanup_fsm_state_e{ 259 enum cleanup_fsm_state_e 260 { 248 261 CLEANUP_IDLE, 249 262 CLEANUP_GET_NLINE, … … 264 277 265 278 /* States of the ALLOC_DIR fsm */ 266 enum alloc_dir_fsm_state_e{ 279 enum alloc_dir_fsm_state_e 280 { 267 281 ALLOC_DIR_RESET, 268 282 ALLOC_DIR_READ, … … 274 288 275 289 /* States of the ALLOC_TRT fsm */ 276 enum alloc_trt_fsm_state_e{ 290 enum alloc_trt_fsm_state_e 291 { 277 292 ALLOC_TRT_READ, 278 293 ALLOC_TRT_WRITE, … … 283 298 284 299 /* States of the ALLOC_UPT fsm */ 285 enum alloc_upt_fsm_state_e{ 300 enum alloc_upt_fsm_state_e 301 { 286 302 ALLOC_UPT_WRITE, 287 303 ALLOC_UPT_XRAM_RSP, … … 292 308 293 309 /* States of the ALLOC_HEAP fsm */ 294 enum alloc_heap_fsm_state_e{ 310 enum alloc_heap_fsm_state_e 311 { 295 312 ALLOC_HEAP_RESET, 296 313 ALLOC_HEAP_READ, … … 386 403 VciMemCache( 387 404 sc_module_name name, // Instance Name 388 const soclib::common::MappingTable &mtp, // Mapping table fordirect network389 const soclib::common::MappingTable &mtx, // Mapping table forexternal network405 const soclib::common::MappingTable &mtp, // Mapping table direct network 406 const soclib::common::MappingTable &mtx, // Mapping table external network 390 407 const soclib::common::IntTab &srcid_x, // global index on external network 391 408 const soclib::common::IntTab &tgtid_d, // global index on direct network … … 395 412 const size_t nwords, // Number of words per line 396 413 const size_t max_copies, // max number of copies in heap 397 const size_t heap_size= 1024, // number of heap entries398 const size_t trt_lines=TR ANSACTION_TAB_LINES,399 const size_t upt_lines=UP DATE_TAB_LINES,414 const size_t heap_size=HEAP_ENTRIES, 415 const size_t trt_lines=TRT_ENTRIES, 416 const size_t upt_lines=UPT_ENTRIES, 400 417 const size_t debug_start_cycle=0, 401 418 const bool debug_ok=false ); … … 449 466 450 467 // broadcast address 451 uint32_t m_broadcast_address;468 uint32_t m_broadcast_boundaries; 452 469 453 470 //////////////////////////////////////////////////
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