Changeset 389 for trunk/platforms/tsar_generic_xbar
- Timestamp:
- May 16, 2013, 3:32:38 PM (12 years ago)
- Location:
- trunk/platforms/tsar_generic_xbar
- Files:
-
- 6 edited
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Makefile (modified) (1 diff)
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top.cpp (modified) (13 diffs)
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top.desc (modified) (1 diff)
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tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (modified) (1 diff)
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tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (modified) (5 diffs)
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tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (modified) (22 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/platforms/tsar_generic_xbar/Makefile
r378 r389 1 1 simul.x: top.cpp top.desc 2 soclib-cc - P -p top.desc -I. -o simul.x2 soclib-cc -j8 -P -p top.desc -I. -o simul.x 3 3 4 4 clean: -
trunk/platforms/tsar_generic_xbar/top.cpp
r379 r389 116 116 #define rsp_width 33 117 117 118 ///////////////////////////////////////////////////////////119 // VCI parameters120 ///////////////////////////////////////////////////////////121 122 #define cell_width 4123 #define address_width 32124 #define plen_width 8125 #define error_width 2126 #define clen_width 1127 #define rflag_width 1128 #define srcid_width 14129 #define pktid_width 4130 #define trdid_width 4131 #define wrplen_width 1132 133 118 //////////////////////////////////////////////////////////// 134 119 // Main Hardware Parameters values … … 357 342 #endif 358 343 359 // Define VCI parameters360 typedef soclib::caba::VciParams<cell_width,361 plen_width,362 address_width,363 error_width,364 clen_width,365 rflag_width,366 srcid_width,367 pktid_width,368 trdid_width,369 wrplen_width> vci_param;370 371 344 // Define parameters depending on mesh size 372 345 size_t cluster_io_id; … … 378 351 else if (CLUSTER_X <= 4) x_width = 2; 379 352 else if (CLUSTER_X <= 8) x_width = 3; 380 else 353 else x_width = 4; 381 354 382 355 if (CLUSTER_Y == 1) y_width = 0; … … 384 357 else if (CLUSTER_Y <= 4) y_width = 2; 385 358 else if (CLUSTER_Y <= 8) y_width = 3; 386 else 359 else y_width = 4; 387 360 388 361 cluster_io_id = 0xBF >> (8 - x_width - y_width); … … 448 421 /////////////////// 449 422 450 sc_clock signal_clk("clk");423 sc_clock signal_clk("clk"); 451 424 sc_signal<bool> signal_resetn("resetn"); 452 425 … … 501 474 //////////////////////////// 502 475 503 TsarXbarCluster<vci_param, proc_iss, cmd_width, rsp_width>* clusters[CLUSTER_X][CLUSTER_Y]; 476 TsarXbarCluster< 477 proc_iss, cmd_width, rsp_width 478 > * clusters[CLUSTER_X][CLUSTER_Y]; 504 479 505 480 #if USE_OPENMP … … 517 492 { 518 493 #endif 494 bool is_io_cluster = (cluster(x,y) == cluster_io_id); 495 519 496 std::ostringstream sc; 520 497 sc << "cluster_" << x << "_" << y; 521 clusters[x][y] = new TsarXbarCluster<vci_param, proc_iss, cmd_width, rsp_width> 498 clusters[x][y] = new TsarXbarCluster< 499 proc_iss, cmd_width, rsp_width 500 > 522 501 ( 523 502 sc.str().c_str(), 524 NB_PROCS_MAX, 525 NB_TTYS, 526 NB_DMAS_MAX, 527 x, 528 y, 529 cluster(x,y), 530 maptabd, 531 maptabx, 532 x_width, 533 y_width, 534 srcid_width - x_width - y_width, // l_id width, 535 MEMC_TGTID, 536 XICU_TGTID, 537 CDMA_TGTID, 538 FBUF_TGTID, 539 MTTY_TGTID, 540 BROM_TGTID, 541 MNIC_TGTID, 542 BDEV_TGTID, 543 MEMC_WAYS, 544 MEMC_SETS, 545 L1_IWAYS, 546 L1_ISETS, 547 L1_DWAYS, 548 L1_DSETS, 549 XRAM_LATENCY, 550 (cluster(x,y) == cluster_io_id), 551 FBUF_X_SIZE, 552 FBUF_Y_SIZE, 553 disk_name, 554 BDEV_SECTOR_SIZE, 555 NB_NICS, 556 nic_rx_name, 557 nic_tx_name, 558 NIC_TIMEOUT, 559 loader, 503 NB_PROCS_MAX , NB_TTYS , NB_DMAS_MAX , // cluster params 504 x , y , cluster(x,y), // mesh coordinates 505 maptabd , maptabx , // mapping tables 506 x_width , y_width , srcid_width - x_width - y_width, // srcid width, 507 MEMC_TGTID , XICU_TGTID , CDMA_TGTID , // 508 FBUF_TGTID , MTTY_TGTID , BROM_TGTID , // targets ids 509 MNIC_TGTID , BDEV_TGTID, // 510 MEMC_WAYS , MEMC_SETS , // MC params 511 L1_IWAYS , L1_ISETS , L1_DWAYS , L1_DSETS, // L1 params 512 XRAM_LATENCY , // 513 is_io_cluster, // is IO cluster ? 514 FBUF_X_SIZE , FBUF_Y_SIZE , // FB params 515 disk_name , BDEV_SECTOR_SIZE, // IOC params 516 NB_NICS , nic_rx_name , nic_tx_name , NIC_TIMEOUT, // NIC params 517 loader , 560 518 frozen_cycles, 561 debug_from ,519 debug_from , 562 520 debug_ok and (cluster(x,y) == debug_memc_id), 563 521 debug_ok and (cluster(x,y) == debug_proc_id) … … 583 541 for (size_t x = 0; x < (CLUSTER_X); x++){ 584 542 for (size_t y = 0; y < CLUSTER_Y; y++){ 585 clusters[x][y]->p_clk (signal_clk);586 clusters[x][y]->p_resetn (signal_resetn);543 clusters[x][y]->p_clk (signal_clk); 544 clusters[x][y]->p_resetn (signal_resetn); 587 545 } 588 546 } … … 631 589 for (size_t k = 0; k < 2; k++) 632 590 { 633 clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]);634 clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]);635 clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]);636 clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]);637 638 clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] 639 clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] 640 clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] 641 clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] 591 clusters[0][y]->p_cmd_in[k][WEST] (signal_dspin_false_cmd_in[0][y][k][WEST]); 592 clusters[0][y]->p_cmd_out[k][WEST] (signal_dspin_false_cmd_out[0][y][k][WEST]); 593 clusters[0][y]->p_rsp_in[k][WEST] (signal_dspin_false_rsp_in[0][y][k][WEST]); 594 clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); 595 596 clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]); 597 clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]); 598 clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]); 599 clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]); 642 600 } 643 601 } … … 648 606 for (size_t k = 0; k < 2; k++) 649 607 { 650 clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]);651 clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]);652 clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]);653 clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]);654 655 clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH] 656 clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH] 657 clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH] 658 clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH] 608 clusters[x][0]->p_cmd_in[k][SOUTH] (signal_dspin_false_cmd_in[x][0][k][SOUTH]); 609 clusters[x][0]->p_cmd_out[k][SOUTH] (signal_dspin_false_cmd_out[x][0][k][SOUTH]); 610 clusters[x][0]->p_rsp_in[k][SOUTH] (signal_dspin_false_rsp_in[x][0][k][SOUTH]); 611 clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); 612 613 clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]); 614 clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]); 615 clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]); 616 clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]); 659 617 } 660 618 } … … 673 631 for (size_t k = 0; k < 2; k++){ 674 632 for (size_t a = 0; a < 4; a++){ 675 signal_dspin_false_cmd_in [x][y][k][a].write = false;676 signal_dspin_false_cmd_in [x][y][k][a].read= true;633 signal_dspin_false_cmd_in [x][y][k][a].write = false; 634 signal_dspin_false_cmd_in [x][y][k][a].read = true; 677 635 signal_dspin_false_cmd_out[x][y][k][a].write = false; 678 signal_dspin_false_cmd_out[x][y][k][a].read = true;679 680 signal_dspin_false_rsp_in [x][y][k][a].write = false;681 signal_dspin_false_rsp_in [x][y][k][a].read= true;636 signal_dspin_false_cmd_out[x][y][k][a].read = true; 637 638 signal_dspin_false_rsp_in [x][y][k][a].write = false; 639 signal_dspin_false_rsp_in [x][y][k][a].read = true; 682 640 signal_dspin_false_rsp_out[x][y][k][a].write = false; 683 signal_dspin_false_rsp_out[x][y][k][a].read = true;641 signal_dspin_false_rsp_out[x][y][k][a].read = true; 684 642 } 685 643 } … … 692 650 for (size_t n = 1; n < ncycles; n++) 693 651 { 694 695 652 if (debug_ok and (n > debug_from) and (n % debug_period == 0)) 696 653 { … … 828 785 829 786 // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 830 831 832 833 -
trunk/platforms/tsar_generic_xbar/top.desc
r378 r389 3 3 4 4 todo = Platform('caba', 'top.cpp', 5 5 uses = [ 6 6 Uses('caba:tsar_xbar_cluster', 7 iss_t = 'common:gdb_iss', 8 gdb_iss_t = 'common:mips32el', 9 cmd_width = 40, 10 rsp_width = 33), 11 Uses('common:elf_file_loader'), 7 iss_t = 'common:gdb_iss', 8 gdb_iss_t = 'common:mips32el', 9 cmd_width = 40, 10 rsp_width = 33 11 ), 12 Uses('common:elf_file_loader'), 12 13 Uses('common:plain_file_loader'), 13 ], 14 cell_size = 4, 15 plen_size = 8, 16 addr_size = 32, 17 rerror_size = 2, 18 clen_size = 1, 19 rflag_size = 1, 20 srcid_size = 14, 21 pktid_size = 4, 22 trdid_size = 4, 23 wrplen_size = 1, 14 ], 15 cell_size_bis = 8, 16 plen_size_bis = 8, 17 addr_size_bis = 32, 18 rerror_size_bis = 2, 19 clen_size_bis = 1, 20 rflag_size_bis = 1, 21 srcid_size_bis = 14, 22 pktid_size_bis = 4, 23 trdid_size_bis = 4, 24 wrplen_size_bis = 1, 25 26 cell_size = 4, 27 plen_size = 8, 28 addr_size = 32, 29 rerror_size = 2, 30 clen_size = 1, 31 rflag_size = 1, 32 srcid_size = 14, 33 pktid_size = 4, 34 trdid_size = 4, 35 wrplen_size = 1, 24 36 ) -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd
r378 r389 3 3 4 4 Module('caba:tsar_xbar_cluster', 5 classname = 'soclib::caba::TsarXbarCluster', 6 tmpl_parameters = [ 7 parameter.Module('vci_param', default = 'caba:vci_param'), 8 parameter.Module('iss_t'), 9 parameter.Int('cmd_width'), 10 parameter.Int('rsp_width'), 11 ], 12 header_files = [ '../source/include/tsar_xbar_cluster.h', ], 13 implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], 14 uses = [ 15 Uses('caba:base_module'), 16 Uses('common:mapping_table'), 17 Uses('common:iss2'), 18 Uses('caba:vci_cc_vcache_wrapper', 19 iss_t = 'common:gdb_iss', 20 gdb_iss_t = 'common:mips32el'), 21 Uses('caba:vci_mem_cache'), 22 Uses('caba:vci_simple_ram'), 5 classname = 'soclib::caba::TsarXbarCluster', 6 tmpl_parameters = [ 7 parameter.Module('iss_t'), 8 parameter.Int('cmd_width'), 9 parameter.Int('rsp_width'), 10 ], 11 header_files = [ '../source/include/tsar_xbar_cluster.h', ], 12 implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], 13 uses = [ 14 Uses('caba:base_module'), 15 Uses('common:mapping_table'), 16 Uses('common:iss2'), 17 Uses('caba:vci_cc_vcache_wrapper', 18 vci_param = 'caba:vci_param', 19 dspin_in_width = parameter.Reference('cmd_width'), 20 dspin_out_width = parameter.Reference('rsp_width'), 21 iss_t = 'common:gdb_iss', 22 gdb_iss_t = 'common:mips32el' 23 ), 24 Uses('caba:vci_mem_cache', 25 vci_param_int = 'caba:vci_param', 26 vci_param_ext = 'caba:vci_param_bis', 27 dspin_in_width = parameter.Reference('rsp_width'), 28 dspin_out_width = parameter.Reference('cmd_width') 29 ), 30 Uses('caba:vci_simple_ram', 31 vci_param = 'caba:vci_param_bis' 32 ), 33 Uses('caba:vci_simple_ram', 34 vci_param = 'caba:vci_param' 35 ), 23 36 Uses('caba:vci_xicu'), 24 37 Uses('caba:dspin_local_crossbar', 25 flit_width = parameter.Reference('cmd_width')), 38 flit_width = parameter.Reference('cmd_width') 39 ), 26 40 Uses('caba:dspin_local_crossbar', 27 flit_width = parameter.Reference('rsp_width')), 41 flit_width = parameter.Reference('rsp_width') 42 ), 28 43 Uses('caba:vci_dspin_initiator_wrapper', 29 44 dspin_cmd_width = parameter.Reference('cmd_width'), 30 dspin_rsp_width = parameter.Reference('rsp_width')), 45 dspin_rsp_width = parameter.Reference('rsp_width') 46 ), 31 47 Uses('caba:vci_dspin_target_wrapper', 32 48 dspin_cmd_width = parameter.Reference('cmd_width'), 33 dspin_rsp_width = parameter.Reference('rsp_width')), 49 dspin_rsp_width = parameter.Reference('rsp_width') 50 ), 34 51 Uses('caba:virtual_dspin_router', 35 flit_width = parameter.Reference('cmd_width')), 52 flit_width = parameter.Reference('cmd_width') 53 ), 36 54 Uses('caba:virtual_dspin_router', 37 flit_width = parameter.Reference('rsp_width')), 38 Uses('caba:vci_multi_tty'), 39 Uses('caba:vci_framebuffer'), 40 Uses('caba:vci_multi_nic'), 41 Uses('caba:vci_block_device_tsar'), 42 Uses('caba:vci_multi_dma'), 43 Uses('common:elf_file_loader'), 44 ], 45 ports = [ 46 Port('caba:bit_in', 'p_resetn', auto = 'resetn'), 47 Port('caba:clock_in', 'p_clk', auto = 'clock'), 48 Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), 49 Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), 50 Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 51 Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 52 ], 55 flit_width = parameter.Reference('rsp_width') 56 ), 57 Uses('caba:vci_multi_tty'), 58 Uses('caba:vci_framebuffer'), 59 Uses('caba:vci_multi_nic'), 60 Uses('caba:vci_block_device_tsar'), 61 Uses('caba:vci_multi_dma'), 62 Uses('common:elf_file_loader'), 63 ], 64 ports = [ 65 Port('caba:bit_in' , 'p_resetn' , auto = 'resetn'), 66 Port('caba:clock_in' , 'p_clk' , auto = 'clock'), 67 Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), 68 Port('caba:dspin_input' , 'p_cmd_in' , [2, 4], dspin_data_size = parameter.Reference('cmd_width')), 69 Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 70 Port('caba:dspin_input' , 'p_rsp_in' , [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 71 ], 53 72 ) 54 73 -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h
r378 r389 34 34 #include "vci_cc_vcache_wrapper.h" 35 35 36 namespace soclib { namespace caba { 36 /////////////////////////////////////////////////////////// 37 // VCI parameters for DIRECT network 38 /////////////////////////////////////////////////////////// 39 #define cell_width 4 40 #define address_width 32 41 #define plen_width 8 42 #define error_width 2 43 #define clen_width 1 44 #define rflag_width 1 45 #define srcid_width 14 46 #define pktid_width 4 47 #define trdid_width 4 48 #define wrplen_width 1 49 50 /////////////////////////////////////////////////////////// 51 // VCI parameters for EXTERNAL network 52 /////////////////////////////////////////////////////////// 53 #define cell_width_ext 8 54 #define address_width_ext address_width 55 #define plen_width_ext plen_width 56 #define error_width_ext error_width 57 #define clen_width_ext clen_width 58 #define rflag_width_ext rflag_width 59 #define srcid_width_ext srcid_width 60 #define pktid_width_ext pktid_width 61 #define trdid_width_ext trdid_width 62 #define wrplen_width_ext wrplen_width 63 64 namespace soclib { namespace caba { 37 65 38 66 /////////////////////////////////////////////////////////////////////////// 39 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> 67 template< 68 typename iss_t, int cmd_width, int rsp_width 69 > 40 70 class TsarXbarCluster 41 71 /////////////////////////////////////////////////////////////////////////// 42 72 : public soclib::caba::BaseModule 43 73 { 74 // Define VCI parameters 75 typedef soclib::caba::VciParams<cell_width, 76 plen_width, 77 address_width, 78 error_width, 79 clen_width, 80 rflag_width, 81 srcid_width, 82 pktid_width, 83 trdid_width, 84 wrplen_width> vci_param_d; 85 86 typedef soclib::caba::VciParamsBis<cell_width_ext, 87 plen_width_ext, 88 address_width_ext, 89 error_width_ext, 90 clen_width_ext, 91 rflag_width_ext, 92 srcid_width_ext, 93 pktid_width_ext, 94 trdid_width_ext, 95 wrplen_width_ext> vci_param_x; 44 96 45 97 public: 46 98 47 48 sc_in<bool> 49 sc_in<bool> 50 soclib::caba::DspinOutput<cmd_width>**p_cmd_out;51 soclib::caba::DspinInput<cmd_width>**p_cmd_in;52 soclib::caba::DspinOutput<rsp_width> 53 soclib::caba::DspinInput<rsp_width> 99 // Ports 100 sc_in<bool> p_clk; 101 sc_in<bool> p_resetn; 102 soclib::caba::DspinOutput<cmd_width> **p_cmd_out; 103 soclib::caba::DspinInput<cmd_width> **p_cmd_in; 104 soclib::caba::DspinOutput<rsp_width> **p_rsp_out; 105 soclib::caba::DspinInput<rsp_width> **p_rsp_in; 54 106 55 107 // interrupt signals 56 sc_signal<bool>signal_false;57 sc_signal<bool>signal_proc_it[8];58 sc_signal<bool>signal_irq_mdma[8];59 sc_signal<bool>signal_irq_mtty[23];60 sc_signal<bool> signal_irq_mnic_rx[8];// unused61 sc_signal<bool> signal_irq_mnic_tx[8];// unused62 sc_signal<bool>signal_irq_bdev;63 64 65 DspinSignals<cmd_width>signal_dspin_cmd_l2g_d;66 DspinSignals<cmd_width>signal_dspin_cmd_g2l_d;67 DspinSignals<cmd_width>signal_dspin_m2p_l2g_c;68 DspinSignals<cmd_width>signal_dspin_m2p_g2l_c;69 DspinSignals<rsp_width>signal_dspin_rsp_l2g_d;70 DspinSignals<rsp_width>signal_dspin_rsp_g2l_d;71 DspinSignals<rsp_width>signal_dspin_p2m_l2g_c;72 DspinSignals<rsp_width>signal_dspin_p2m_g2l_c;73 74 75 VciSignals<vci_param>signal_vci_ini_proc[8];76 VciSignals<vci_param>signal_vci_ini_mdma;77 VciSignals<vci_param>signal_vci_ini_bdev;78 79 VciSignals<vci_param>signal_vci_tgt_memc;80 VciSignals<vci_param>signal_vci_tgt_xicu;81 VciSignals<vci_param>signal_vci_tgt_mdma;82 VciSignals<vci_param>signal_vci_tgt_mtty;83 VciSignals<vci_param>signal_vci_tgt_bdev;84 VciSignals<vci_param>signal_vci_tgt_brom;85 VciSignals<vci_param>signal_vci_tgt_fbuf;86 VciSignals<vci_param>signal_vci_tgt_mnic;87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 VciSignals<vci_param>signal_vci_xram;121 108 sc_signal<bool> signal_false; 109 sc_signal<bool> signal_proc_it[8]; 110 sc_signal<bool> signal_irq_mdma[8]; 111 sc_signal<bool> signal_irq_mtty[23]; 112 sc_signal<bool> signal_irq_mnic_rx[8]; // unused 113 sc_signal<bool> signal_irq_mnic_tx[8]; // unused 114 sc_signal<bool> signal_irq_bdev; 115 116 // DSPIN signals between DSPIN routers and local_crossbars 117 DspinSignals<cmd_width> signal_dspin_cmd_l2g_d; 118 DspinSignals<cmd_width> signal_dspin_cmd_g2l_d; 119 DspinSignals<cmd_width> signal_dspin_m2p_l2g_c; 120 DspinSignals<cmd_width> signal_dspin_m2p_g2l_c; 121 DspinSignals<rsp_width> signal_dspin_rsp_l2g_d; 122 DspinSignals<rsp_width> signal_dspin_rsp_g2l_d; 123 DspinSignals<rsp_width> signal_dspin_p2m_l2g_c; 124 DspinSignals<rsp_width> signal_dspin_p2m_g2l_c; 125 126 // Direct VCI signals to VCI/DSPIN wrappers 127 VciSignals<vci_param_d> signal_vci_ini_proc[8]; 128 VciSignals<vci_param_d> signal_vci_ini_mdma; 129 VciSignals<vci_param_d> signal_vci_ini_bdev; 130 131 VciSignals<vci_param_d> signal_vci_tgt_memc; 132 VciSignals<vci_param_d> signal_vci_tgt_xicu; 133 VciSignals<vci_param_d> signal_vci_tgt_mdma; 134 VciSignals<vci_param_d> signal_vci_tgt_mtty; 135 VciSignals<vci_param_d> signal_vci_tgt_bdev; 136 VciSignals<vci_param_d> signal_vci_tgt_brom; 137 VciSignals<vci_param_d> signal_vci_tgt_fbuf; 138 VciSignals<vci_param_d> signal_vci_tgt_mnic; 139 140 // Direct DSPIN signals to local crossbars 141 DspinSignals<cmd_width> signal_dspin_cmd_proc_i[8]; 142 DspinSignals<rsp_width> signal_dspin_rsp_proc_i[8]; 143 DspinSignals<cmd_width> signal_dspin_cmd_mdma_i; 144 DspinSignals<rsp_width> signal_dspin_rsp_mdma_i; 145 DspinSignals<cmd_width> signal_dspin_cmd_bdev_i; 146 DspinSignals<rsp_width> signal_dspin_rsp_bdev_i; 147 148 DspinSignals<cmd_width> signal_dspin_cmd_memc_t; 149 DspinSignals<rsp_width> signal_dspin_rsp_memc_t; 150 DspinSignals<cmd_width> signal_dspin_cmd_xicu_t; 151 DspinSignals<rsp_width> signal_dspin_rsp_xicu_t; 152 DspinSignals<cmd_width> signal_dspin_cmd_mdma_t; 153 DspinSignals<rsp_width> signal_dspin_rsp_mdma_t; 154 DspinSignals<cmd_width> signal_dspin_cmd_mtty_t; 155 DspinSignals<rsp_width> signal_dspin_rsp_mtty_t; 156 DspinSignals<cmd_width> signal_dspin_cmd_bdev_t; 157 DspinSignals<rsp_width> signal_dspin_rsp_bdev_t; 158 DspinSignals<cmd_width> signal_dspin_cmd_brom_t; 159 DspinSignals<rsp_width> signal_dspin_rsp_brom_t; 160 DspinSignals<cmd_width> signal_dspin_cmd_fbuf_t; 161 DspinSignals<rsp_width> signal_dspin_rsp_fbuf_t; 162 DspinSignals<cmd_width> signal_dspin_cmd_mnic_t; 163 DspinSignals<rsp_width> signal_dspin_rsp_mnic_t; 164 165 // Coherence DSPIN signals to local crossbar 166 DspinSignals<cmd_width> signal_dspin_m2p_memc; 167 DspinSignals<rsp_width> signal_dspin_p2m_memc; 168 DspinSignals<cmd_width> signal_dspin_m2p_proc[8]; 169 DspinSignals<rsp_width> signal_dspin_p2m_proc[8]; 170 171 // external RAM VCI signal 172 VciSignals<vci_param_x> signal_vci_xram; 173 122 174 // Components 123 175 124 VciCcVCacheWrapper<vci_param, iss_t>* proc[8]; 125 VciDspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* wi_proc[4]; 126 127 VciMemCache<vci_param>* memc; 128 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_memc; 129 130 VciXicu<vci_param>* xicu; 131 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_xicu; 132 133 VciMultiDma<vci_param>* mdma; 134 VciDspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* wi_mdma; 135 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_mdma; 136 137 VciSimpleRam<vci_param>* xram; 138 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_xram; 139 140 VciSimpleRam<vci_param>* brom; 141 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_brom; 142 143 VciMultiTty<vci_param>* mtty; 144 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_mtty; 145 146 VciFrameBuffer<vci_param>* fbuf; 147 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_fbuf; 148 149 VciMultiNic<vci_param>* mnic; 150 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_mnic; 151 152 VciBlockDeviceTsar<vci_param>* bdev; 153 VciDspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* wi_bdev; 154 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_bdev; 155 156 DspinLocalCrossbar<cmd_width>* xbar_cmd_d; 157 DspinLocalCrossbar<rsp_width>* xbar_rsp_d; 158 DspinLocalCrossbar<cmd_width>* xbar_m2p_c; 159 DspinLocalCrossbar<rsp_width>* xbar_p2m_c; 160 161 VirtualDspinRouter<cmd_width>* router_cmd; 162 VirtualDspinRouter<rsp_width>* router_rsp; 163 164 TsarXbarCluster( sc_module_name insname, 176 VciCcVCacheWrapper<vci_param_d, cmd_width, rsp_width, iss_t>* proc[8]; 177 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_proc[4]; 178 179 VciMemCache<vci_param_d, vci_param_x, rsp_width, cmd_width> * memc; 180 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_memc; 181 182 VciXicu<vci_param_d>* xicu; 183 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_xicu; 184 185 VciMultiDma<vci_param_d>* mdma; 186 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_mdma; 187 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mdma; 188 189 VciSimpleRam<vci_param_x>* xram; 190 191 VciSimpleRam<vci_param_d>* brom; 192 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_brom; 193 194 VciMultiTty<vci_param_d>* mtty; 195 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mtty; 196 197 VciFrameBuffer<vci_param_d>* fbuf; 198 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_fbuf; 199 200 VciMultiNic<vci_param_d>* mnic; 201 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mnic; 202 203 VciBlockDeviceTsar<vci_param_d>* bdev; 204 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_bdev; 205 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_bdev; 206 207 DspinLocalCrossbar<cmd_width>* xbar_cmd_d; 208 DspinLocalCrossbar<rsp_width>* xbar_rsp_d; 209 DspinLocalCrossbar<cmd_width>* xbar_m2p_c; 210 DspinLocalCrossbar<rsp_width>* xbar_p2m_c; 211 212 VirtualDspinRouter<cmd_width>* router_cmd; 213 VirtualDspinRouter<rsp_width>* router_rsp; 214 215 TsarXbarCluster( sc_module_name insname, 165 216 size_t nb_procs, // number of processors 166 217 size_t nb_ttys, // number of TTY terminals … … 171 222 const soclib::common::MappingTable &mtd, // direct mapping table 172 223 const soclib::common::MappingTable &mtx, // xram mapping table 173 size_t 174 size_t 175 size_t 176 size_t 177 size_t 224 size_t x_width, // x field number of bits 225 size_t y_width, // y field number of bits 226 size_t l_width, // l field number of bits 227 size_t tgtid_memc, 228 size_t tgtid_xicu, 178 229 size_t tgtid_mdma, 179 size_t 230 size_t tgtid_fbuf, 180 231 size_t tgtid_mtty, 181 232 size_t tgtid_brom, … … 187 238 size_t l1_i_sets, 188 239 size_t l1_d_ways, 189 size_t l1_d_sets, 240 size_t l1_d_sets, 190 241 size_t xram_latency, // external ram latency 191 bool io, 242 bool io, // I/O cluster if true 192 243 size_t xfb, // frame buffer pixels 193 244 size_t yfb, // frame buffer lines … … 197 248 char* nic_rx_name, // file name rx packets 198 249 char* nic_tx_name, // file name tx packets 199 uint32_t 200 250 uint32_t nic_timeout, // number of cycles 251 const Loader &loader, // loader for BROM 201 252 uint32_t frozen_cycles, // max frozen cycles 202 253 uint32_t start_debug_cycle, … … 204 255 bool proc_debug_ok); 205 256 206 257 ~TsarXbarCluster(); 207 258 }; 208 259 }} -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp
r379 r389 26 26 #include "../include/tsar_xbar_cluster.h" 27 27 28 #define tmpl(x) template<\ 29 typename iss_t,int cmd_width, int rsp_width> \ 30 x TsarXbarCluster<\ 31 iss_t, cmd_width, rsp_width\ 32 > 33 28 34 namespace soclib { 29 35 namespace caba { … … 32 38 // Constructor 33 39 ////////////////////////////////////////////////////////////////////////// 34 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> 35 TsarXbarCluster<vci_param, iss_t, cmd_width, rsp_width>::TsarXbarCluster( 40 tmpl(/**/)::TsarXbarCluster( 36 41 sc_module_name insname, 37 42 size_t nb_procs, … … 103 108 std::ostringstream sproc; 104 109 sproc << "proc_" << p; 105 proc[p] = new VciCcVCacheWrapper<vci_param , iss_t>(110 proc[p] = new VciCcVCacheWrapper<vci_param_d, cmd_width, rsp_width, iss_t>( 106 111 sproc.str().c_str(), 107 112 cluster_id*nb_procs + p, // GLOBAL PROC_ID … … 125 130 std::ostringstream swip; 126 131 swip << "wi_proc_" << x_id << "_" << y_id << p; 127 wi_proc[p] = new VciDspinInitiatorWrapper<vci_param ,cmd_width,rsp_width>(132 wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>( 128 133 swip.str().c_str(), 129 134 x_width + y_width + l_width); … … 133 138 std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; 134 139 135 memc = new VciMemCache<vci_param >(140 memc = new VciMemCache<vci_param_d, vci_param_x, rsp_width, cmd_width>( 136 141 "memc", 137 142 mtd, // Mapping Table direct space … … 148 153 memc_debug_ok ); 149 154 150 wt_memc = new VciDspinTargetWrapper<vci_param ,cmd_width,rsp_width>(155 wt_memc = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>( 151 156 "wt_memc", 152 157 x_width + y_width + l_width); … … 155 160 std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; 156 161 157 xram = new VciSimpleRam<vci_param >(162 xram = new VciSimpleRam<vci_param_x>( 158 163 "xram", 159 164 IntTab(cluster_id), … … 165 170 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 166 171 167 xicu = new VciXicu<vci_param >(172 xicu = new VciXicu<vci_param_d>( 168 173 "xicu", 169 174 mtd, // mapping table … … 171 176 nb_procs, // number of timer IRQs 172 177 32, // number of hard IRQs 173 0,// number of soft IRQs178 32, // number of soft IRQs 174 179 nb_procs); // number of output IRQs 175 180 176 wt_xicu = new VciDspinTargetWrapper<vci_param ,cmd_width,rsp_width>(181 wt_xicu = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>( 177 182 "wt_xicu", 178 183 x_width + y_width + l_width); … … 181 186 std::cout << " - building mdma_" << x_id << "_" << y_id << std::endl; 182 187 183 mdma = new VciMultiDma<vci_param >(188 mdma = new VciMultiDma<vci_param_d>( 184 189 "mdma", 185 190 mtd, … … 189 194 nb_dmas); // number of IRQs 190 195 191 wt_mdma = new VciDspinTargetWrapper<vci_param ,cmd_width,rsp_width>(196 wt_mdma = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>( 192 197 "wt_mdma", 193 198 x_width + y_width + l_width); 194 199 195 wi_mdma = new VciDspinInitiatorWrapper<vci_param ,cmd_width,rsp_width>(200 wi_mdma = new VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>( 196 201 "wi_mdma", 197 202 x_width + y_width + l_width); … … 285 290 std::cout << " - building brom" << std::endl; 286 291 287 brom = new VciSimpleRam<vci_param >(292 brom = new VciSimpleRam<vci_param_d>( 288 293 "brom", 289 294 IntTab(cluster_id, tgtid_brom), … … 291 296 loader); 292 297 293 wt_brom = new VciDspinTargetWrapper<vci_param ,cmd_width,rsp_width>("wt_brom",298 wt_brom = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_brom", 294 299 x_width + y_width + l_width); 295 300 … … 297 302 std::cout << " - building fbuf" << std::endl; 298 303 299 fbuf = new VciFrameBuffer<vci_param >(304 fbuf = new VciFrameBuffer<vci_param_d>( 300 305 "fbuf", 301 306 IntTab(cluster_id, tgtid_fbuf), … … 303 308 xfb, yfb); 304 309 305 wt_fbuf = new VciDspinTargetWrapper<vci_param ,cmd_width,rsp_width>("wt_fbuf",310 wt_fbuf = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_fbuf", 306 311 x_width + y_width + l_width); 307 312 … … 309 314 std::cout << " - building bdev" << std::endl; 310 315 311 bdev = new VciBlockDeviceTsar<vci_param >(316 bdev = new VciBlockDeviceTsar<vci_param_d>( 312 317 "bdev", 313 318 mtd, … … 318 323 64); // burst size 319 324 320 wt_bdev = new VciDspinTargetWrapper<vci_param ,cmd_width,rsp_width>("wt_bdev",321 x_width + y_width + l_width); 322 wi_bdev = new VciDspinInitiatorWrapper<vci_param ,cmd_width,rsp_width>("wi_bdev",325 wt_bdev = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_bdev", 326 x_width + y_width + l_width); 327 wi_bdev = new VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>("wi_bdev", 323 328 x_width + y_width + l_width); 324 329 … … 326 331 std::cout << " - building mnic" << std::endl; 327 332 328 mnic = new VciMultiNic<vci_param >(333 mnic = new VciMultiNic<vci_param_d>( 329 334 "mnic", 330 335 IntTab(cluster_id, tgtid_mnic), … … 336 341 0 ); // mac_2 address 337 342 338 wt_mnic = new VciDspinTargetWrapper<vci_param ,cmd_width,rsp_width>("wt_mnic",343 wt_mnic = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_mnic", 339 344 x_width + y_width + l_width); 340 345 … … 349 354 vect_names.push_back(term_name.str().c_str()); 350 355 } 351 mtty = new VciMultiTty<vci_param >(356 mtty = new VciMultiTty<vci_param_d>( 352 357 "mtty", 353 358 IntTab(cluster_id, tgtid_mtty), … … 355 360 vect_names); 356 361 357 wt_mtty = new VciDspinTargetWrapper<vci_param ,cmd_width,rsp_width>("wt_mtty",362 wt_mtty = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_mtty", 358 363 x_width + y_width + l_width); 359 364 … … 677 682 // destructor 678 683 /////////////////////////////////////////////////////////////////////////// 679 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> 680 TsarXbarCluster<vci_param, iss_t, cmd_width, rsp_width>::~TsarXbarCluster() {} 681 684 tmpl(/**/)::~TsarXbarCluster() {} 682 685 } 683 686 }
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