- Timestamp:
- May 16, 2013, 3:32:38 PM (11 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h
r378 r389 34 34 #include "vci_cc_vcache_wrapper.h" 35 35 36 namespace soclib { namespace caba { 36 /////////////////////////////////////////////////////////// 37 // VCI parameters for DIRECT network 38 /////////////////////////////////////////////////////////// 39 #define cell_width 4 40 #define address_width 32 41 #define plen_width 8 42 #define error_width 2 43 #define clen_width 1 44 #define rflag_width 1 45 #define srcid_width 14 46 #define pktid_width 4 47 #define trdid_width 4 48 #define wrplen_width 1 49 50 /////////////////////////////////////////////////////////// 51 // VCI parameters for EXTERNAL network 52 /////////////////////////////////////////////////////////// 53 #define cell_width_ext 8 54 #define address_width_ext address_width 55 #define plen_width_ext plen_width 56 #define error_width_ext error_width 57 #define clen_width_ext clen_width 58 #define rflag_width_ext rflag_width 59 #define srcid_width_ext srcid_width 60 #define pktid_width_ext pktid_width 61 #define trdid_width_ext trdid_width 62 #define wrplen_width_ext wrplen_width 63 64 namespace soclib { namespace caba { 37 65 38 66 /////////////////////////////////////////////////////////////////////////// 39 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width> 67 template< 68 typename iss_t, int cmd_width, int rsp_width 69 > 40 70 class TsarXbarCluster 41 71 /////////////////////////////////////////////////////////////////////////// 42 72 : public soclib::caba::BaseModule 43 73 { 74 // Define VCI parameters 75 typedef soclib::caba::VciParams<cell_width, 76 plen_width, 77 address_width, 78 error_width, 79 clen_width, 80 rflag_width, 81 srcid_width, 82 pktid_width, 83 trdid_width, 84 wrplen_width> vci_param_d; 85 86 typedef soclib::caba::VciParamsBis<cell_width_ext, 87 plen_width_ext, 88 address_width_ext, 89 error_width_ext, 90 clen_width_ext, 91 rflag_width_ext, 92 srcid_width_ext, 93 pktid_width_ext, 94 trdid_width_ext, 95 wrplen_width_ext> vci_param_x; 44 96 45 97 public: 46 98 47 48 sc_in<bool> 49 sc_in<bool> 50 soclib::caba::DspinOutput<cmd_width>**p_cmd_out;51 soclib::caba::DspinInput<cmd_width>**p_cmd_in;52 soclib::caba::DspinOutput<rsp_width> 53 soclib::caba::DspinInput<rsp_width> 99 // Ports 100 sc_in<bool> p_clk; 101 sc_in<bool> p_resetn; 102 soclib::caba::DspinOutput<cmd_width> **p_cmd_out; 103 soclib::caba::DspinInput<cmd_width> **p_cmd_in; 104 soclib::caba::DspinOutput<rsp_width> **p_rsp_out; 105 soclib::caba::DspinInput<rsp_width> **p_rsp_in; 54 106 55 107 // interrupt signals 56 sc_signal<bool>signal_false;57 sc_signal<bool>signal_proc_it[8];58 sc_signal<bool>signal_irq_mdma[8];59 sc_signal<bool>signal_irq_mtty[23];60 sc_signal<bool> signal_irq_mnic_rx[8];// unused61 sc_signal<bool> signal_irq_mnic_tx[8];// unused62 sc_signal<bool>signal_irq_bdev;63 64 65 DspinSignals<cmd_width>signal_dspin_cmd_l2g_d;66 DspinSignals<cmd_width>signal_dspin_cmd_g2l_d;67 DspinSignals<cmd_width>signal_dspin_m2p_l2g_c;68 DspinSignals<cmd_width>signal_dspin_m2p_g2l_c;69 DspinSignals<rsp_width>signal_dspin_rsp_l2g_d;70 DspinSignals<rsp_width>signal_dspin_rsp_g2l_d;71 DspinSignals<rsp_width>signal_dspin_p2m_l2g_c;72 DspinSignals<rsp_width>signal_dspin_p2m_g2l_c;73 74 75 VciSignals<vci_param>signal_vci_ini_proc[8];76 VciSignals<vci_param>signal_vci_ini_mdma;77 VciSignals<vci_param>signal_vci_ini_bdev;78 79 VciSignals<vci_param>signal_vci_tgt_memc;80 VciSignals<vci_param>signal_vci_tgt_xicu;81 VciSignals<vci_param>signal_vci_tgt_mdma;82 VciSignals<vci_param>signal_vci_tgt_mtty;83 VciSignals<vci_param>signal_vci_tgt_bdev;84 VciSignals<vci_param>signal_vci_tgt_brom;85 VciSignals<vci_param>signal_vci_tgt_fbuf;86 VciSignals<vci_param>signal_vci_tgt_mnic;87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 VciSignals<vci_param>signal_vci_xram;121 108 sc_signal<bool> signal_false; 109 sc_signal<bool> signal_proc_it[8]; 110 sc_signal<bool> signal_irq_mdma[8]; 111 sc_signal<bool> signal_irq_mtty[23]; 112 sc_signal<bool> signal_irq_mnic_rx[8]; // unused 113 sc_signal<bool> signal_irq_mnic_tx[8]; // unused 114 sc_signal<bool> signal_irq_bdev; 115 116 // DSPIN signals between DSPIN routers and local_crossbars 117 DspinSignals<cmd_width> signal_dspin_cmd_l2g_d; 118 DspinSignals<cmd_width> signal_dspin_cmd_g2l_d; 119 DspinSignals<cmd_width> signal_dspin_m2p_l2g_c; 120 DspinSignals<cmd_width> signal_dspin_m2p_g2l_c; 121 DspinSignals<rsp_width> signal_dspin_rsp_l2g_d; 122 DspinSignals<rsp_width> signal_dspin_rsp_g2l_d; 123 DspinSignals<rsp_width> signal_dspin_p2m_l2g_c; 124 DspinSignals<rsp_width> signal_dspin_p2m_g2l_c; 125 126 // Direct VCI signals to VCI/DSPIN wrappers 127 VciSignals<vci_param_d> signal_vci_ini_proc[8]; 128 VciSignals<vci_param_d> signal_vci_ini_mdma; 129 VciSignals<vci_param_d> signal_vci_ini_bdev; 130 131 VciSignals<vci_param_d> signal_vci_tgt_memc; 132 VciSignals<vci_param_d> signal_vci_tgt_xicu; 133 VciSignals<vci_param_d> signal_vci_tgt_mdma; 134 VciSignals<vci_param_d> signal_vci_tgt_mtty; 135 VciSignals<vci_param_d> signal_vci_tgt_bdev; 136 VciSignals<vci_param_d> signal_vci_tgt_brom; 137 VciSignals<vci_param_d> signal_vci_tgt_fbuf; 138 VciSignals<vci_param_d> signal_vci_tgt_mnic; 139 140 // Direct DSPIN signals to local crossbars 141 DspinSignals<cmd_width> signal_dspin_cmd_proc_i[8]; 142 DspinSignals<rsp_width> signal_dspin_rsp_proc_i[8]; 143 DspinSignals<cmd_width> signal_dspin_cmd_mdma_i; 144 DspinSignals<rsp_width> signal_dspin_rsp_mdma_i; 145 DspinSignals<cmd_width> signal_dspin_cmd_bdev_i; 146 DspinSignals<rsp_width> signal_dspin_rsp_bdev_i; 147 148 DspinSignals<cmd_width> signal_dspin_cmd_memc_t; 149 DspinSignals<rsp_width> signal_dspin_rsp_memc_t; 150 DspinSignals<cmd_width> signal_dspin_cmd_xicu_t; 151 DspinSignals<rsp_width> signal_dspin_rsp_xicu_t; 152 DspinSignals<cmd_width> signal_dspin_cmd_mdma_t; 153 DspinSignals<rsp_width> signal_dspin_rsp_mdma_t; 154 DspinSignals<cmd_width> signal_dspin_cmd_mtty_t; 155 DspinSignals<rsp_width> signal_dspin_rsp_mtty_t; 156 DspinSignals<cmd_width> signal_dspin_cmd_bdev_t; 157 DspinSignals<rsp_width> signal_dspin_rsp_bdev_t; 158 DspinSignals<cmd_width> signal_dspin_cmd_brom_t; 159 DspinSignals<rsp_width> signal_dspin_rsp_brom_t; 160 DspinSignals<cmd_width> signal_dspin_cmd_fbuf_t; 161 DspinSignals<rsp_width> signal_dspin_rsp_fbuf_t; 162 DspinSignals<cmd_width> signal_dspin_cmd_mnic_t; 163 DspinSignals<rsp_width> signal_dspin_rsp_mnic_t; 164 165 // Coherence DSPIN signals to local crossbar 166 DspinSignals<cmd_width> signal_dspin_m2p_memc; 167 DspinSignals<rsp_width> signal_dspin_p2m_memc; 168 DspinSignals<cmd_width> signal_dspin_m2p_proc[8]; 169 DspinSignals<rsp_width> signal_dspin_p2m_proc[8]; 170 171 // external RAM VCI signal 172 VciSignals<vci_param_x> signal_vci_xram; 173 122 174 // Components 123 175 124 VciCcVCacheWrapper<vci_param, iss_t>* proc[8]; 125 VciDspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* wi_proc[4]; 126 127 VciMemCache<vci_param>* memc; 128 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_memc; 129 130 VciXicu<vci_param>* xicu; 131 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_xicu; 132 133 VciMultiDma<vci_param>* mdma; 134 VciDspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* wi_mdma; 135 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_mdma; 136 137 VciSimpleRam<vci_param>* xram; 138 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_xram; 139 140 VciSimpleRam<vci_param>* brom; 141 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_brom; 142 143 VciMultiTty<vci_param>* mtty; 144 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_mtty; 145 146 VciFrameBuffer<vci_param>* fbuf; 147 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_fbuf; 148 149 VciMultiNic<vci_param>* mnic; 150 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_mnic; 151 152 VciBlockDeviceTsar<vci_param>* bdev; 153 VciDspinInitiatorWrapper<vci_param,cmd_width,rsp_width>* wi_bdev; 154 VciDspinTargetWrapper<vci_param,cmd_width,rsp_width>* wt_bdev; 155 156 DspinLocalCrossbar<cmd_width>* xbar_cmd_d; 157 DspinLocalCrossbar<rsp_width>* xbar_rsp_d; 158 DspinLocalCrossbar<cmd_width>* xbar_m2p_c; 159 DspinLocalCrossbar<rsp_width>* xbar_p2m_c; 160 161 VirtualDspinRouter<cmd_width>* router_cmd; 162 VirtualDspinRouter<rsp_width>* router_rsp; 163 164 TsarXbarCluster( sc_module_name insname, 176 VciCcVCacheWrapper<vci_param_d, cmd_width, rsp_width, iss_t>* proc[8]; 177 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_proc[4]; 178 179 VciMemCache<vci_param_d, vci_param_x, rsp_width, cmd_width> * memc; 180 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_memc; 181 182 VciXicu<vci_param_d>* xicu; 183 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_xicu; 184 185 VciMultiDma<vci_param_d>* mdma; 186 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_mdma; 187 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mdma; 188 189 VciSimpleRam<vci_param_x>* xram; 190 191 VciSimpleRam<vci_param_d>* brom; 192 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_brom; 193 194 VciMultiTty<vci_param_d>* mtty; 195 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mtty; 196 197 VciFrameBuffer<vci_param_d>* fbuf; 198 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_fbuf; 199 200 VciMultiNic<vci_param_d>* mnic; 201 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mnic; 202 203 VciBlockDeviceTsar<vci_param_d>* bdev; 204 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_bdev; 205 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_bdev; 206 207 DspinLocalCrossbar<cmd_width>* xbar_cmd_d; 208 DspinLocalCrossbar<rsp_width>* xbar_rsp_d; 209 DspinLocalCrossbar<cmd_width>* xbar_m2p_c; 210 DspinLocalCrossbar<rsp_width>* xbar_p2m_c; 211 212 VirtualDspinRouter<cmd_width>* router_cmd; 213 VirtualDspinRouter<rsp_width>* router_rsp; 214 215 TsarXbarCluster( sc_module_name insname, 165 216 size_t nb_procs, // number of processors 166 217 size_t nb_ttys, // number of TTY terminals … … 171 222 const soclib::common::MappingTable &mtd, // direct mapping table 172 223 const soclib::common::MappingTable &mtx, // xram mapping table 173 size_t 174 size_t 175 size_t 176 size_t 177 size_t 224 size_t x_width, // x field number of bits 225 size_t y_width, // y field number of bits 226 size_t l_width, // l field number of bits 227 size_t tgtid_memc, 228 size_t tgtid_xicu, 178 229 size_t tgtid_mdma, 179 size_t 230 size_t tgtid_fbuf, 180 231 size_t tgtid_mtty, 181 232 size_t tgtid_brom, … … 187 238 size_t l1_i_sets, 188 239 size_t l1_d_ways, 189 size_t l1_d_sets, 240 size_t l1_d_sets, 190 241 size_t xram_latency, // external ram latency 191 bool io, 242 bool io, // I/O cluster if true 192 243 size_t xfb, // frame buffer pixels 193 244 size_t yfb, // frame buffer lines … … 197 248 char* nic_rx_name, // file name rx packets 198 249 char* nic_tx_name, // file name tx packets 199 uint32_t 200 250 uint32_t nic_timeout, // number of cycles 251 const Loader &loader, // loader for BROM 201 252 uint32_t frozen_cycles, // max frozen cycles 202 253 uint32_t start_debug_cycle, … … 204 255 bool proc_debug_ok); 205 256 206 257 ~TsarXbarCluster(); 207 258 }; 208 259 }}
Note: See TracChangeset
for help on using the changeset viewer.