Changeset 395 for trunk/modules/vci_mem_cache

Timestamp:

May 28, 2013, 9:56:06 AM (12 years ago)

Author:

alain

Message:

ntroducing support for 40 bits physical addresses.

Location:

trunk/modules/vci_mem_cache/caba

Files:

• metadata/vci_mem_cache.sd (modified) (1 diff)
• source/include/vci_mem_cache.h (modified) (18 diffs)
• source/src/vci_mem_cache.cpp (modified) (73 diffs)

trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd

@@ -55 +55 @@
             parameter.Int   ( 'heap_size' ),
         ],
-
-        extensions = [
-            'dsx:get_ident='
-            'vci_ini_index:p_vci_ini:mtc,'
-            'vci_tgt_index_cleanup:p_vci_tgt_cleanup:mtc,'
-            'vci_tgt_index:p_vci_tgt:mtp,'
-            'vci_ixr_index:p_vci_ixr:mtx',
-            'dsx:addressable=vci_tgt_index,vci_tgt_index_cleanup',
-        ],
 )

trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -52 +52 @@
 #include "dspin_dhccp_param.h"
 
-#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
-#define UPDATE_TAB_LINES      4 // Number of lines in the update tab
+#define TRT_ENTRIES      4      // Number of entries in TRT
+#define UPT_ENTRIES      4      // Number of entries in UPT
+#define HEAP_ENTRIES     1024   // Number of entries in HEAP
 
 namespace soclib {  namespace caba {
+
   using namespace sc_core;
 
@@ -83 +85 @@
 
       /* States of the TGT_RSP fsm */
-      enum tgt_rsp_fsm_state_e{
+      enum tgt_rsp_fsm_state_e
+      {
         TGT_RSP_READ_IDLE,
         TGT_RSP_WRITE_IDLE,
@@ -99 +102 @@
 
       /* States of the DSPIN_TGT fsm */
-      enum cc_receive_fsm_state_e{
+      enum cc_receive_fsm_state_e
+      {
         CC_RECEIVE_IDLE,
         CC_RECEIVE_CLEANUP,
@@ -106 +110 @@
 
       /* States of the CC_SEND fsm */
-      enum cc_send_fsm_state_e{
+      enum cc_send_fsm_state_e
+      {
         CC_SEND_XRAM_RSP_IDLE,
         CC_SEND_WRITE_IDLE,
@@ -130 +135 @@
 
       /* States of the MULTI_ACK fsm */
-      enum multi_ack_fsm_state_e{
+      enum multi_ack_fsm_state_e
+      {
         MULTI_ACK_IDLE,
         MULTI_ACK_UPT_LOCK,
@@ -138 +144 @@
 
       /* States of the READ fsm */
-      enum read_fsm_state_e{
+      enum read_fsm_state_e
+      {
         READ_IDLE,
         READ_DIR_REQ,
@@ -155 +162 @@
 
       /* States of the WRITE fsm */
-      enum write_fsm_state_e{
+      enum write_fsm_state_e
+      {
         WRITE_IDLE,
         WRITE_NEXT,
@@ -181 +189 @@
 
       /* States of the IXR_RSP fsm */
-      enum ixr_rsp_fsm_state_e{
+      enum ixr_rsp_fsm_state_e
+      {
         IXR_RSP_IDLE,
         IXR_RSP_ACK,
@@ -189 +198 @@
 
       /* States of the XRAM_RSP fsm */
-      enum xram_rsp_fsm_state_e{
+      enum xram_rsp_fsm_state_e
+      {
         XRAM_RSP_IDLE,
         XRAM_RSP_TRT_COPY,
@@ -208 +218 @@
 
       /* States of the IXR_CMD fsm */
-      enum ixr_cmd_fsm_state_e{
+      enum ixr_cmd_fsm_state_e
+      {
         IXR_CMD_READ_IDLE,
         IXR_CMD_WRITE_IDLE,
         IXR_CMD_CAS_IDLE,
         IXR_CMD_XRAM_IDLE,
-        IXR_CMD_READ_NLINE,
-        IXR_CMD_WRITE_NLINE,
-        IXR_CMD_CAS_NLINE,
-        IXR_CMD_XRAM_DATA
+        IXR_CMD_READ,
+        IXR_CMD_WRITE,
+        IXR_CMD_CAS,
+        IXR_CMD_XRAM
       };
 
       /* States of the CAS fsm */
-      enum cas_fsm_state_e{
+      enum cas_fsm_state_e
+      {
         CAS_IDLE,
         CAS_DIR_REQ,
@@ -245 +257 @@
 
       /* States of the CLEANUP fsm */
-      enum cleanup_fsm_state_e{
+      enum cleanup_fsm_state_e
+      {
         CLEANUP_IDLE,
         CLEANUP_GET_NLINE,
@@ -264 +277 @@
 
       /* States of the ALLOC_DIR fsm */
-      enum alloc_dir_fsm_state_e{
+      enum alloc_dir_fsm_state_e
+      {
         ALLOC_DIR_RESET,
         ALLOC_DIR_READ,
@@ -274 +288 @@
 
       /* States of the ALLOC_TRT fsm */
-      enum alloc_trt_fsm_state_e{
+      enum alloc_trt_fsm_state_e
+      {
         ALLOC_TRT_READ,
         ALLOC_TRT_WRITE,
@@ -283 +298 @@
 
       /* States of the ALLOC_UPT fsm */
-      enum alloc_upt_fsm_state_e{
+      enum alloc_upt_fsm_state_e
+      {
         ALLOC_UPT_WRITE,
         ALLOC_UPT_XRAM_RSP,
@@ -292 +308 @@
 
       /* States of the ALLOC_HEAP fsm */
-      enum alloc_heap_fsm_state_e{
+      enum alloc_heap_fsm_state_e
+      {
         ALLOC_HEAP_RESET,
         ALLOC_HEAP_READ,
@@ -386 +403 @@
       VciMemCache(
           sc_module_name name,                                // Instance Name
-          const soclib::common::MappingTable &mtp,            // Mapping table for direct network
-          const soclib::common::MappingTable &mtx,            // Mapping table for external network
+          const soclib::common::MappingTable &mtp,            // Mapping table direct network
+          const soclib::common::MappingTable &mtx,            // Mapping table external network
           const soclib::common::IntTab       &srcid_x,        // global index on external network
           const soclib::common::IntTab       &tgtid_d,        // global index on direct network
@@ -395 +412 @@
           const size_t                       nwords,          // Number of words per line
           const size_t                       max_copies,      // max number of copies in heap
-          const size_t                       heap_size=1024,  // number of heap entries
-          const size_t                       trt_lines=TRANSACTION_TAB_LINES, 
-          const size_t                       upt_lines=UPDATE_TAB_LINES,       
+          const size_t                       heap_size=HEAP_ENTRIES,
+          const size_t                       trt_lines=TRT_ENTRIES, 
+          const size_t                       upt_lines=UPT_ENTRIES,     
           const size_t                       debug_start_cycle=0,
           const bool                         debug_ok=false );
@@ -449 +466 @@
 
       // broadcast address
-      uint32_t                                                m_broadcast_address;
+      uint32_t                           m_broadcast_boundaries;
 
       //////////////////////////////////////////////////

trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

@@ -26 +26 @@
 * SOCLIB_LGPL_HEADER_END
 *
-* Maintainers: alain eric.guthmuller@polytechnique.edu
+* Maintainers: alain.greiner@lip6.fr
+*              eric.guthmuller@polytechnique.edu
 *              cesar.fuguet-tortolero@lip6.fr
 *              alexandre.joannou@lip6.fr
@@ -55 +56 @@
 #define RANDOMIZE_CAS        1
 
-namespace soclib
-{
-namespace caba
-{
+namespace soclib { namespace caba {
 
 const char *tgt_cmd_fsm_str[] =
@@ -190 +188 @@
   "IXR_CMD_CAS_IDLE",
   "IXR_CMD_XRAM_IDLE",
-  "IXR_CMD_READ_NLINE",
-  "IXR_CMD_WRITE_NLINE",
-  "IXR_CMD_CAS_NLINE",
-  "IXR_CMD_XRAM_DATA"
+  "IXR_CMD_READ",
+  "IXR_CMD_WRITE",
+  "IXR_CMD_CAS",
+  "IXR_CMD_XRAM"
 };
 const char *cas_fsm_str[] =
@@ -341 +339 @@
     // XMIN(5 bits) / XMAX(5 bits) / YMIN(5 bits) / YMAX(5 bits)
     //   0b00000    /   0b11111    /   0b00000    /   0b11111
-    m_broadcast_address(0x7C1F),
+    m_broadcast_boundaries(0x7C1F),
 
     //  FIFOs
@@ -514 +512 @@
       (addr < m_monitor_base + m_monitor_length))
   {
-    if ( read ) std::cout << " MEMC Read Monitor ";
-    else        std::cout << " MEMC Write Monitor "; 
+    if ( read ) std::cout << " Monitor MEMC Read  ";
+    else        std::cout << " Monitor MEMC Write "; 
     std::cout << buf 
-              << " Address = " << std::hex << addr
+              << " / Address = " << std::hex << addr
               << " / Data = " << data 
               << " at cycle " << std::dec << m_cpt_cycles << std::endl;
@@ -528 +526 @@
 {
   DirectoryEntry entry = m_cache_directory.read_neutral(addr);
+
   if((entry.count != m_debug_previous_count) or
       (entry.valid != m_debug_previous_hit))
   {
-    std::cout << " MEMC " << name()
-              << " cache change at cycle " << std::dec << m_cpt_cycles
+    std::cout << "Monitor MEMC " << name()
+              << " at cycle " << std::dec << m_cpt_cycles
               << " for address " << std::hex << addr
               << " / HIT = " << entry.valid
@@ -546 +545 @@
 {
   std::cout << "MEMC " << name() << std::endl;
-  std::cout << "  "  << tgt_cmd_fsm_str[r_tgt_cmd_fsm]
-            << " | " << tgt_rsp_fsm_str[r_tgt_rsp_fsm]
-            << " | " << read_fsm_str[r_read_fsm]
-            << " | " << write_fsm_str[r_write_fsm]
-            << " | " << cas_fsm_str[r_cas_fsm]
-            << " | " << cleanup_fsm_str[r_cleanup_fsm] << std::endl;
-  std::cout << "  "  << cc_send_fsm_str[r_cc_send_fsm]
-            << " | " << cc_receive_fsm_str[r_cc_receive_fsm]
-            << " | " << multi_ack_fsm_str[r_multi_ack_fsm]
-            << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm]
-            << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm]
+  std::cout << "  "  << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()]
+            << " | " << tgt_rsp_fsm_str[r_tgt_rsp_fsm.read()]
+            << " | " << read_fsm_str[r_read_fsm.read()]
+            << " | " << write_fsm_str[r_write_fsm.read()]
+            << " | " << cas_fsm_str[r_cas_fsm.read()]
+            << " | " << cleanup_fsm_str[r_cleanup_fsm.read()] << std::endl;
+  std::cout << "  "  << cc_send_fsm_str[r_cc_send_fsm.read()]
+            << " | " << cc_receive_fsm_str[r_cc_receive_fsm.read()]
+            << " | " << multi_ack_fsm_str[r_multi_ack_fsm.read()]
+            << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()]
+            << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()]
             << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl;
-
-  //m_llsc_table.print_trace();
-
+  std::cout << "  "  << alloc_dir_fsm_str[r_alloc_dir_fsm.read()]
+            << " | " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()]
+            << " | " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()]
+            << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl;
 }
 
@@ -1309 +1309 @@
   switch(r_read_fsm.read())
   {
-      ///////////////
+    ///////////////
     case READ_IDLE:
       // waiting a read request
@@ -1317 +1317 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " READ_IDLE> Read request:"
-                    << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
-                    << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
-                    << " / pktid = " << std::hex << m_cmd_read_pktid_fifo.read()
-                    << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
-        }
+if(m_debug_read_fsm)
+std::cout << "  <MEMC " << name() << " READ_IDLE> Read request:"
+          << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
+          << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / pktid = " << std::hex << m_cmd_read_pktid_fifo.read()
+          << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
 #endif
         r_read_fsm = READ_DIR_REQ;
@@ -1341 +1339 @@
 
 #if DEBUG_MEMC_READ
-      if(m_debug_read_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock "
-            << std::endl;
-      }
+if(m_debug_read_fsm)
+std::cout << "  <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl;
 #endif
       break;
@@ -1400 +1394 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: "
-              << " address = " << std::hex << m_cmd_read_addr_fifo.read()
-              << " / hit = " << std::dec << entry.valid
-              << " / count = " <<std::dec << entry.count
-              << " / is_cnt = " << entry.is_cnt << std::endl;
-          if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL)
-          {
-            std::cout
-                << "  <MEMC " << name() << " READ_DIR_LOCK> global_llsc_table LL access" << std::endl;
-          }
-        }
+if(m_debug_read_fsm)
+{
+std::cout << "  <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: "
+          << " address = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / hit = " << std::dec << entry.valid
+          << " / count = " <<std::dec << entry.count
+          << " / is_cnt = " << entry.is_cnt;
+if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl;
+else                                                std::cout << std::endl;
+}
 #endif
       }
       else
       {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " READ_DIR_LOCK state" << std::endl
-            << "Bad DIR allocation"   << std::endl;
-
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_DIR_LOCK state" 
+                  << "Bad DIR allocation"   << std::endl;
         exit(0);
       }
@@ -1439 +1426 @@
       if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ)
       {
-        // signals generation
         // check if this is an instruction read, this means pktid is either
         // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
@@ -1496 +1482 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
-              << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
-              << " / set = " << std::dec << set
-              << " / way = " << way
-              << " / owner_id = " << entry.owner.srcid
-              << " / owner_ins = " << entry.owner.inst
-              << " / count = " << entry.count
-              << " / is_cnt = " << entry.is_cnt << std::endl;
-        }
+if(m_debug_read_fsm)
+std::cout << "  <MEMC " << name() << " READ_DIR_HIT> Update directory entry:"
+          << " addr = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / set = " << std::dec << set
+          << " / way = " << way
+          << " / owner_id = " << entry.owner.srcid
+          << " / owner_ins = " << entry.owner.inst
+          << " / count = " << entry.count
+          << " / is_cnt = " << entry.is_cnt << std::endl;
 #endif
 
@@ -1526 +1509 @@
     }
 
+    ///////////////////
+    case READ_HEAP_REQ:    // Get the lock to the HEAP directory
+    {
+      if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
+      {
+        r_read_fsm = READ_HEAP_LOCK;
+      }
+
+#if DEBUG_MEMC_READ
+if(m_debug_read_fsm)
+std::cout << "  <MEMC " << name() << " READ_HEAP_REQ>" 
+          << " Requesting HEAP lock " << std::endl;
+#endif
+      break;
+    }
+
     ////////////////////
-    case READ_HEAP_REQ:
-      // Get the lock to the HEAP directory
-    {
-      if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
-      {
-        r_read_fsm = READ_HEAP_LOCK;
-      }
-
-#if DEBUG_MEMC_READ
-      if(m_debug_read_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name() << " READ_HEAP_REQ> Requesting HEAP lock "
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
-    ////////////////////
-    case READ_HEAP_LOCK:
-      // read data in cache, update the directory
-      // and prepare the HEAP update
+    case READ_HEAP_LOCK:   // read data in cache, update the directory
+                           // and prepare the HEAP update
     {
       if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
@@ -1627 +1605 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " READ_HEAP_LOCK> Update directory:"
-                    << " tag = " << std::hex << entry.tag
-                    << " set = " << std::dec << set
-                    << " way = " << way
-                    << " count = " << entry.count
-                    << " is_cnt = " << entry.is_cnt << std::endl;
-        }
+if(m_debug_read_fsm)
+std::cout << "  <MEMC " << name() << " READ_HEAP_LOCK> Update directory:"
+          << " tag = " << std::hex << entry.tag
+          << " set = " << std::dec << set
+          << " way = " << way
+          << " count = " << entry.count
+          << " is_cnt = " << entry.is_cnt << std::endl;
 #endif
       }
       else
       {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " READ_HEAP_LOCK state" << std::endl
-            << "Bad HEAP allocation"   << std::endl;
-
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK" 
+                  << "Bad HEAP allocation"   << std::endl;
         exit(0);
       }
-
-      break;
-    }
-
+      break;
+    }
     /////////////////////
-    case READ_HEAP_WRITE:       // add a entry in the heap
+    case READ_HEAP_WRITE:       // add an entry in the heap
     {
       if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)
@@ -1678 +1649 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:"
-              << " owner_id = " << heap_entry.owner.srcid
-              << " owner_ins = " << heap_entry.owner.inst << std::endl;
-        }
+if(m_debug_read_fsm)
+std::cout << "  <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:"
+          << " owner_id = " << heap_entry.owner.srcid
+          << " owner_ins = " << heap_entry.owner.inst << std::endl;
 #endif
       }
       else
       {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " READ_HEAP_WRITE state" << std::endl
-            << "Bad HEAP allocation" << std::endl;
-
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE" 
+                  << "Bad HEAP allocation" << std::endl;
         exit(0);
       }
       break;
     }
-
     /////////////////////
     case READ_HEAP_ERASE:
@@ -1717 +1681 @@
       else
       {
-        std::cout
-            << "VCI_MEM_CACHE ERROR " << name()
-            << " READ_HEAP_ERASE state" << std::endl
-            << "Bad HEAP allocation" << std::endl;
-
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE" 
+                  << "Bad HEAP allocation" << std::endl;
         exit(0);
       }
@@ -1753 +1714 @@
       else
       {
-        std::cout << "VCI_MEM_CACHE ERROR " << name()
-                  << " READ_HEAP_LAST state" << std::endl;
-        std::cout << "Bad HEAP allocation" << std::endl;
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST" 
+                  << "Bad HEAP allocation" << std::endl;
         exit(0);
       }
       break;
     }
-
     //////////////
     case READ_RSP:    //  request the TGT_RSP FSM to return data
@@ -1778 +1737 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " READ_RSP> Request the TGT_RSP FSM to return data:"
-                    << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read()
-                    << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
-                    << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
-        }
-#endif
-      }
-      break;
-    }
-
+if(m_debug_read_fsm)
+std::cout << "  <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:"
+          << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read()
+          << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
+#endif
+      }
+      break;
+    }
     ///////////////////
     case READ_TRT_LOCK: // read miss : check the Transaction Table
@@ -1815 +1771 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " READ_TRT_LOCK> Check TRT:"
-                    << " hit_read = " << hit_read
-                    << " / hit_write = " << hit_write
-                    << " / full = " << !wok << std::endl;
-        }
+if(m_debug_read_fsm)
+std::cout << "  <MEMC " << name() << " READ_TRT_LOCK> Check TRT:"
+          << " hit_read = " << hit_read
+          << " / hit_write = " << hit_write
+          << " / full = " << !wok << std::endl;
 #endif
       }
@@ -1845 +1799 @@
                               r_read_ll_key.read());
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " READ_TRT_SET> Write in Transaction Table: " << std::hex
-                    << " address = " << std::hex << m_cmd_read_addr_fifo.read()
-                    << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
-                    << std::endl;
-        }
+if(m_debug_read_fsm)
+std::cout << "  <MEMC " << name() << " READ_TRT_SET> Write in Transaction Table:"
+          << " address = " << std::hex << m_cmd_read_addr_fifo.read()
+          << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read() << std::endl;
 #endif
         r_read_fsm = READ_TRT_REQ;
@@ -1859 +1810 @@
 
     //////////////////
-    case READ_TRT_REQ:
-    {
-      // consume the read request in the FIFO,
-      // and send it to the ixr_cmd_fsm
-
+    case READ_TRT_REQ:   // consume the read request in FIFO and send it to IXR_CMD_FSM
+    {
       if(not r_read_to_ixr_cmd_req)
       {
@@ -1873 +1821 @@
 
 #if DEBUG_MEMC_READ
-        if(m_debug_read_fsm)
-        {
-          std::cout
-              << "  <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address "
-              << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
-        }
+if(m_debug_read_fsm)
+std::cout << "  <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address "
+          << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
 #endif
       }
@@ -2921 +2866 @@
   ///////////////////////////////////////////////////////////////////////
   // The IXR_CMD fsm controls the command packets to the XRAM :
-  // It handles requests from the READ, WRITE, CAS & XRAM_RSP FSMs
+  // It handles requests from the READ, WRITE, CAS, XRAM_RSP FSMs
   // with a round-robin priority.
   //
-  // - It sends a single cell VCI read request to the XRAM in case of MISS
+  // - It sends a single flit VCI read request to the XRAM in case of MISS
   // posted by the READ, WRITE or CAS FSMs : the TRDID field contains
   // the Transaction Tab index.
-  // The VCI response is a multi-cell packet : the N cells contain
+  // The VCI response is a multi-flit packet : the N cells contain
   // the N data words.
   //
-  // - It sends a multi-cell VCI write when the XRAM_RSP FSM, WRITE FSM
+  // - It sends a multi-flit VCI write when the XRAM_RSP FSM, WRITE FSM
   // or CAS FSM request to save a dirty line to the XRAM.
-  // The VCI response is a single cell packet.
+  // The VCI response is a single flit packet.
   ////////////////////////////////////////////////////////////////////////
 
   switch(r_ixr_cmd_fsm.read())
   {
-      ////////////////////////
+    ////////////////////////
     case IXR_CMD_READ_IDLE:
-      if     (r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
-      break;
-      ////////////////////////
+    {
+      if     (r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      break;
+    }
+    ////////////////////////
     case IXR_CMD_WRITE_IDLE:
-      if(r_cas_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
-      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
-      break;
-      ////////////////////////
+    {
+      if     (r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      break;
+    }
+    ////////////////////////
     case IXR_CMD_CAS_IDLE:
-      if(r_xram_rsp_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
-      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
-      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
-      break;
-      ////////////////////////
+    {
+      if     (r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      else if(r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      break;
+    }
+    ////////////////////////
     case IXR_CMD_XRAM_IDLE:
-      if(r_read_to_ixr_cmd_req)          r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
-      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
-      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
-      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
-      break;
-      /////////////////////////       // send a get request to XRAM
-    case IXR_CMD_READ_NLINE:
+    {
+      if     (r_read_to_ixr_cmd_req)     r_ixr_cmd_fsm = IXR_CMD_READ;
+      else if(r_write_to_ixr_cmd_req)    r_ixr_cmd_fsm = IXR_CMD_WRITE;
+      else if(r_cas_to_ixr_cmd_req)      r_ixr_cmd_fsm = IXR_CMD_CAS;
+      else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;
+      break;
+    }
+    //////////////////       // send a get from READ FSM
+    case IXR_CMD_READ:
+    {
       if(p_vci_ixr.cmdack)
       {
@@ -2974 +2928 @@
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug_ixr_cmd_fsm)
-{
-    std::cout << "  <MEMC " << name() 
-              << " IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;
-}
-#endif
-      }
-      break;
-      //////////////////////////
-    case IXR_CMD_WRITE_NLINE:     // send a put or get command to XRAM
+std::cout << "  <MEMC " << name() << " IXR_CMD_READ>"
+          << " Send a get request to xram / address = " << std::hex
+          << (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
+#endif
+      }
+      break;
+    }
+    ///////////////////
+    case IXR_CMD_WRITE:     // send a put or get from WRITE FSM
+    {
       if(p_vci_ixr.cmdack)
       {
@@ -3000 +2955 @@
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug_ixr_cmd_fsm)
-{
-    std::cout << "  <MEMC " << name() 
-              << " IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;
-}
+std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE>"
+          << " Send a put request to xram / address = " << std::hex
+          << (addr_t)((r_write_to_ixr_cmd_nline.read() * m_words +
+                      r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
 #endif
         }
@@ -3013 +2968 @@
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug_ixr_cmd_fsm)
-{
-    std::cout << "  <MEMC " << name() 
-              << " IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;
-}
-#endif
-        }
-      }
-      break;
-      //////////////////////
-    case IXR_CMD_CAS_NLINE:      // send a put or get command to XRAM
+std::cout << "  <MEMC " << name() << " IXR_CMD_WRITE>"
+          << " Send a get request to xram / address = " << std::hex
+          << (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
+#endif
+        }
+      }
+      break;
+    }
+    /////////////////
+    case IXR_CMD_CAS:      // send a put or get command from CAS FSM
+    {
       if(p_vci_ixr.cmdack)
       {
@@ -3040 +2996 @@
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug_ixr_cmd_fsm)
-{
-    std::cout << "  <MEMC " << name() 
-              << " IXR_CMD_CAS_NLINE> Send a put request to xram" << std::endl;
-}
+std::cout << "  <MEMC " << name() << " IXR_CMD_CAS>"
+          << " Send a put request to xram / address = " << std::hex
+          << (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words +
+                      r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
 #endif
         }
@@ -3053 +3009 @@
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug_ixr_cmd_fsm)
-{
-    std::cout << "  <MEMC " << name() 
-              << " IXR_CMD_CAS_NLINE> Send a get request to xram" << std::endl;
-}
-#endif
-        }
-      }
-      break;
-      ////////////////////////
-    case IXR_CMD_XRAM_DATA:     // send a put command to XRAM
+std::cout << "  <MEMC " << name() << " IXR_CMD_CAS>"
+          << " Send a get request to xram / address = " << std::hex
+          << (addr_t)(r_cas_to_ixr_cmd_nline.read()*m_words*4) << std::endl;
+#endif
+        }
+      }
+      break;
+    }
+    //////////////////
+    case IXR_CMD_XRAM:     // send a put from XRAM_RSP FSM
+    {
       if(p_vci_ixr.cmdack)
       {
@@ -3078 +3035 @@
 #if DEBUG_MEMC_IXR_CMD
 if(m_debug_ixr_cmd_fsm)
-{
-    std::cout << "  <MEMC " << name() 
-              << " IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;
-}
-#endif
-      }
-      break;
+std::cout << "  <MEMC " << name() << " IXR_CMD_XRAM>"
+          << " Send a put request to xram / address = " << std::hex
+          << (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words +
+                       r_ixr_cmd_cpt.read()) * 4 ) << std::endl;
+#endif
+      }
+      break;
+    }
 
   } // end switch r_ixr_cmd_fsm
@@ -3225 +3183 @@
   //
   // When a response is available, the corresponding TRT entry
-  // must be copied in a local buffer to be written in the cache.
+  // is copied in a local buffer to be written in the cache.
   // The FSM takes the lock protecting the TRT, and the lock protecting the DIR.
   // It selects a cache slot and writes the line in the cache.
@@ -3239 +3197 @@
   switch(r_xram_rsp_fsm.read())
   {
-      ///////////////////
-    case XRAM_RSP_IDLE: // scan the XRAM responses to get the TRT index (round robin)
+    ///////////////////
+    case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin)
     {
       size_t ptr   = r_xram_rsp_trt_index.read();
@@ -3246 +3204 @@
       for(size_t i=0 ; i<lines ; i++)
       {
-        size_t index= (i+ptr+1) %lines;
+        size_t index = (i+ptr+1) %lines;
         if(r_ixr_rsp_to_xram_rsp_rok[index])
         {
@@ -3254 +3212 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-          if(m_debug_xram_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << " XRAM_RSP_IDLE> Available cache line in TRT:"
-                      << " index = " << std::dec << index << std::endl;
-          }
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_IDLE>"
+          << " Available cache line in TRT:"
+          << " index = " << std::dec << index << std::endl;
 #endif
           break;
@@ -3266 +3223 @@
     }
     ///////////////////////
-    case XRAM_RSP_DIR_LOCK:
-      // Takes the lock on the directory
-      // Takes the lock on TRT
-      // Copy the TRT entry in a local buffer
+    case XRAM_RSP_DIR_LOCK: // Takes the DIR lock and the TRT lock
+                            // Copy the TRT entry in a local buffer
     {
       if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) &&
@@ -3276 +3231 @@
         // copy the TRT entry in the r_xram_rsp_trt_buf local buffer
         size_t  index = r_xram_rsp_trt_index.read();
-
-        TransactionTabEntry trt_entry(m_trt.read(index));
-        r_xram_rsp_trt_buf.copy(trt_entry);  // TRT entry local buffer
+        r_xram_rsp_trt_buf.copy( m_trt.read(index) );  
 
         r_xram_rsp_fsm = XRAM_RSP_TRT_COPY;
+
+//        TransactionTabEntry trt_entry(m_trt.read(index));
+//        r_xram_rsp_trt_buf.copy(trt_entry);           // TRT entry local buffer
 
 #if DEBUG_MEMC_XRAM_RSP
 if(m_debug_xram_rsp_fsm)
-{
-    std::cout << "  <MEMC " << name() 
-              << " XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl;
-}
+std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_LOCK>"
+          << " Get access to DIR and TRT" << std::endl;
 #endif
       }
@@ -3293 +3247 @@
     }
     ///////////////////////
-    case XRAM_RSP_TRT_COPY:
-      // Select a victim cache line
-    {
-      if((r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP))
+    case XRAM_RSP_TRT_COPY: // Select a victim cache line
+                            // and copy it in a local buffer
+    {
+      if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and
+           (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) )
       {
         // selects & extracts a victim line from cache
@@ -3310 +3265 @@
 
         r_xram_rsp_victim_copy      = victim.owner.srcid;
+
 #if L1_MULTI_CACHE
         r_xram_rsp_victim_copy_cache= victim.owner.cache_id;
@@ -3333 +3289 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY> Select a slot: "
-                    << " way = " << std::dec << way
-                    << " / set = " << set
-                    << " / inval_required = " << inval << std::endl;
-        }
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY>"
+          << " Select a slot: "
+          << " way = " << std::dec << way
+          << " / set = " << set
+          << " / inval_required = " << inval << std::endl;
 #endif
       }
       else
       {
-        std::cout << "VCI_MEM_CACHE ERROR "     << name()
-                  << " XRAM_RSP_TRT_COPY state" << std::endl
-                  << "bad TRT allocation"       << std::endl;
-
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_TRT_COPY" 
+                  << " bad TRT or DIR allocation" << std::endl;
         exit(0);
       }
@@ -3353 +3306 @@
     }
     /////////////////////////
-    case XRAM_RSP_INVAL_LOCK: // check a possible pending inval
+    case XRAM_RSP_INVAL_LOCK: // Take the UPT lock to check a possible pending inval
     {
       if(r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP)
       {
-        size_t index;
-        if(m_upt.search_inval(r_xram_rsp_trt_buf.nline, index))
+        size_t index = 0;
+        if(m_upt.search_inval(r_xram_rsp_trt_buf.nline, index))  // pending inval
         {
           r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 
 #if DEBUG_MEMC_XRAM_RSP
-          if(m_debug_xram_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
-                      << " but an invalidation is already registered at this address" << std::endl;
-            m_upt.print();
-          }
-#endif
-
-        }
-        else if(m_upt.is_full() && r_xram_rsp_victim_inval.read())
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
+          << " Get acces to UPT, but line invalidation registered" 
+          << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline 
+          << " / index = " << std::dec << index << std::endl;
+#endif
+
+        }
+        else if(m_upt.is_full() && r_xram_rsp_victim_inval.read()) // UPT full
         {
           r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 
 #if DEBUG_MEMC_XRAM_RSP
-          if(m_debug_xram_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
-                      << " but the table is full" << std::endl;
-            m_upt.print();
-          }
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
+          << " Get acces to UPT, but inval required and UPT full" << std::endl;
 #endif
         }
@@ -3390 +3339 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-          if(m_debug_xram_rsp_fsm)
-          {
-            std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl;
-          }
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>"
+          << " Get acces to UPT" << std::endl;
 #endif
         }
@@ -3400 +3348 @@
     }
     /////////////////////////
-    case XRAM_RSP_INVAL_WAIT: // returns to DIR_LOCK to retry
-    {
+    case XRAM_RSP_INVAL_WAIT: // release all locks and returns to DIR_LOCK to retry
+    {
+
+#if DEBUG_MEMC_XRAM_RSP
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL_WAIT>"
+          << " Release all locks and retry" << std::endl;
+#endif
       r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
       break;
@@ -3407 +3361 @@
     ///////////////////////
     case XRAM_RSP_DIR_UPDT:   // updates the cache (both data & directory)
-      // and possibly set an inval request in UPT
-    {
-      // signals generation
+                              // and possibly set an inval request in UPT
+    {
       // check if this is an instruction read, this means pktid is either
       // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
       // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
       bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) && r_xram_rsp_trt_buf.proc_read;
+
       // check if this is a cached read, this means pktid is either
       // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
@@ -3419 +3373 @@
       bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) && r_xram_rsp_trt_buf.proc_read;
 
-      // update data
+      bool dirty = false;
+
+      // update cache data
       size_t set   = r_xram_rsp_victim_set.read();
       size_t way   = r_xram_rsp_victim_way.read();
@@ -3426 +3382 @@
         m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]);
 
+        dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[word] != 0);
+
         if(m_monitor_ok)
         {
@@ -3432 +3390 @@
         }
       }
-      // compute dirty
-      bool dirty = false;
-      for(size_t i=0; i<m_words; i++) dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[i] != 0);
-      // update directory
+
+      // update cache directory
       DirectoryEntry entry;
       entry.valid   = true;
@@ -3463 +3419 @@
       m_cache_directory.write(set, way, entry);
 
+      // request an invalidattion request in UPT for victim line
       if(r_xram_rsp_victim_inval.read())
       {
-        bool   brdcast    = r_xram_rsp_victim_is_cnt.read();
-        size_t index    = 0;
-        size_t count_copies   = r_xram_rsp_victim_count.read();
+        bool   broadcast    = r_xram_rsp_victim_is_cnt.read();
+        size_t index        = 0;
+        size_t count_copies = r_xram_rsp_victim_count.read();
 
         bool   wok = m_upt.set(false,      // it's an inval transaction
-                                      brdcast,  // set brdcast bit
-                                      false,    // it does not need a response
-                                      0,    // srcid
-                                      0,    // trdid
-                                      0,    // pktid
-                                      r_xram_rsp_victim_nline.read(),
-                                      count_copies,
-                                      index);
+                               broadcast,  // set broadcast bit
+                               false,      // it does not need a response
+                               0,          // srcid
+                               0,          // trdid
+                               0,          // pktid
+                               r_xram_rsp_victim_nline.read(),
+                               count_copies,
+                               index);
+
         r_xram_rsp_upt_index = index;
 
         if(!wok)
         {
-          std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST state" << std::endl;
-          std::cout << "an update_tab entry was free but write is unsuccessful" << std::endl;
+          std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_DIR_UPDT"
+                    << " update_tab entry free but write unsuccessful" << std::endl;
           exit(0);
         }
@@ -3489 +3447 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-      if(m_debug_xram_rsp_fsm)
-      {
-        std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_UPDT> Directory update: "
-                  << " way = " << std::dec << way
-                  << " / set = " << set
-                  << " / owner_id = " << entry.owner.srcid
-                  << " / owner_ins = " << entry.owner.inst
-                  << " / count = " << entry.count
-                  << " / is_cnt = " << entry.is_cnt << std::endl;
-        if(r_xram_rsp_victim_inval.read())
-          std::cout << "                           Invalidation request for victim line "
-                    << std::hex << r_xram_rsp_victim_nline.read()
-                    << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl;
-      }
-#endif
-
-      // If the victim is not dirty, we don't need another XRAM  put transaction,
-      // and we canwe erase the TRT entry
+if(m_debug_xram_rsp_fsm)
+{
+std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_UPDT>" 
+          << " Cache update: "
+          << " way = " << std::dec << way
+          << " / set = " << set
+          << " / owner_id = " << entry.owner.srcid
+          << " / owner_ins = " << entry.owner.inst
+          << " / count = " << entry.count
+          << " / is_cnt = " << entry.is_cnt << std::endl;
+if(r_xram_rsp_victim_inval.read())
+std::cout << "                           Invalidation request for victim line "
+          << std::hex << r_xram_rsp_victim_nline.read()
+          << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl;
+}
+#endif
+
+      // If the victim is not dirty, we don't need another XRAM put transaction,
+      // and we can erase the TRT entry
       if(!r_xram_rsp_victim_dirty.read())  m_trt.erase(r_xram_rsp_trt_index.read());
 
       // Next state
       if(r_xram_rsp_victim_dirty.read())       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
-      else if(r_xram_rsp_trt_buf.proc_read)       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
-      else if(r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
-      else                                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+      else if(r_xram_rsp_trt_buf.proc_read)    r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+      else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
+      else                                     r_xram_rsp_fsm = XRAM_RSP_IDLE;
       break;
     }
     ////////////////////////
-    case XRAM_RSP_TRT_DIRTY:  // set the TRT entry (write to XRAM) if the victim is dirty
+    case XRAM_RSP_TRT_DIRTY:  // set the TRT entry (PUT to XRAM) if the victim is dirty
     {
       if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)
@@ -3534 +3493 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:"
-                    << " dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
-        }
-#endif
-        if(r_xram_rsp_trt_buf.proc_read)       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
-        else if(r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
-        else                                            r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>"
+          << " Set TRT entry for the put transaction"
+          << " / dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
+#endif
+        if(r_xram_rsp_trt_buf.proc_read)         r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+        else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
+        else                                     r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
       }
       break;
@@ -3554 +3512 @@
         r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
         r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
-        for(size_t i=0; i < m_words; i++) r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+        for(size_t i=0; i < m_words; i++) 
+        {
+            r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+        }
         r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
         r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
@@ -3561 +3522 @@
         r_xram_rsp_to_tgt_rsp_req    = true;
 
-        if(r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL;
+        if(r_xram_rsp_victim_inval)      r_xram_rsp_fsm = XRAM_RSP_INVAL;
         else if(r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
-        else                                r_xram_rsp_fsm = XRAM_RSP_IDLE;
-
+        else                             r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:"
-                    << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid
-                    << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
-                    << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl;
-        }
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_DIR_RSP>"
+          << " Request the TGT_RSP FSM to return data:"
+          << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid
+          << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
+          << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl;
 #endif
       }
@@ -3601 +3560 @@
 
         if(r_xram_rsp_victim_dirty)  r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
-        else if(not_last_multi_req)    r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
-        else                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+        else if(not_last_multi_req)  r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
+        else                         r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL> Send an inval request to CC_SEND FSM:"
-                    << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
-        }
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_INVAL>"
+          << " Send an inval request to CC_SEND FSM"
+          << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
 #endif
       }
@@ -3622 +3580 @@
         r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read();
         r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read();
-        for(size_t i=0; i<m_words ; i++) r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+        for(size_t i=0; i<m_words ; i++) 
+        {
+            r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+        }
         m_cpt_write_dirty++;
 
         bool multi_req = !r_xram_rsp_victim_is_cnt.read() && r_xram_rsp_victim_inval.read();
         bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1);
+
         if(not_last_multi_req)   r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
-        else                        r_xram_rsp_fsm = XRAM_RSP_IDLE;
+        else                     r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:"
-                    << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
-        }
-#endif
-      }
-      break;
-    }
-
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY>"
+          << " Send the put request to IXR_CMD FSM"
+          << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
+#endif
+      }
+      break;
+    }
     /////////////////////////
-    case XRAM_RSP_HEAP_REQ:
-      // Get the lock to the HEAP directory
+    case XRAM_RSP_HEAP_REQ:    // Get the lock to the HEAP 
     {
       if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)
@@ -3651 +3610 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-      if(m_debug_xram_rsp_fsm)
-      {
-        std::cout
-            << "  <MEMC " << name() << " XRAM_RSP_HEAP_REQ> Requesting HEAP lock "
-            << std::endl;
-      }
-#endif
-      break;
-    }
-
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_REQ>"
+          << " Requesting HEAP lock" << std::endl;
+#endif
+      break;
+    }
     /////////////////////////
-    case XRAM_RSP_HEAP_ERASE: // erase the list of copies and sent invalidations
+    case XRAM_RSP_HEAP_ERASE: // erase the copies and send invalidations
     {
       if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)
@@ -3693 +3648 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_ERASE> Erase the list of copies:"
-                    << " srcid = " << std::dec << entry.owner.srcid
-                    << " / inst = " << std::dec << entry.owner.inst << std::endl;
-        }
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_ERASE>"
+          << " Erase copy:"
+          << " srcid = " << std::dec << entry.owner.srcid
+          << " / inst = " << std::dec << entry.owner.inst << std::endl;
 #endif
       }
@@ -3704 +3658 @@
     }
     /////////////////////////
-    case XRAM_RSP_HEAP_LAST:  // last member of the list
+    case XRAM_RSP_HEAP_LAST:  // last copy
     {
       if(r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP)
       {
-        std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST state" << std::endl;
-        std::cout << "bad HEAP allocation" << std::endl;
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST"
+                   << " bad HEAP allocation" << std::endl;
         exit(0);
       }
@@ -3736 +3690 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-      if(m_debug_xram_rsp_fsm)
-      {
-        std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl;
-      }
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_HEAP_LAST>"
+          << " Heap housekeeping" << std::endl;
 #endif
       break;
@@ -3750 +3703 @@
       // Next state
       if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP;
-      else                                 r_xram_rsp_fsm = XRAM_RSP_IDLE;
+      else                             r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
 #if DEBUG_MEMC_XRAM_RSP
-      if(m_debug_xram_rsp_fsm)
-      {
-        std::cout << "  <MEMC " << name() << " XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl;
-      }
+if(m_debug_xram_rsp_fsm)
+std::cout << "  <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>"
+          << " Error reported by XRAM / erase the TRT entry" << std::endl;
 #endif
       break;
@@ -3763 +3715 @@
     case XRAM_RSP_ERROR_RSP:     // Request an error response to TGT_RSP FSM
     {
-      if(!r_xram_rsp_to_tgt_rsp_req.read())
+      if(!r_xram_rsp_to_tgt_rsp_req.read()) 
       {
         r_xram_rsp_to_tgt_rsp_srcid  = r_xram_rsp_trt_buf.srcid;
         r_xram_rsp_to_tgt_rsp_trdid  = r_xram_rsp_trt_buf.trdid;
         r_xram_rsp_to_tgt_rsp_pktid  = r_xram_rsp_trt_buf.pktid;
-        for(size_t i=0; i < m_words; i++) r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+        for(size_t i=0; i < m_words; i++) 
+        {
+            r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+        }
         r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
         r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
@@ -3777 +3732 @@
 
 #if DEBUG_MEMC_XRAM_RSP
-        if(m_debug_xram_rsp_fsm)
-        {
-          std::cout << "  <MEMC " << name() << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
-                    << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
-        }
+if(m_debug_xram_rsp_fsm)
+    std::cout << "  <MEMC " << name() 
+              << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
+              << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
 #endif
       }
@@ -5151 +5105 @@
       break;
     }
-    ///////////////////
+    /////////////////////
     case CAS_BC_UPT_LOCK:  // register a broadcast inval transaction in UPT
-      // write data in cache in case of successful registration
+                           // write data in cache in case of successful registration
     {
       if(r_alloc_upt_fsm.read() == ALLOC_UPT_CAS)
@@ -6525 +6479 @@
   switch(r_alloc_dir_fsm.read())
   {
-    case ALLOC_DIR_RESET:
-      // Initializes the directory one SET each cycle. All the WAYS of a SET are
-      // initialize in parallel
+    case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle. 
+                          // All the WAYS of a SET initialized in parallel
 
       r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1);
@@ -6534 +6487 @@
       {
         m_cache_directory.init();
-
         r_alloc_dir_fsm = ALLOC_DIR_READ;
       }
       break;
 
-      ////////////////////
+    ////////////////////
     case ALLOC_DIR_READ:
       if(((r_read_fsm.read()        != READ_DIR_REQ)   &&
@@ -6682 +6634 @@
   switch(r_alloc_trt_fsm.read())
   {
-      ////////////////////
+    ////////////////////
     case ALLOC_TRT_READ:
       if(r_read_fsm.read() != READ_TRT_LOCK)
@@ -6704 +6656 @@
       break;
 
-      /////////////////////
+    /////////////////////
     case ALLOC_TRT_WRITE:
       if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) &&
@@ -6727 +6679 @@
       break;
 
-      ////////////////////
+    ////////////////////
     case ALLOC_TRT_CAS:
       if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) &&
@@ -6750 +6702 @@
       break;
 
-      ////////////////////////
+    ////////////////////////
     case ALLOC_TRT_XRAM_RSP:
       if(((r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_LOCK)  ||
@@ -6775 +6727 @@
       break;
 
-      ////////////////////////
+    ////////////////////////
     case ALLOC_TRT_IXR_RSP:
       if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) &&
@@ -7210 +7162 @@
   p_vci_ixr.plen    = 64;
 
-  if(r_ixr_cmd_fsm.read() == IXR_CMD_READ_NLINE)
+  if(r_ixr_cmd_fsm.read() == IXR_CMD_READ)
   {
     p_vci_ixr.cmd       = vci_param_ext::CMD_READ;
@@ -7219 +7171 @@
     p_vci_ixr.eop       = true;
   }
-  else if(r_ixr_cmd_fsm.read() == IXR_CMD_CAS_NLINE)
+  else if(r_ixr_cmd_fsm.read() == IXR_CMD_CAS)
   {
     if(r_cas_to_ixr_cmd_write.read())
@@ -7242 +7194 @@
     }
   }
-  else if(r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_NLINE)
+  else if(r_ixr_cmd_fsm.read() == IXR_CMD_WRITE)
   {
     if(r_write_to_ixr_cmd_write.read())
@@ -7265 +7217 @@
     }
   }
-  else if(r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_DATA)
+  else if(r_ixr_cmd_fsm.read() == IXR_CMD_XRAM)
   {
     p_vci_ixr.cmd       = vci_param_ext::CMD_WRITE;
@@ -7583 +7535 @@
         DspinDhccpParam::dspin_set(
             flit,
-            m_broadcast_address,
+            m_broadcast_boundaries,
             DspinDhccpParam::BROADCAST_BOX);