- Timestamp:
- May 28, 2013, 9:56:06 AM (12 years ago)
- File:
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trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r391 r395 26 26 * SOCLIB_LGPL_HEADER_END 27 27 * 28 * Maintainers: alain eric.guthmuller@polytechnique.edu 28 * Maintainers: alain.greiner@lip6.fr 29 * eric.guthmuller@polytechnique.edu 29 30 * cesar.fuguet-tortolero@lip6.fr 30 31 * alexandre.joannou@lip6.fr … … 55 56 #define RANDOMIZE_CAS 1 56 57 57 namespace soclib 58 { 59 namespace caba 60 { 58 namespace soclib { namespace caba { 61 59 62 60 const char *tgt_cmd_fsm_str[] = … … 190 188 "IXR_CMD_CAS_IDLE", 191 189 "IXR_CMD_XRAM_IDLE", 192 "IXR_CMD_READ _NLINE",193 "IXR_CMD_WRITE _NLINE",194 "IXR_CMD_CAS _NLINE",195 "IXR_CMD_XRAM _DATA"190 "IXR_CMD_READ", 191 "IXR_CMD_WRITE", 192 "IXR_CMD_CAS", 193 "IXR_CMD_XRAM" 196 194 }; 197 195 const char *cas_fsm_str[] = … … 341 339 // XMIN(5 bits) / XMAX(5 bits) / YMIN(5 bits) / YMAX(5 bits) 342 340 // 0b00000 / 0b11111 / 0b00000 / 0b11111 343 m_broadcast_ address(0x7C1F),341 m_broadcast_boundaries(0x7C1F), 344 342 345 343 // FIFOs … … 514 512 (addr < m_monitor_base + m_monitor_length)) 515 513 { 516 if ( read ) std::cout << " M EMC Read Monitor";517 else std::cout << " M EMC Write Monitor";514 if ( read ) std::cout << " Monitor MEMC Read "; 515 else std::cout << " Monitor MEMC Write "; 518 516 std::cout << buf 519 << " Address = " << std::hex << addr517 << " / Address = " << std::hex << addr 520 518 << " / Data = " << data 521 519 << " at cycle " << std::dec << m_cpt_cycles << std::endl; … … 528 526 { 529 527 DirectoryEntry entry = m_cache_directory.read_neutral(addr); 528 530 529 if((entry.count != m_debug_previous_count) or 531 530 (entry.valid != m_debug_previous_hit)) 532 531 { 533 std::cout << " MEMC " << name()534 << " cache changeat cycle " << std::dec << m_cpt_cycles532 std::cout << "Monitor MEMC " << name() 533 << " at cycle " << std::dec << m_cpt_cycles 535 534 << " for address " << std::hex << addr 536 535 << " / HIT = " << entry.valid … … 546 545 { 547 546 std::cout << "MEMC " << name() << std::endl; 548 std::cout << " " << tgt_cmd_fsm_str[r_tgt_cmd_fsm ]549 << " | " << tgt_rsp_fsm_str[r_tgt_rsp_fsm ]550 << " | " << read_fsm_str[r_read_fsm ]551 << " | " << write_fsm_str[r_write_fsm ]552 << " | " << cas_fsm_str[r_cas_fsm ]553 << " | " << cleanup_fsm_str[r_cleanup_fsm ] << std::endl;554 std::cout << " " << cc_send_fsm_str[r_cc_send_fsm ]555 << " | " << cc_receive_fsm_str[r_cc_receive_fsm ]556 << " | " << multi_ack_fsm_str[r_multi_ack_fsm ]557 << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm ]558 << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm ]547 std::cout << " " << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()] 548 << " | " << tgt_rsp_fsm_str[r_tgt_rsp_fsm.read()] 549 << " | " << read_fsm_str[r_read_fsm.read()] 550 << " | " << write_fsm_str[r_write_fsm.read()] 551 << " | " << cas_fsm_str[r_cas_fsm.read()] 552 << " | " << cleanup_fsm_str[r_cleanup_fsm.read()] << std::endl; 553 std::cout << " " << cc_send_fsm_str[r_cc_send_fsm.read()] 554 << " | " << cc_receive_fsm_str[r_cc_receive_fsm.read()] 555 << " | " << multi_ack_fsm_str[r_multi_ack_fsm.read()] 556 << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()] 557 << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()] 559 558 << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl; 560 561 //m_llsc_table.print_trace(); 562 559 std::cout << " " << alloc_dir_fsm_str[r_alloc_dir_fsm.read()] 560 << " | " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()] 561 << " | " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()] 562 << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; 563 563 } 564 564 … … 1309 1309 switch(r_read_fsm.read()) 1310 1310 { 1311 1311 /////////////// 1312 1312 case READ_IDLE: 1313 1313 // waiting a read request … … 1317 1317 1318 1318 #if DEBUG_MEMC_READ 1319 if(m_debug_read_fsm) 1320 { 1321 std::cout << " <MEMC " << name() << " READ_IDLE> Read request:" 1322 << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read() 1323 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() 1324 << " / pktid = " << std::hex << m_cmd_read_pktid_fifo.read() 1325 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 1326 } 1319 if(m_debug_read_fsm) 1320 std::cout << " <MEMC " << name() << " READ_IDLE> Read request:" 1321 << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read() 1322 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() 1323 << " / pktid = " << std::hex << m_cmd_read_pktid_fifo.read() 1324 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 1327 1325 #endif 1328 1326 r_read_fsm = READ_DIR_REQ; … … 1341 1339 1342 1340 #if DEBUG_MEMC_READ 1343 if(m_debug_read_fsm) 1344 { 1345 std::cout 1346 << " <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " 1347 << std::endl; 1348 } 1341 if(m_debug_read_fsm) 1342 std::cout << " <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl; 1349 1343 #endif 1350 1344 break; … … 1400 1394 1401 1395 #if DEBUG_MEMC_READ 1402 if(m_debug_read_fsm) 1403 { 1404 std::cout 1405 << " <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: " 1406 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 1407 << " / hit = " << std::dec << entry.valid 1408 << " / count = " <<std::dec << entry.count 1409 << " / is_cnt = " << entry.is_cnt << std::endl; 1410 if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) 1411 { 1412 std::cout 1413 << " <MEMC " << name() << " READ_DIR_LOCK> global_llsc_table LL access" << std::endl; 1414 } 1415 } 1396 if(m_debug_read_fsm) 1397 { 1398 std::cout << " <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: " 1399 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 1400 << " / hit = " << std::dec << entry.valid 1401 << " / count = " <<std::dec << entry.count 1402 << " / is_cnt = " << entry.is_cnt; 1403 if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl; 1404 else std::cout << std::endl; 1405 } 1416 1406 #endif 1417 1407 } 1418 1408 else 1419 1409 { 1420 std::cout 1421 << "VCI_MEM_CACHE ERROR " << name() 1422 << " READ_DIR_LOCK state" << std::endl 1423 << "Bad DIR allocation" << std::endl; 1424 1410 std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_DIR_LOCK state" 1411 << "Bad DIR allocation" << std::endl; 1425 1412 exit(0); 1426 1413 } … … 1439 1426 if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) 1440 1427 { 1441 // signals generation1442 1428 // check if this is an instruction read, this means pktid is either 1443 1429 // TYPE_READ_INS_UNC 0bX010 with TSAR encoding … … 1496 1482 1497 1483 #if DEBUG_MEMC_READ 1498 if(m_debug_read_fsm) 1499 { 1500 std::cout 1501 << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 1502 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() 1503 << " / set = " << std::dec << set 1504 << " / way = " << way 1505 << " / owner_id = " << entry.owner.srcid 1506 << " / owner_ins = " << entry.owner.inst 1507 << " / count = " << entry.count 1508 << " / is_cnt = " << entry.is_cnt << std::endl; 1509 } 1484 if(m_debug_read_fsm) 1485 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 1486 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() 1487 << " / set = " << std::dec << set 1488 << " / way = " << way 1489 << " / owner_id = " << entry.owner.srcid 1490 << " / owner_ins = " << entry.owner.inst 1491 << " / count = " << entry.count 1492 << " / is_cnt = " << entry.is_cnt << std::endl; 1510 1493 #endif 1511 1494 … … 1526 1509 } 1527 1510 1511 /////////////////// 1512 case READ_HEAP_REQ: // Get the lock to the HEAP directory 1513 { 1514 if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 1515 { 1516 r_read_fsm = READ_HEAP_LOCK; 1517 } 1518 1519 #if DEBUG_MEMC_READ 1520 if(m_debug_read_fsm) 1521 std::cout << " <MEMC " << name() << " READ_HEAP_REQ>" 1522 << " Requesting HEAP lock " << std::endl; 1523 #endif 1524 break; 1525 } 1526 1528 1527 //////////////////// 1529 case READ_HEAP_REQ: 1530 // Get the lock to the HEAP directory 1531 { 1532 if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 1533 { 1534 r_read_fsm = READ_HEAP_LOCK; 1535 } 1536 1537 #if DEBUG_MEMC_READ 1538 if(m_debug_read_fsm) 1539 { 1540 std::cout 1541 << " <MEMC " << name() << " READ_HEAP_REQ> Requesting HEAP lock " 1542 << std::endl; 1543 } 1544 #endif 1545 break; 1546 } 1547 1548 //////////////////// 1549 case READ_HEAP_LOCK: 1550 // read data in cache, update the directory 1551 // and prepare the HEAP update 1528 case READ_HEAP_LOCK: // read data in cache, update the directory 1529 // and prepare the HEAP update 1552 1530 { 1553 1531 if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) … … 1627 1605 1628 1606 #if DEBUG_MEMC_READ 1629 if(m_debug_read_fsm) 1630 { 1631 std::cout << " <MEMC " << name() << " READ_HEAP_LOCK> Update directory:" 1632 << " tag = " << std::hex << entry.tag 1633 << " set = " << std::dec << set 1634 << " way = " << way 1635 << " count = " << entry.count 1636 << " is_cnt = " << entry.is_cnt << std::endl; 1637 } 1607 if(m_debug_read_fsm) 1608 std::cout << " <MEMC " << name() << " READ_HEAP_LOCK> Update directory:" 1609 << " tag = " << std::hex << entry.tag 1610 << " set = " << std::dec << set 1611 << " way = " << way 1612 << " count = " << entry.count 1613 << " is_cnt = " << entry.is_cnt << std::endl; 1638 1614 #endif 1639 1615 } 1640 1616 else 1641 1617 { 1642 std::cout 1643 << "VCI_MEM_CACHE ERROR " << name() 1644 << " READ_HEAP_LOCK state" << std::endl 1645 << "Bad HEAP allocation" << std::endl; 1646 1618 std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK" 1619 << "Bad HEAP allocation" << std::endl; 1647 1620 exit(0); 1648 1621 } 1649 1650 break; 1651 } 1652 1622 break; 1623 } 1653 1624 ///////////////////// 1654 case READ_HEAP_WRITE: // add a entry in the heap1625 case READ_HEAP_WRITE: // add an entry in the heap 1655 1626 { 1656 1627 if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) … … 1678 1649 1679 1650 #if DEBUG_MEMC_READ 1680 if(m_debug_read_fsm) 1681 { 1682 std::cout 1683 << " <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:" 1684 << " owner_id = " << heap_entry.owner.srcid 1685 << " owner_ins = " << heap_entry.owner.inst << std::endl; 1686 } 1651 if(m_debug_read_fsm) 1652 std::cout << " <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:" 1653 << " owner_id = " << heap_entry.owner.srcid 1654 << " owner_ins = " << heap_entry.owner.inst << std::endl; 1687 1655 #endif 1688 1656 } 1689 1657 else 1690 1658 { 1691 std::cout 1692 << "VCI_MEM_CACHE ERROR " << name() 1693 << " READ_HEAP_WRITE state" << std::endl 1694 << "Bad HEAP allocation" << std::endl; 1695 1659 std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE" 1660 << "Bad HEAP allocation" << std::endl; 1696 1661 exit(0); 1697 1662 } 1698 1663 break; 1699 1664 } 1700 1701 1665 ///////////////////// 1702 1666 case READ_HEAP_ERASE: … … 1717 1681 else 1718 1682 { 1719 std::cout 1720 << "VCI_MEM_CACHE ERROR " << name() 1721 << " READ_HEAP_ERASE state" << std::endl 1722 << "Bad HEAP allocation" << std::endl; 1723 1683 std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE" 1684 << "Bad HEAP allocation" << std::endl; 1724 1685 exit(0); 1725 1686 } … … 1753 1714 else 1754 1715 { 1755 std::cout << "VCI_MEM_CACHE ERROR " << name() 1756 << " READ_HEAP_LAST state" << std::endl; 1757 std::cout << "Bad HEAP allocation" << std::endl; 1716 std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST" 1717 << "Bad HEAP allocation" << std::endl; 1758 1718 exit(0); 1759 1719 } 1760 1720 break; 1761 1721 } 1762 1763 1722 ////////////// 1764 1723 case READ_RSP: // request the TGT_RSP FSM to return data … … 1778 1737 1779 1738 #if DEBUG_MEMC_READ 1780 if(m_debug_read_fsm) 1781 { 1782 std::cout << " <MEMC " << name() << " READ_RSP> Request the TGT_RSP FSM to return data:" 1783 << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read() 1784 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() 1785 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 1786 } 1787 #endif 1788 } 1789 break; 1790 } 1791 1739 if(m_debug_read_fsm) 1740 std::cout << " <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:" 1741 << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read() 1742 << " / address = " << std::hex << m_cmd_read_addr_fifo.read() 1743 << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; 1744 #endif 1745 } 1746 break; 1747 } 1792 1748 /////////////////// 1793 1749 case READ_TRT_LOCK: // read miss : check the Transaction Table … … 1815 1771 1816 1772 #if DEBUG_MEMC_READ 1817 if(m_debug_read_fsm) 1818 { 1819 std::cout << " <MEMC " << name() << " READ_TRT_LOCK> Check TRT:" 1820 << " hit_read = " << hit_read 1821 << " / hit_write = " << hit_write 1822 << " / full = " << !wok << std::endl; 1823 } 1773 if(m_debug_read_fsm) 1774 std::cout << " <MEMC " << name() << " READ_TRT_LOCK> Check TRT:" 1775 << " hit_read = " << hit_read 1776 << " / hit_write = " << hit_write 1777 << " / full = " << !wok << std::endl; 1824 1778 #endif 1825 1779 } … … 1845 1799 r_read_ll_key.read()); 1846 1800 #if DEBUG_MEMC_READ 1847 if(m_debug_read_fsm) 1848 { 1849 std::cout << " <MEMC " << name() << " READ_TRT_SET> Write in Transaction Table: " << std::hex 1850 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 1851 << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read() 1852 << std::endl; 1853 } 1801 if(m_debug_read_fsm) 1802 std::cout << " <MEMC " << name() << " READ_TRT_SET> Write in Transaction Table:" 1803 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 1804 << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read() << std::endl; 1854 1805 #endif 1855 1806 r_read_fsm = READ_TRT_REQ; … … 1859 1810 1860 1811 ////////////////// 1861 case READ_TRT_REQ: 1862 { 1863 // consume the read request in the FIFO, 1864 // and send it to the ixr_cmd_fsm 1865 1812 case READ_TRT_REQ: // consume the read request in FIFO and send it to IXR_CMD_FSM 1813 { 1866 1814 if(not r_read_to_ixr_cmd_req) 1867 1815 { … … 1873 1821 1874 1822 #if DEBUG_MEMC_READ 1875 if(m_debug_read_fsm) 1876 { 1877 std::cout 1878 << " <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address " 1879 << std::hex << m_cmd_read_addr_fifo.read() << std::endl; 1880 } 1823 if(m_debug_read_fsm) 1824 std::cout << " <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address " 1825 << std::hex << m_cmd_read_addr_fifo.read() << std::endl; 1881 1826 #endif 1882 1827 } … … 2921 2866 /////////////////////////////////////////////////////////////////////// 2922 2867 // The IXR_CMD fsm controls the command packets to the XRAM : 2923 // It handles requests from the READ, WRITE, CAS &XRAM_RSP FSMs2868 // It handles requests from the READ, WRITE, CAS, XRAM_RSP FSMs 2924 2869 // with a round-robin priority. 2925 2870 // 2926 // - It sends a single cellVCI read request to the XRAM in case of MISS2871 // - It sends a single flit VCI read request to the XRAM in case of MISS 2927 2872 // posted by the READ, WRITE or CAS FSMs : the TRDID field contains 2928 2873 // the Transaction Tab index. 2929 // The VCI response is a multi- cellpacket : the N cells contain2874 // The VCI response is a multi-flit packet : the N cells contain 2930 2875 // the N data words. 2931 2876 // 2932 // - It sends a multi- cellVCI write when the XRAM_RSP FSM, WRITE FSM2877 // - It sends a multi-flit VCI write when the XRAM_RSP FSM, WRITE FSM 2933 2878 // or CAS FSM request to save a dirty line to the XRAM. 2934 // The VCI response is a single cellpacket.2879 // The VCI response is a single flit packet. 2935 2880 //////////////////////////////////////////////////////////////////////// 2936 2881 2937 2882 switch(r_ixr_cmd_fsm.read()) 2938 2883 { 2939 2884 //////////////////////// 2940 2885 case IXR_CMD_READ_IDLE: 2941 if (r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE; 2942 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE; 2943 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA; 2944 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ_NLINE; 2945 break; 2946 //////////////////////// 2886 { 2887 if (r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 2888 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 2889 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 2890 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 2891 break; 2892 } 2893 //////////////////////// 2947 2894 case IXR_CMD_WRITE_IDLE: 2948 if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE; 2949 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA; 2950 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ_NLINE; 2951 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE; 2952 break; 2953 //////////////////////// 2895 { 2896 if (r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 2897 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 2898 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 2899 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 2900 break; 2901 } 2902 //////////////////////// 2954 2903 case IXR_CMD_CAS_IDLE: 2955 if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA; 2956 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ_NLINE; 2957 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE; 2958 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE; 2959 break; 2960 //////////////////////// 2904 { 2905 if (r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 2906 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 2907 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 2908 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 2909 break; 2910 } 2911 //////////////////////// 2961 2912 case IXR_CMD_XRAM_IDLE: 2962 if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ_NLINE; 2963 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE; 2964 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE; 2965 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA; 2966 break; 2967 ///////////////////////// // send a get request to XRAM 2968 case IXR_CMD_READ_NLINE: 2913 { 2914 if (r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 2915 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 2916 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 2917 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 2918 break; 2919 } 2920 ////////////////// // send a get from READ FSM 2921 case IXR_CMD_READ: 2922 { 2969 2923 if(p_vci_ixr.cmdack) 2970 2924 { … … 2974 2928 #if DEBUG_MEMC_IXR_CMD 2975 2929 if(m_debug_ixr_cmd_fsm) 2976 { 2977 std::cout << " <MEMC " << name() 2978 << " IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl; 2979 } 2980 #endif 2981 } 2982 break; 2983 ////////////////////////// 2984 case IXR_CMD_WRITE_NLINE: // send a put or get command to XRAM 2930 std::cout << " <MEMC " << name() << " IXR_CMD_READ>" 2931 << " Send a get request to xram / address = " << std::hex 2932 << (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4) << std::endl; 2933 #endif 2934 } 2935 break; 2936 } 2937 /////////////////// 2938 case IXR_CMD_WRITE: // send a put or get from WRITE FSM 2939 { 2985 2940 if(p_vci_ixr.cmdack) 2986 2941 { … … 3000 2955 #if DEBUG_MEMC_IXR_CMD 3001 2956 if(m_debug_ixr_cmd_fsm) 3002 { 3003 std::cout << " <MEMC " << name()3004 << " IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;3005 } 2957 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE>" 2958 << " Send a put request to xram / address = " << std::hex 2959 << (addr_t)((r_write_to_ixr_cmd_nline.read() * m_words + 2960 r_ixr_cmd_cpt.read()) * 4 ) << std::endl; 3006 2961 #endif 3007 2962 } … … 3013 2968 #if DEBUG_MEMC_IXR_CMD 3014 2969 if(m_debug_ixr_cmd_fsm) 3015 { 3016 std::cout << " <MEMC " << name() 3017 << " IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl; 3018 } 3019 #endif 3020 } 3021 } 3022 break; 3023 ////////////////////// 3024 case IXR_CMD_CAS_NLINE: // send a put or get command to XRAM 2970 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE>" 2971 << " Send a get request to xram / address = " << std::hex 2972 << (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4) << std::endl; 2973 #endif 2974 } 2975 } 2976 break; 2977 } 2978 ///////////////// 2979 case IXR_CMD_CAS: // send a put or get command from CAS FSM 2980 { 3025 2981 if(p_vci_ixr.cmdack) 3026 2982 { … … 3040 2996 #if DEBUG_MEMC_IXR_CMD 3041 2997 if(m_debug_ixr_cmd_fsm) 3042 { 3043 std::cout << " <MEMC " << name()3044 << " IXR_CMD_CAS_NLINE> Send a put request to xram" << std::endl;3045 } 2998 std::cout << " <MEMC " << name() << " IXR_CMD_CAS>" 2999 << " Send a put request to xram / address = " << std::hex 3000 << (addr_t)( (r_cas_to_ixr_cmd_nline.read() * m_words + 3001 r_ixr_cmd_cpt.read()) * 4 ) << std::endl; 3046 3002 #endif 3047 3003 } … … 3053 3009 #if DEBUG_MEMC_IXR_CMD 3054 3010 if(m_debug_ixr_cmd_fsm) 3055 { 3056 std::cout << " <MEMC " << name() 3057 << " IXR_CMD_CAS_NLINE> Send a get request to xram" << std::endl; 3058 } 3059 #endif 3060 } 3061 } 3062 break; 3063 //////////////////////// 3064 case IXR_CMD_XRAM_DATA: // send a put command to XRAM 3011 std::cout << " <MEMC " << name() << " IXR_CMD_CAS>" 3012 << " Send a get request to xram / address = " << std::hex 3013 << (addr_t)(r_cas_to_ixr_cmd_nline.read()*m_words*4) << std::endl; 3014 #endif 3015 } 3016 } 3017 break; 3018 } 3019 ////////////////// 3020 case IXR_CMD_XRAM: // send a put from XRAM_RSP FSM 3021 { 3065 3022 if(p_vci_ixr.cmdack) 3066 3023 { … … 3078 3035 #if DEBUG_MEMC_IXR_CMD 3079 3036 if(m_debug_ixr_cmd_fsm) 3080 { 3081 std::cout << " <MEMC " << name() 3082 << " IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl; 3083 } 3084 #endif 3085 } 3086 break; 3037 std::cout << " <MEMC " << name() << " IXR_CMD_XRAM>" 3038 << " Send a put request to xram / address = " << std::hex 3039 << (addr_t)( (r_xram_rsp_to_ixr_cmd_nline.read() * m_words + 3040 r_ixr_cmd_cpt.read()) * 4 ) << std::endl; 3041 #endif 3042 } 3043 break; 3044 } 3087 3045 3088 3046 } // end switch r_ixr_cmd_fsm … … 3225 3183 // 3226 3184 // When a response is available, the corresponding TRT entry 3227 // must becopied in a local buffer to be written in the cache.3185 // is copied in a local buffer to be written in the cache. 3228 3186 // The FSM takes the lock protecting the TRT, and the lock protecting the DIR. 3229 3187 // It selects a cache slot and writes the line in the cache. … … 3239 3197 switch(r_xram_rsp_fsm.read()) 3240 3198 { 3241 3242 case XRAM_RSP_IDLE: // scan the XRAM responses to get theTRT index (round robin)3199 /////////////////// 3200 case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin) 3243 3201 { 3244 3202 size_t ptr = r_xram_rsp_trt_index.read(); … … 3246 3204 for(size_t i=0 ; i<lines ; i++) 3247 3205 { 3248 size_t index = (i+ptr+1) %lines;3206 size_t index = (i+ptr+1) %lines; 3249 3207 if(r_ixr_rsp_to_xram_rsp_rok[index]) 3250 3208 { … … 3254 3212 3255 3213 #if DEBUG_MEMC_XRAM_RSP 3256 if(m_debug_xram_rsp_fsm) 3257 { 3258 std::cout << " <MEMC " << name() << " XRAM_RSP_IDLE> Available cache line in TRT:" 3259 << " index = " << std::dec << index << std::endl; 3260 } 3214 if(m_debug_xram_rsp_fsm) 3215 std::cout << " <MEMC " << name() << " XRAM_RSP_IDLE>" 3216 << " Available cache line in TRT:" 3217 << " index = " << std::dec << index << std::endl; 3261 3218 #endif 3262 3219 break; … … 3266 3223 } 3267 3224 /////////////////////// 3268 case XRAM_RSP_DIR_LOCK: 3269 // Takes the lock on the directory 3270 // Takes the lock on TRT 3271 // Copy the TRT entry in a local buffer 3225 case XRAM_RSP_DIR_LOCK: // Takes the DIR lock and the TRT lock 3226 // Copy the TRT entry in a local buffer 3272 3227 { 3273 3228 if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) && … … 3276 3231 // copy the TRT entry in the r_xram_rsp_trt_buf local buffer 3277 3232 size_t index = r_xram_rsp_trt_index.read(); 3278 3279 TransactionTabEntry trt_entry(m_trt.read(index)); 3280 r_xram_rsp_trt_buf.copy(trt_entry); // TRT entry local buffer 3233 r_xram_rsp_trt_buf.copy( m_trt.read(index) ); 3281 3234 3282 3235 r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; 3236 3237 // TransactionTabEntry trt_entry(m_trt.read(index)); 3238 // r_xram_rsp_trt_buf.copy(trt_entry); // TRT entry local buffer 3283 3239 3284 3240 #if DEBUG_MEMC_XRAM_RSP 3285 3241 if(m_debug_xram_rsp_fsm) 3286 { 3287 std::cout << " <MEMC " << name() 3288 << " XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl; 3289 } 3242 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_LOCK>" 3243 << " Get access to DIR and TRT" << std::endl; 3290 3244 #endif 3291 3245 } … … 3293 3247 } 3294 3248 /////////////////////// 3295 case XRAM_RSP_TRT_COPY: 3296 // Select a victim cache line 3297 { 3298 if((r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)) 3249 case XRAM_RSP_TRT_COPY: // Select a victim cache line 3250 // and copy it in a local buffer 3251 { 3252 if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and 3253 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) ) 3299 3254 { 3300 3255 // selects & extracts a victim line from cache … … 3310 3265 3311 3266 r_xram_rsp_victim_copy = victim.owner.srcid; 3267 3312 3268 #if L1_MULTI_CACHE 3313 3269 r_xram_rsp_victim_copy_cache= victim.owner.cache_id; … … 3333 3289 3334 3290 #if DEBUG_MEMC_XRAM_RSP 3335 if(m_debug_xram_rsp_fsm) 3336 { 3337 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_COPY> Select a slot: " 3338 << " way = " << std::dec << way 3339 << " / set = " << set 3340 << " / inval_required = " << inval << std::endl; 3341 } 3291 if(m_debug_xram_rsp_fsm) 3292 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_COPY>" 3293 << " Select a slot: " 3294 << " way = " << std::dec << way 3295 << " / set = " << set 3296 << " / inval_required = " << inval << std::endl; 3342 3297 #endif 3343 3298 } 3344 3299 else 3345 3300 { 3346 std::cout << "VCI_MEM_CACHE ERROR " << name() 3347 << " XRAM_RSP_TRT_COPY state" << std::endl 3348 << "bad TRT allocation" << std::endl; 3349 3301 std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_TRT_COPY" 3302 << " bad TRT or DIR allocation" << std::endl; 3350 3303 exit(0); 3351 3304 } … … 3353 3306 } 3354 3307 ///////////////////////// 3355 case XRAM_RSP_INVAL_LOCK: // check a possible pending inval3308 case XRAM_RSP_INVAL_LOCK: // Take the UPT lock to check a possible pending inval 3356 3309 { 3357 3310 if(r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP) 3358 3311 { 3359 size_t index ;3360 if(m_upt.search_inval(r_xram_rsp_trt_buf.nline, index)) 3312 size_t index = 0; 3313 if(m_upt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval 3361 3314 { 3362 3315 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 3363 3316 3364 3317 #if DEBUG_MEMC_XRAM_RSP 3365 if(m_debug_xram_rsp_fsm) 3366 { 3367 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK> Get acces to UPT," 3368 << " but an invalidation is already registered at this address" << std::endl; 3369 m_upt.print(); 3370 } 3371 #endif 3372 3373 } 3374 else if(m_upt.is_full() && r_xram_rsp_victim_inval.read()) 3318 if(m_debug_xram_rsp_fsm) 3319 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 3320 << " Get acces to UPT, but line invalidation registered" 3321 << " / nline = " << std::hex << r_xram_rsp_trt_buf.nline 3322 << " / index = " << std::dec << index << std::endl; 3323 #endif 3324 3325 } 3326 else if(m_upt.is_full() && r_xram_rsp_victim_inval.read()) // UPT full 3375 3327 { 3376 3328 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 3377 3329 3378 3330 #if DEBUG_MEMC_XRAM_RSP 3379 if(m_debug_xram_rsp_fsm) 3380 { 3381 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK> Get acces to UPT," 3382 << " but the table is full" << std::endl; 3383 m_upt.print(); 3384 } 3331 if(m_debug_xram_rsp_fsm) 3332 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 3333 << " Get acces to UPT, but inval required and UPT full" << std::endl; 3385 3334 #endif 3386 3335 } … … 3390 3339 3391 3340 #if DEBUG_MEMC_XRAM_RSP 3392 if(m_debug_xram_rsp_fsm) 3393 { 3394 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl; 3395 } 3341 if(m_debug_xram_rsp_fsm) 3342 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 3343 << " Get acces to UPT" << std::endl; 3396 3344 #endif 3397 3345 } … … 3400 3348 } 3401 3349 ///////////////////////// 3402 case XRAM_RSP_INVAL_WAIT: // returns to DIR_LOCK to retry 3403 { 3350 case XRAM_RSP_INVAL_WAIT: // release all locks and returns to DIR_LOCK to retry 3351 { 3352 3353 #if DEBUG_MEMC_XRAM_RSP 3354 if(m_debug_xram_rsp_fsm) 3355 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_WAIT>" 3356 << " Release all locks and retry" << std::endl; 3357 #endif 3404 3358 r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; 3405 3359 break; … … 3407 3361 /////////////////////// 3408 3362 case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory) 3409 // and possibly set an inval request in UPT 3410 { 3411 // signals generation 3363 // and possibly set an inval request in UPT 3364 { 3412 3365 // check if this is an instruction read, this means pktid is either 3413 3366 // TYPE_READ_INS_UNC 0bX010 with TSAR encoding 3414 3367 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 3415 3368 bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) && r_xram_rsp_trt_buf.proc_read; 3369 3416 3370 // check if this is a cached read, this means pktid is either 3417 3371 // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding … … 3419 3373 bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) && r_xram_rsp_trt_buf.proc_read; 3420 3374 3421 // update data 3375 bool dirty = false; 3376 3377 // update cache data 3422 3378 size_t set = r_xram_rsp_victim_set.read(); 3423 3379 size_t way = r_xram_rsp_victim_way.read(); … … 3426 3382 m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]); 3427 3383 3384 dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[word] != 0); 3385 3428 3386 if(m_monitor_ok) 3429 3387 { … … 3432 3390 } 3433 3391 } 3434 // compute dirty 3435 bool dirty = false; 3436 for(size_t i=0; i<m_words; i++) dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[i] != 0); 3437 // update directory 3392 3393 // update cache directory 3438 3394 DirectoryEntry entry; 3439 3395 entry.valid = true; … … 3463 3419 m_cache_directory.write(set, way, entry); 3464 3420 3421 // request an invalidattion request in UPT for victim line 3465 3422 if(r_xram_rsp_victim_inval.read()) 3466 3423 { 3467 bool br dcast = r_xram_rsp_victim_is_cnt.read();3468 size_t index = 0;3469 size_t count_copies 3424 bool broadcast = r_xram_rsp_victim_is_cnt.read(); 3425 size_t index = 0; 3426 size_t count_copies = r_xram_rsp_victim_count.read(); 3470 3427 3471 3428 bool wok = m_upt.set(false, // it's an inval transaction 3472 brdcast, // set brdcast bit 3473 false, // it does not need a response 3474 0, // srcid 3475 0, // trdid 3476 0, // pktid 3477 r_xram_rsp_victim_nline.read(), 3478 count_copies, 3479 index); 3429 broadcast, // set broadcast bit 3430 false, // it does not need a response 3431 0, // srcid 3432 0, // trdid 3433 0, // pktid 3434 r_xram_rsp_victim_nline.read(), 3435 count_copies, 3436 index); 3437 3480 3438 r_xram_rsp_upt_index = index; 3481 3439 3482 3440 if(!wok) 3483 3441 { 3484 std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_ HEAP_LAST state" << std::endl;3485 std::cout << "an update_tab entry was free but write isunsuccessful" << std::endl;3442 std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_DIR_UPDT" 3443 << " update_tab entry free but write unsuccessful" << std::endl; 3486 3444 exit(0); 3487 3445 } … … 3489 3447 3490 3448 #if DEBUG_MEMC_XRAM_RSP 3491 if(m_debug_xram_rsp_fsm) 3492 { 3493 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_UPDT> Directory update: " 3494 << " way = " << std::dec << way 3495 << " / set = " << set 3496 << " / owner_id = " << entry.owner.srcid 3497 << " / owner_ins = " << entry.owner.inst 3498 << " / count = " << entry.count 3499 << " / is_cnt = " << entry.is_cnt << std::endl; 3500 if(r_xram_rsp_victim_inval.read()) 3501 std::cout << " Invalidation request for victim line " 3502 << std::hex << r_xram_rsp_victim_nline.read() 3503 << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl; 3504 } 3505 #endif 3506 3507 // If the victim is not dirty, we don't need another XRAM put transaction, 3508 // and we canwe erase the TRT entry 3449 if(m_debug_xram_rsp_fsm) 3450 { 3451 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_UPDT>" 3452 << " Cache update: " 3453 << " way = " << std::dec << way 3454 << " / set = " << set 3455 << " / owner_id = " << entry.owner.srcid 3456 << " / owner_ins = " << entry.owner.inst 3457 << " / count = " << entry.count 3458 << " / is_cnt = " << entry.is_cnt << std::endl; 3459 if(r_xram_rsp_victim_inval.read()) 3460 std::cout << " Invalidation request for victim line " 3461 << std::hex << r_xram_rsp_victim_nline.read() 3462 << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl; 3463 } 3464 #endif 3465 3466 // If the victim is not dirty, we don't need another XRAM put transaction, 3467 // and we can erase the TRT entry 3509 3468 if(!r_xram_rsp_victim_dirty.read()) m_trt.erase(r_xram_rsp_trt_index.read()); 3510 3469 3511 3470 // Next state 3512 3471 if(r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; 3513 else if(r_xram_rsp_trt_buf.proc_read) 3514 else if(r_xram_rsp_victim_inval.read()) 3515 else 3472 else if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; 3473 else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 3474 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 3516 3475 break; 3517 3476 } 3518 3477 //////////////////////// 3519 case XRAM_RSP_TRT_DIRTY: // set the TRT entry ( writeto XRAM) if the victim is dirty3478 case XRAM_RSP_TRT_DIRTY: // set the TRT entry (PUT to XRAM) if the victim is dirty 3520 3479 { 3521 3480 if(r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) … … 3534 3493 3535 3494 #if DEBUG_MEMC_XRAM_RSP 3536 if(m_debug_xram_rsp_fsm) 3537 { 3538 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:" 3539 << " dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl; 3540 } 3541 #endif 3542 if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; 3543 else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 3544 else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 3495 if(m_debug_xram_rsp_fsm) 3496 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>" 3497 << " Set TRT entry for the put transaction" 3498 << " / dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl; 3499 #endif 3500 if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; 3501 else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 3502 else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 3545 3503 } 3546 3504 break; … … 3554 3512 r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; 3555 3513 r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; 3556 for(size_t i=0; i < m_words; i++) r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; 3514 for(size_t i=0; i < m_words; i++) 3515 { 3516 r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; 3517 } 3557 3518 r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; 3558 3519 r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; … … 3561 3522 r_xram_rsp_to_tgt_rsp_req = true; 3562 3523 3563 if(r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL;3524 if(r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL; 3564 3525 else if(r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 3565 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 3566 3526 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 3567 3527 3568 3528 #if DEBUG_MEMC_XRAM_RSP 3569 if(m_debug_xram_rsp_fsm) 3570 { 3571 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:" 3572 << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid 3573 << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 3574 << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl; 3575 } 3529 if(m_debug_xram_rsp_fsm) 3530 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_RSP>" 3531 << " Request the TGT_RSP FSM to return data:" 3532 << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid 3533 << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 3534 << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl; 3576 3535 #endif 3577 3536 } … … 3601 3560 3602 3561 if(r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 3603 else if(not_last_multi_req) 3604 else 3562 else if(not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; 3563 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 3605 3564 3606 3565 #if DEBUG_MEMC_XRAM_RSP 3607 if(m_debug_xram_rsp_fsm) 3608 { 3609 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL> Send an inval request to CC_SEND FSM:" 3610 << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl; 3611 } 3566 if(m_debug_xram_rsp_fsm) 3567 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL>" 3568 << " Send an inval request to CC_SEND FSM" 3569 << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl; 3612 3570 #endif 3613 3571 } … … 3622 3580 r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read(); 3623 3581 r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read(); 3624 for(size_t i=0; i<m_words ; i++) r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i]; 3582 for(size_t i=0; i<m_words ; i++) 3583 { 3584 r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i]; 3585 } 3625 3586 m_cpt_write_dirty++; 3626 3587 3627 3588 bool multi_req = !r_xram_rsp_victim_is_cnt.read() && r_xram_rsp_victim_inval.read(); 3628 3589 bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1); 3590 3629 3591 if(not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; 3630 else 3592 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 3631 3593 3632 3594 #if DEBUG_MEMC_XRAM_RSP 3633 if(m_debug_xram_rsp_fsm) 3634 { 3635 std::cout << " <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:" 3636 << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl; 3637 } 3638 #endif 3639 } 3640 break; 3641 } 3642 3595 if(m_debug_xram_rsp_fsm) 3596 std::cout << " <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY>" 3597 << " Send the put request to IXR_CMD FSM" 3598 << " / victim line = " << r_xram_rsp_victim_nline.read() << std::endl; 3599 #endif 3600 } 3601 break; 3602 } 3643 3603 ///////////////////////// 3644 case XRAM_RSP_HEAP_REQ: 3645 // Get the lock to the HEAP directory 3604 case XRAM_RSP_HEAP_REQ: // Get the lock to the HEAP 3646 3605 { 3647 3606 if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) … … 3651 3610 3652 3611 #if DEBUG_MEMC_XRAM_RSP 3653 if(m_debug_xram_rsp_fsm) 3654 { 3655 std::cout 3656 << " <MEMC " << name() << " XRAM_RSP_HEAP_REQ> Requesting HEAP lock " 3657 << std::endl; 3658 } 3659 #endif 3660 break; 3661 } 3662 3612 if(m_debug_xram_rsp_fsm) 3613 std::cout << " <MEMC " << name() << " XRAM_RSP_HEAP_REQ>" 3614 << " Requesting HEAP lock" << std::endl; 3615 #endif 3616 break; 3617 } 3663 3618 ///////////////////////// 3664 case XRAM_RSP_HEAP_ERASE: // erase the list of copies and sentinvalidations3619 case XRAM_RSP_HEAP_ERASE: // erase the copies and send invalidations 3665 3620 { 3666 3621 if(r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) … … 3693 3648 3694 3649 #if DEBUG_MEMC_XRAM_RSP 3695 if(m_debug_xram_rsp_fsm) 3696 { 3697 std::cout << " <MEMC " << name() << " XRAM_RSP_HEAP_ERASE> Erase the list of copies:" 3698 << " srcid = " << std::dec << entry.owner.srcid 3699 << " / inst = " << std::dec << entry.owner.inst << std::endl; 3700 } 3650 if(m_debug_xram_rsp_fsm) 3651 std::cout << " <MEMC " << name() << " XRAM_RSP_HEAP_ERASE>" 3652 << " Erase copy:" 3653 << " srcid = " << std::dec << entry.owner.srcid 3654 << " / inst = " << std::dec << entry.owner.inst << std::endl; 3701 3655 #endif 3702 3656 } … … 3704 3658 } 3705 3659 ///////////////////////// 3706 case XRAM_RSP_HEAP_LAST: // last member of the list3660 case XRAM_RSP_HEAP_LAST: // last copy 3707 3661 { 3708 3662 if(r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP) 3709 3663 { 3710 std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST state" << std::endl;3711 std::cout << "bad HEAP allocation" << std::endl;3664 std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST" 3665 << " bad HEAP allocation" << std::endl; 3712 3666 exit(0); 3713 3667 } … … 3736 3690 3737 3691 #if DEBUG_MEMC_XRAM_RSP 3738 if(m_debug_xram_rsp_fsm) 3739 { 3740 std::cout << " <MEMC " << name() << " XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl; 3741 } 3692 if(m_debug_xram_rsp_fsm) 3693 std::cout << " <MEMC " << name() << " XRAM_RSP_HEAP_LAST>" 3694 << " Heap housekeeping" << std::endl; 3742 3695 #endif 3743 3696 break; … … 3750 3703 // Next state 3751 3704 if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP; 3752 else 3705 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 3753 3706 3754 3707 #if DEBUG_MEMC_XRAM_RSP 3755 if(m_debug_xram_rsp_fsm) 3756 { 3757 std::cout << " <MEMC " << name() << " XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl; 3758 } 3708 if(m_debug_xram_rsp_fsm) 3709 std::cout << " <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>" 3710 << " Error reported by XRAM / erase the TRT entry" << std::endl; 3759 3711 #endif 3760 3712 break; … … 3763 3715 case XRAM_RSP_ERROR_RSP: // Request an error response to TGT_RSP FSM 3764 3716 { 3765 if(!r_xram_rsp_to_tgt_rsp_req.read()) 3717 if(!r_xram_rsp_to_tgt_rsp_req.read()) 3766 3718 { 3767 3719 r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; 3768 3720 r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; 3769 3721 r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; 3770 for(size_t i=0; i < m_words; i++) r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; 3722 for(size_t i=0; i < m_words; i++) 3723 { 3724 r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; 3725 } 3771 3726 r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; 3772 3727 r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; … … 3777 3732 3778 3733 #if DEBUG_MEMC_XRAM_RSP 3779 if(m_debug_xram_rsp_fsm) 3780 { 3781 std::cout << " <MEMC " << name() << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:" 3782 << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; 3783 } 3734 if(m_debug_xram_rsp_fsm) 3735 std::cout << " <MEMC " << name() 3736 << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:" 3737 << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; 3784 3738 #endif 3785 3739 } … … 5151 5105 break; 5152 5106 } 5153 /////////////////// 5107 ///////////////////// 5154 5108 case CAS_BC_UPT_LOCK: // register a broadcast inval transaction in UPT 5155 // write data in cache in case of successful registration5109 // write data in cache in case of successful registration 5156 5110 { 5157 5111 if(r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) … … 6525 6479 switch(r_alloc_dir_fsm.read()) 6526 6480 { 6527 case ALLOC_DIR_RESET: 6528 // Initializes the directory one SET each cycle. All the WAYS of a SET are 6529 // initialize in parallel 6481 case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle. 6482 // All the WAYS of a SET initialized in parallel 6530 6483 6531 6484 r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1); … … 6534 6487 { 6535 6488 m_cache_directory.init(); 6536 6537 6489 r_alloc_dir_fsm = ALLOC_DIR_READ; 6538 6490 } 6539 6491 break; 6540 6492 6541 6493 //////////////////// 6542 6494 case ALLOC_DIR_READ: 6543 6495 if(((r_read_fsm.read() != READ_DIR_REQ) && … … 6682 6634 switch(r_alloc_trt_fsm.read()) 6683 6635 { 6684 6636 //////////////////// 6685 6637 case ALLOC_TRT_READ: 6686 6638 if(r_read_fsm.read() != READ_TRT_LOCK) … … 6704 6656 break; 6705 6657 6706 6658 ///////////////////// 6707 6659 case ALLOC_TRT_WRITE: 6708 6660 if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) && … … 6727 6679 break; 6728 6680 6729 6681 //////////////////// 6730 6682 case ALLOC_TRT_CAS: 6731 6683 if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) && … … 6750 6702 break; 6751 6703 6752 6704 //////////////////////// 6753 6705 case ALLOC_TRT_XRAM_RSP: 6754 6706 if(((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) || … … 6775 6727 break; 6776 6728 6777 6729 //////////////////////// 6778 6730 case ALLOC_TRT_IXR_RSP: 6779 6731 if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) && … … 7210 7162 p_vci_ixr.plen = 64; 7211 7163 7212 if(r_ixr_cmd_fsm.read() == IXR_CMD_READ _NLINE)7164 if(r_ixr_cmd_fsm.read() == IXR_CMD_READ) 7213 7165 { 7214 7166 p_vci_ixr.cmd = vci_param_ext::CMD_READ; … … 7219 7171 p_vci_ixr.eop = true; 7220 7172 } 7221 else if(r_ixr_cmd_fsm.read() == IXR_CMD_CAS _NLINE)7173 else if(r_ixr_cmd_fsm.read() == IXR_CMD_CAS) 7222 7174 { 7223 7175 if(r_cas_to_ixr_cmd_write.read()) … … 7242 7194 } 7243 7195 } 7244 else if(r_ixr_cmd_fsm.read() == IXR_CMD_WRITE _NLINE)7196 else if(r_ixr_cmd_fsm.read() == IXR_CMD_WRITE) 7245 7197 { 7246 7198 if(r_write_to_ixr_cmd_write.read()) … … 7265 7217 } 7266 7218 } 7267 else if(r_ixr_cmd_fsm.read() == IXR_CMD_XRAM _DATA)7219 else if(r_ixr_cmd_fsm.read() == IXR_CMD_XRAM) 7268 7220 { 7269 7221 p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; … … 7583 7535 DspinDhccpParam::dspin_set( 7584 7536 flit, 7585 m_broadcast_ address,7537 m_broadcast_boundaries, 7586 7538 DspinDhccpParam::BROADCAST_BOX); 7587 7539
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