Changeset 396 for trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba
- Timestamp:
- May 28, 2013, 11:02:08 AM (12 years ago)
- Location:
- trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd
r389 r396 2 2 # -*- python -*- 3 3 4 Module('caba:tsar_xbar_cluster', 4 Module('caba:tsar_xbar_cluster', 5 5 classname = 'soclib::caba::TsarXbarCluster', 6 tmpl_parameters = [ 7 parameter.Module('iss_t'), 8 parameter.Int('cmd_width'), 9 parameter.Int('rsp_width'), 6 tmpl_parameters = [ 7 parameter.Int('dspin_cmd_width'), 8 parameter.Int('dspin_rsp_width'), 9 parameter.Module('vci_param_int'), 10 parameter.Module('vci_param_ext'), 10 11 ], 11 header_files = [ '../source/include/tsar_xbar_cluster.h', ], 12 implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], 13 uses = [ 14 Uses('caba:base_module'), 15 Uses('common:mapping_table'), 16 Uses('common:iss2'), 17 Uses('caba:vci_cc_vcache_wrapper', 18 vci_param = 'caba:vci_param', 19 dspin_in_width = parameter.Reference('cmd_width'), 20 dspin_out_width = parameter.Reference('rsp_width'), 12 13 header_files = [ '../source/include/tsar_xbar_cluster.h', ], 14 implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', ], 15 16 uses = [ 17 Uses('caba:base_module'), 18 Uses('common:mapping_table'), 19 Uses('common:iss2'), 20 21 Uses('caba:vci_cc_vcache_wrapper', 22 vci_param = parameter.Reference('vci_param_int'), 23 dspin_in_width = parameter.Reference('dspin_cmd_width'), 24 dspin_out_width = parameter.Reference('dspin_rsp_width'), 21 25 iss_t = 'common:gdb_iss', 22 gdb_iss_t = 'common:mips32el' 23 ), 24 Uses('caba:vci_mem_cache', 26 gdb_iss_t = 'common:mips32el'), 27 28 Uses('caba:vci_simple_ram', 29 vci_param = parameter.Reference('vci_param_int')), 30 31 Uses('caba:vci_simple_ram', 32 vci_param = parameter.Reference('vci_param_ext')), 33 34 Uses('caba:vci_xicu', 35 vci_param = parameter.Reference('vci_param_int')), 36 37 Uses('caba:dspin_local_crossbar', 38 flit_width = parameter.Reference('dspin_cmd_width')), 39 40 Uses('caba:dspin_local_crossbar', 41 flit_width = parameter.Reference('dspin_rsp_width')), 42 43 Uses('caba:virtual_dspin_router', 44 flit_width = parameter.Reference('dspin_cmd_width')), 45 46 Uses('caba:virtual_dspin_router', 47 flit_width = parameter.Reference('dspin_rsp_width')), 48 49 Uses('caba:vci_multi_tty', 50 vci_param = parameter.Reference('vci_param_int')), 51 52 Uses('caba:vci_framebuffer', 53 vci_param = parameter.Reference('vci_param_int')), 54 55 Uses('caba:vci_multi_nic', 56 vci_param = parameter.Reference('vci_param_int')), 57 58 Uses('caba:vci_block_device_tsar', 59 vci_param = parameter.Reference('vci_param_int')), 60 61 Uses('caba:vci_multi_dma', 62 vci_param = parameter.Reference('vci_param_int')), 63 64 Uses('caba:vci_dspin_target_wrapper', 65 vci_param = parameter.Reference('vci_param_int')), 66 67 Uses('caba:vci_dspin_initiator_wrapper', 68 vci_param = parameter.Reference('vci_param_int')), 69 70 Uses('caba:vci_mem_cache', 25 71 vci_param_int = 'caba:vci_param', 26 72 vci_param_ext = 'caba:vci_param_bis', 27 dspin_in_width = parameter.Reference('rsp_width'), 28 dspin_out_width = parameter.Reference('cmd_width') 29 ), 30 Uses('caba:vci_simple_ram', 31 vci_param = 'caba:vci_param_bis' 32 ), 33 Uses('caba:vci_simple_ram', 34 vci_param = 'caba:vci_param' 35 ), 36 Uses('caba:vci_xicu'), 37 Uses('caba:dspin_local_crossbar', 38 flit_width = parameter.Reference('cmd_width') 39 ), 40 Uses('caba:dspin_local_crossbar', 41 flit_width = parameter.Reference('rsp_width') 42 ), 43 Uses('caba:vci_dspin_initiator_wrapper', 44 dspin_cmd_width = parameter.Reference('cmd_width'), 45 dspin_rsp_width = parameter.Reference('rsp_width') 46 ), 47 Uses('caba:vci_dspin_target_wrapper', 48 dspin_cmd_width = parameter.Reference('cmd_width'), 49 dspin_rsp_width = parameter.Reference('rsp_width') 50 ), 51 Uses('caba:virtual_dspin_router', 52 flit_width = parameter.Reference('cmd_width') 53 ), 54 Uses('caba:virtual_dspin_router', 55 flit_width = parameter.Reference('rsp_width') 56 ), 57 Uses('caba:vci_multi_tty'), 58 Uses('caba:vci_framebuffer'), 59 Uses('caba:vci_multi_nic'), 60 Uses('caba:vci_block_device_tsar'), 61 Uses('caba:vci_multi_dma'), 62 Uses('common:elf_file_loader'), 63 ], 64 ports = [ 65 Port('caba:bit_in' , 'p_resetn' , auto = 'resetn'), 66 Port('caba:clock_in' , 'p_clk' , auto = 'clock'), 67 Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')), 68 Port('caba:dspin_input' , 'p_cmd_in' , [2, 4], dspin_data_size = parameter.Reference('cmd_width')), 69 Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 70 Port('caba:dspin_input' , 'p_rsp_in' , [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 71 ], 73 dspin_in_width = parameter.Reference('dspin_rsp_width'), 74 dspin_out_width = parameter.Reference('dspin_cmd_width')), 75 76 Uses('common:elf_file_loader'), 77 ], 78 79 ports = [ 80 Port('caba:bit_in', 'p_resetn', auto = 'resetn'), 81 Port('caba:clock_in', 'p_clk', auto = 'clock'), 82 Port('caba:dspin_output', 'p_cmd_out', [2, 4], 83 dspin_data_size = parameter.Reference('dspin_cmd_width')), 84 Port('caba:dspin_input', 'p_cmd_in', [2, 4], 85 dspin_data_size = parameter.Reference('dspin_cmd_width')), 86 Port('caba:dspin_output', 'p_rsp_out', [2, 4], 87 dspin_data_size = parameter.Reference('dspin_rsp_width')), 88 Port('caba:dspin_input', 'p_rsp_in', [2, 4], 89 dspin_data_size = parameter.Reference('dspin_rsp_width')), 90 ], 72 91 ) 73 92 -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h
r389 r396 1 1 ////////////////////////////////////////////////////////////////////////////// 2 // File: tsar_xbar_cluster _mmu.h2 // File: tsar_xbar_cluster.h 3 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 // Date : march 201 15 // Date : march 2013 6 6 // This program is released under the GNU public license 7 7 ////////////////////////////////////////////////////////////////////////////// … … 34 34 #include "vci_cc_vcache_wrapper.h" 35 35 36 ///////////////////////////////////////////////////////////37 // VCI parameters for DIRECT network38 ///////////////////////////////////////////////////////////39 #define cell_width 440 #define address_width 3241 #define plen_width 842 #define error_width 243 #define clen_width 144 #define rflag_width 145 #define srcid_width 1446 #define pktid_width 447 #define trdid_width 448 #define wrplen_width 149 50 ///////////////////////////////////////////////////////////51 // VCI parameters for EXTERNAL network52 ///////////////////////////////////////////////////////////53 #define cell_width_ext 854 #define address_width_ext address_width55 #define plen_width_ext plen_width56 #define error_width_ext error_width57 #define clen_width_ext clen_width58 #define rflag_width_ext rflag_width59 #define srcid_width_ext srcid_width60 #define pktid_width_ext pktid_width61 #define trdid_width_ext trdid_width62 #define wrplen_width_ext wrplen_width63 64 36 namespace soclib { namespace caba { 65 37 66 38 /////////////////////////////////////////////////////////////////////////// 67 template< 68 typename iss_t, int cmd_width, int rsp_width69 >70 class TsarXbarCluster39 template<size_t dspin_cmd_width, 40 size_t dspin_rsp_width, 41 typename vci_param_int, 42 typename vci_param_ext> class TsarXbarCluster 71 43 /////////////////////////////////////////////////////////////////////////// 72 44 : public soclib::caba::BaseModule 73 45 { 74 // Define VCI parameters 75 typedef soclib::caba::VciParams<cell_width, 76 plen_width, 77 address_width, 78 error_width, 79 clen_width, 80 rflag_width, 81 srcid_width, 82 pktid_width, 83 trdid_width, 84 wrplen_width> vci_param_d; 85 86 typedef soclib::caba::VciParamsBis<cell_width_ext, 87 plen_width_ext, 88 address_width_ext, 89 error_width_ext, 90 clen_width_ext, 91 rflag_width_ext, 92 srcid_width_ext, 93 pktid_width_ext, 94 trdid_width_ext, 95 wrplen_width_ext> vci_param_x; 96 97 public: 98 99 // Ports 100 sc_in<bool> p_clk; 101 sc_in<bool> p_resetn; 102 soclib::caba::DspinOutput<cmd_width> **p_cmd_out; 103 soclib::caba::DspinInput<cmd_width> **p_cmd_in; 104 soclib::caba::DspinOutput<rsp_width> **p_rsp_out; 105 soclib::caba::DspinInput<rsp_width> **p_rsp_in; 46 public: 47 48 // Ports 49 sc_in<bool> p_clk; 50 sc_in<bool> p_resetn; 51 soclib::caba::DspinOutput<dspin_cmd_width> **p_cmd_out; 52 soclib::caba::DspinInput<dspin_cmd_width> **p_cmd_in; 53 soclib::caba::DspinOutput<dspin_rsp_width> **p_rsp_out; 54 soclib::caba::DspinInput<dspin_rsp_width> **p_rsp_in; 106 55 107 56 // interrupt signals 108 sc_signal<bool>signal_false;109 sc_signal<bool>signal_proc_it[8];110 sc_signal<bool>signal_irq_mdma[8];111 sc_signal<bool>signal_irq_mtty[23];112 sc_signal<bool> signal_irq_mnic_rx[8];// unused113 sc_signal<bool> signal_irq_mnic_tx[8];// unused114 sc_signal<bool>signal_irq_bdev;115 116 117 DspinSignals<cmd_width>signal_dspin_cmd_l2g_d;118 DspinSignals<cmd_width>signal_dspin_cmd_g2l_d;119 DspinSignals<cmd_width>signal_dspin_m2p_l2g_c;120 DspinSignals<cmd_width>signal_dspin_m2p_g2l_c;121 DspinSignals<rsp_width>signal_dspin_rsp_l2g_d;122 DspinSignals<rsp_width>signal_dspin_rsp_g2l_d;123 DspinSignals<rsp_width>signal_dspin_p2m_l2g_c;124 DspinSignals<rsp_width>signal_dspin_p2m_g2l_c;125 126 127 VciSignals<vci_param_d>signal_vci_ini_proc[8];128 VciSignals<vci_param_d>signal_vci_ini_mdma;129 VciSignals<vci_param_d>signal_vci_ini_bdev;130 131 VciSignals<vci_param_d>signal_vci_tgt_memc;132 VciSignals<vci_param_d>signal_vci_tgt_xicu;133 VciSignals<vci_param_d>signal_vci_tgt_mdma;134 VciSignals<vci_param_d>signal_vci_tgt_mtty;135 VciSignals<vci_param_d>signal_vci_tgt_bdev;136 VciSignals<vci_param_d>signal_vci_tgt_brom;137 VciSignals<vci_param_d>signal_vci_tgt_fbuf;138 VciSignals<vci_param_d>signal_vci_tgt_mnic;139 140 141 DspinSignals<cmd_width> signal_dspin_cmd_proc_i[8];142 DspinSignals<rsp_width> signal_dspin_rsp_proc_i[8];143 DspinSignals<cmd_width> signal_dspin_cmd_mdma_i;144 DspinSignals<rsp_width> signal_dspin_rsp_mdma_i;145 DspinSignals<cmd_width> signal_dspin_cmd_bdev_i;146 DspinSignals<rsp_width> signal_dspin_rsp_bdev_i;147 148 DspinSignals<cmd_width> signal_dspin_cmd_memc_t;149 DspinSignals<rsp_width> signal_dspin_rsp_memc_t;150 DspinSignals<cmd_width> signal_dspin_cmd_xicu_t;151 DspinSignals<rsp_width> signal_dspin_rsp_xicu_t;152 DspinSignals<cmd_width> signal_dspin_cmd_mdma_t;153 DspinSignals<rsp_width> signal_dspin_rsp_mdma_t;154 DspinSignals<cmd_width> signal_dspin_cmd_mtty_t;155 DspinSignals<rsp_width> signal_dspin_rsp_mtty_t;156 DspinSignals<cmd_width> signal_dspin_cmd_bdev_t;157 DspinSignals<rsp_width> signal_dspin_rsp_bdev_t;158 DspinSignals<cmd_width> signal_dspin_cmd_brom_t;159 DspinSignals<rsp_width> signal_dspin_rsp_brom_t;160 DspinSignals<cmd_width> signal_dspin_cmd_fbuf_t;161 DspinSignals<rsp_width> signal_dspin_rsp_fbuf_t;162 DspinSignals<cmd_width> signal_dspin_cmd_mnic_t;163 DspinSignals<rsp_width> signal_dspin_rsp_mnic_t;164 165 166 DspinSignals<cmd_width> signal_dspin_m2p_memc;167 DspinSignals<rsp_width> signal_dspin_p2m_memc;168 DspinSignals<cmd_width> signal_dspin_m2p_proc[8];169 DspinSignals<rsp_width> signal_dspin_p2m_proc[8];170 171 // external RAMVCI signal172 VciSignals<vci_param_x>signal_vci_xram;173 57 sc_signal<bool> signal_false; 58 sc_signal<bool> signal_proc_it[8]; 59 sc_signal<bool> signal_irq_mdma[8]; 60 sc_signal<bool> signal_irq_mtty[23]; 61 sc_signal<bool> signal_irq_mnic_rx[8]; // unused 62 sc_signal<bool> signal_irq_mnic_tx[8]; // unused 63 sc_signal<bool> signal_irq_bdev; 64 65 // DSPIN signals between DSPIN routers and local_crossbars 66 DspinSignals<dspin_cmd_width> signal_dspin_cmd_l2g_d; 67 DspinSignals<dspin_cmd_width> signal_dspin_cmd_g2l_d; 68 DspinSignals<dspin_cmd_width> signal_dspin_m2p_l2g_c; 69 DspinSignals<dspin_cmd_width> signal_dspin_m2p_g2l_c; 70 DspinSignals<dspin_rsp_width> signal_dspin_rsp_l2g_d; 71 DspinSignals<dspin_rsp_width> signal_dspin_rsp_g2l_d; 72 DspinSignals<dspin_rsp_width> signal_dspin_p2m_l2g_c; 73 DspinSignals<dspin_rsp_width> signal_dspin_p2m_g2l_c; 74 75 // Direct VCI signals to VCI/DSPIN wrappers 76 VciSignals<vci_param_int> signal_vci_ini_proc[8]; 77 VciSignals<vci_param_int> signal_vci_ini_mdma; 78 VciSignals<vci_param_int> signal_vci_ini_bdev; 79 80 VciSignals<vci_param_int> signal_vci_tgt_memc; 81 VciSignals<vci_param_int> signal_vci_tgt_xicu; 82 VciSignals<vci_param_int> signal_vci_tgt_mdma; 83 VciSignals<vci_param_int> signal_vci_tgt_mtty; 84 VciSignals<vci_param_int> signal_vci_tgt_bdev; 85 VciSignals<vci_param_int> signal_vci_tgt_brom; 86 VciSignals<vci_param_int> signal_vci_tgt_fbuf; 87 VciSignals<vci_param_int> signal_vci_tgt_mnic; 88 89 // Direct DSPIN signals to local crossbars 90 DspinSignals<dspin_cmd_width> signal_dspin_cmd_proc_i[8]; 91 DspinSignals<dspin_rsp_width> signal_dspin_rsp_proc_i[8]; 92 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mdma_i; 93 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mdma_i; 94 DspinSignals<dspin_cmd_width> signal_dspin_cmd_bdev_i; 95 DspinSignals<dspin_rsp_width> signal_dspin_rsp_bdev_i; 96 97 DspinSignals<dspin_cmd_width> signal_dspin_cmd_memc_t; 98 DspinSignals<dspin_rsp_width> signal_dspin_rsp_memc_t; 99 DspinSignals<dspin_cmd_width> signal_dspin_cmd_xicu_t; 100 DspinSignals<dspin_rsp_width> signal_dspin_rsp_xicu_t; 101 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mdma_t; 102 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mdma_t; 103 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mtty_t; 104 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mtty_t; 105 DspinSignals<dspin_cmd_width> signal_dspin_cmd_bdev_t; 106 DspinSignals<dspin_rsp_width> signal_dspin_rsp_bdev_t; 107 DspinSignals<dspin_cmd_width> signal_dspin_cmd_brom_t; 108 DspinSignals<dspin_rsp_width> signal_dspin_rsp_brom_t; 109 DspinSignals<dspin_cmd_width> signal_dspin_cmd_fbuf_t; 110 DspinSignals<dspin_rsp_width> signal_dspin_rsp_fbuf_t; 111 DspinSignals<dspin_cmd_width> signal_dspin_cmd_mnic_t; 112 DspinSignals<dspin_rsp_width> signal_dspin_rsp_mnic_t; 113 114 // Coherence DSPIN signals to local crossbar 115 DspinSignals<dspin_cmd_width> signal_dspin_m2p_memc; 116 DspinSignals<dspin_rsp_width> signal_dspin_p2m_memc; 117 DspinSignals<dspin_cmd_width> signal_dspin_m2p_proc[8]; 118 DspinSignals<dspin_rsp_width> signal_dspin_p2m_proc[8]; 119 120 // external RAM to MEMC VCI signal 121 VciSignals<vci_param_ext> signal_vci_xram; 122 174 123 // Components 175 124 176 VciCcVCacheWrapper<vci_param_d, cmd_width, rsp_width, iss_t>* proc[8]; 177 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_proc[4]; 178 179 VciMemCache<vci_param_d, vci_param_x, rsp_width, cmd_width> * memc; 180 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_memc; 181 182 VciXicu<vci_param_d>* xicu; 183 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_xicu; 184 185 VciMultiDma<vci_param_d>* mdma; 186 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_mdma; 187 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mdma; 188 189 VciSimpleRam<vci_param_x>* xram; 190 191 VciSimpleRam<vci_param_d>* brom; 192 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_brom; 193 194 VciMultiTty<vci_param_d>* mtty; 195 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mtty; 196 197 VciFrameBuffer<vci_param_d>* fbuf; 198 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_fbuf; 199 200 VciMultiNic<vci_param_d>* mnic; 201 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_mnic; 202 203 VciBlockDeviceTsar<vci_param_d>* bdev; 204 VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>* wi_bdev; 205 VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>* wt_bdev; 206 207 DspinLocalCrossbar<cmd_width>* xbar_cmd_d; 208 DspinLocalCrossbar<rsp_width>* xbar_rsp_d; 209 DspinLocalCrossbar<cmd_width>* xbar_m2p_c; 210 DspinLocalCrossbar<rsp_width>* xbar_p2m_c; 211 212 VirtualDspinRouter<cmd_width>* router_cmd; 213 VirtualDspinRouter<rsp_width>* router_rsp; 214 215 TsarXbarCluster( sc_module_name insname, 216 size_t nb_procs, // number of processors 217 size_t nb_ttys, // number of TTY terminals 218 size_t nb_dmas, // number of DMA channels 125 VciCcVCacheWrapper<vci_param_int, 126 dspin_cmd_width, 127 dspin_rsp_width, 128 GdbServer<Mips32ElIss> >* proc[8]; 129 130 VciDspinInitiatorWrapper<vci_param_int, 131 dspin_cmd_width, 132 dspin_rsp_width>* wi_proc[8]; 133 134 VciMemCache<vci_param_int, 135 vci_param_ext, 136 dspin_rsp_width, 137 dspin_cmd_width>* memc; 138 139 VciDspinTargetWrapper<vci_param_int, 140 dspin_cmd_width, 141 dspin_rsp_width>* wt_memc; 142 143 VciXicu<vci_param_int>* xicu; 144 145 VciDspinTargetWrapper<vci_param_int, 146 dspin_cmd_width, 147 dspin_rsp_width>* wt_xicu; 148 149 VciMultiDma<vci_param_int>* mdma; 150 151 VciDspinInitiatorWrapper<vci_param_int, 152 dspin_cmd_width, 153 dspin_rsp_width>* wi_mdma; 154 155 VciDspinTargetWrapper<vci_param_int, 156 dspin_cmd_width, 157 dspin_rsp_width>* wt_mdma; 158 159 VciSimpleRam<vci_param_ext>* xram; 160 161 VciSimpleRam<vci_param_int>* brom; 162 163 VciDspinTargetWrapper<vci_param_int, 164 dspin_cmd_width, 165 dspin_rsp_width>* wt_brom; 166 167 VciMultiTty<vci_param_int>* mtty; 168 169 VciDspinTargetWrapper<vci_param_int, 170 dspin_cmd_width, 171 dspin_rsp_width>* wt_mtty; 172 173 VciFrameBuffer<vci_param_int>* fbuf; 174 175 VciDspinTargetWrapper<vci_param_int, 176 dspin_cmd_width, 177 dspin_rsp_width>* wt_fbuf; 178 179 VciMultiNic<vci_param_int>* mnic; 180 181 VciDspinTargetWrapper<vci_param_int, 182 dspin_cmd_width, 183 dspin_rsp_width>* wt_mnic; 184 185 VciBlockDeviceTsar<vci_param_int>* bdev; 186 187 VciDspinInitiatorWrapper<vci_param_int, 188 dspin_cmd_width, 189 dspin_rsp_width>* wi_bdev; 190 191 VciDspinTargetWrapper<vci_param_int, 192 dspin_cmd_width, 193 dspin_rsp_width>* wt_bdev; 194 195 DspinLocalCrossbar<dspin_cmd_width>* xbar_cmd_d; 196 DspinLocalCrossbar<dspin_rsp_width>* xbar_rsp_d; 197 DspinLocalCrossbar<dspin_cmd_width>* xbar_m2p_c; 198 DspinLocalCrossbar<dspin_rsp_width>* xbar_p2m_c; 199 200 VirtualDspinRouter<dspin_cmd_width>* router_cmd; 201 VirtualDspinRouter<dspin_rsp_width>* router_rsp; 202 203 TsarXbarCluster( sc_module_name insname, 204 size_t nb_procs, // processors 205 size_t nb_ttys, // TTY terminals 206 size_t nb_dmas, // DMA channels 219 207 size_t x, // x coordinate 220 208 size_t y, // y coordinate 221 209 size_t cluster, // y + ymax*x 222 const soclib::common::MappingTable &mtd, // direct mapping table223 const soclib::common::MappingTable &mtx, // xram mapping table224 size_t x_width, // x field number ofbits225 size_t y_width, // y field number ofbits226 size_t l_width, // l field number ofbits227 size_t 228 size_t 210 const soclib::common::MappingTable &mtd, // internal 211 const soclib::common::MappingTable &mtx, // external 212 size_t x_width, // x field bits 213 size_t y_width, // y field bits 214 size_t l_width, // l field bits 215 size_t tgtid_memc, 216 size_t tgtid_xicu, 229 217 size_t tgtid_mdma, 230 218 size_t tgtid_fbuf, … … 239 227 size_t l1_d_ways, 240 228 size_t l1_d_sets, 241 size_t xram_latency, // external ram latency242 bool io, // I/O cluster if true243 size_t xfb, // f rame bufferpixels244 size_t yfb, // f rame bufferlines245 char* disk_name, // virtual disk for BDEV246 size_t block_size, // block size for BDEV247 size_t nic_channels, // number ofchannels248 char* nic_rx_name, // file name rx packets249 char* nic_tx_name, // file name tx packets250 uint32_t nic_timeout, // number ofcycles251 const Loader &loader, // loader for BROM 252 uint32_t frozen_cycles, // max frozen cycles229 size_t xram_latency, // external ram 230 bool io, // I/O cluster 231 size_t xfb, // fbf pixels 232 size_t yfb, // fbf lines 233 char* disk_name, // virtual disk 234 size_t block_size, // block size 235 size_t nic_channels, // number channels 236 char* nic_rx_name, // filename rx 237 char* nic_tx_name, // filename tx 238 uint32_t nic_timeout, // cycles 239 const Loader &loader, 240 uint32_t frozen_cycles, 253 241 uint32_t start_debug_cycle, 254 242 bool memc_debug_ok, 255 243 bool proc_debug_ok); 256 244 257 ~TsarXbarCluster();258 245 }; 259 246 }} -
trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp
r389 r396 15 15 // - Each processor has a private dma channel (vci_multi_dma) 16 16 // - It uses the vci_xicu interrupt controller 17 // - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in the cluster 18 // containing address 0xBFC00000. 17 // - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0) 19 18 // - The Multi-TTY component controls up to 15 terminals. 20 19 // - Each Multi-DMA component controls up to 8 DMA channels. … … 26 25 #include "../include/tsar_xbar_cluster.h" 27 26 28 #define tmpl(x) template<\29 typename iss_t,int cmd_width, int rsp_width> \30 x TsarXbarCluster<\31 iss_t, cmd_width, rsp_width\32 >33 27 34 28 namespace soclib { 35 29 namespace caba { 36 30 37 ////////////////////////////////////////////////////////////////////////// 38 // Constructor 39 ////////////////////////////////////////////////////////////////////////// 40 tmpl(/**/)::TsarXbarCluster( 31 //////////////////////////////////////////////////////////////////////////////////// 32 template<size_t dspin_cmd_width, 33 size_t dspin_rsp_width, 34 typename vci_param_int, 35 typename vci_param_ext> TsarXbarCluster<dspin_cmd_width, 36 dspin_rsp_width, 37 vci_param_int, 38 vci_param_ext>::TsarXbarCluster( 39 //////////////////////////////////////////////////////////////////////////////////// 41 40 sc_module_name insname, 42 41 size_t nb_procs, … … 86 85 { 87 86 // Vectors of ports definition 88 89 p_cmd_ in = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);90 p_ cmd_out = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);91 p_rsp_ in = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);92 p_rsp_out = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4); 93 87 p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 2, 4); 88 p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 2, 4); 89 p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> >("p_rsp_in", 2, 4); 90 p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> >("p_rsp_out", 2, 4); 91 92 ///////////////////////////////////////////////////////////////////////////// 94 93 // Components definition 95 96 // on direct network : local srcid[proc] in [0..nb_procs-1]97 // on direct network : local srcid[mdma] = nb_procs98 // on direct network : local srcid[bdev] = nb_procs + 199 100 // on coherence network : local srcid[proc] in [0...nb_procs-1]101 // on coherence network : local srcid[memc] = nb_procs102 103 94 ///////////////////////////////////////////////////////////////////////////// 104 95 std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; … … 107 98 { 108 99 std::ostringstream sproc; 109 sproc << "proc_" << p; 110 proc[p] = new VciCcVCacheWrapper<vci_param_d, cmd_width, rsp_width, iss_t>( 100 sproc << "proc_" << x_id << "_" << y_id << "_" << p; 101 proc[p] = new VciCcVCacheWrapper<vci_param_int, 102 dspin_cmd_width, 103 dspin_rsp_width, 104 GdbServer<Mips32ElIss> >( 111 105 sproc.str().c_str(), 112 106 cluster_id*nb_procs + p, // GLOBAL PROC_ID … … 130 124 std::ostringstream swip; 131 125 swip << "wi_proc_" << x_id << "_" << y_id << p; 132 wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>( 126 wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_int, 127 dspin_cmd_width, 128 dspin_rsp_width>( 133 129 swip.str().c_str(), 134 130 x_width + y_width + l_width); … … 138 134 std::cout << " - building memc_" << x_id << "_" << y_id << std::endl; 139 135 140 memc = new VciMemCache<vci_param_d, vci_param_x, rsp_width, cmd_width>( 141 "memc", 136 std::ostringstream smemc; 137 smemc << "memc_" << x_id << "_" << y_id; 138 memc = new VciMemCache<vci_param_int, 139 vci_param_ext, 140 dspin_rsp_width, 141 dspin_cmd_width>( 142 smemc.str().c_str(), 142 143 mtd, // Mapping Table direct space 143 144 mtx, // Mapping Table external space … … 153 154 memc_debug_ok ); 154 155 155 wt_memc = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>( 156 wt_memc = new VciDspinTargetWrapper<vci_param_int, 157 dspin_cmd_width, 158 dspin_rsp_width>( 156 159 "wt_memc", 157 160 x_width + y_width + l_width); … … 160 163 std::cout << " - building xram_" << x_id << "_" << y_id << std::endl; 161 164 162 xram = new VciSimpleRam<vci_param_x>( 163 "xram", 165 std::ostringstream sxram; 166 sxram << "xram_" << x_id << "_" << y_id; 167 xram = new VciSimpleRam<vci_param_ext>( 168 sxram.str().c_str(), 164 169 IntTab(cluster_id), 165 170 mtx, … … 170 175 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 171 176 172 xicu = new VciXicu<vci_param_d>( 173 "xicu", 177 std::ostringstream sxicu; 178 sxicu << "xicu_" << x_id << "_" << y_id; 179 xicu = new VciXicu<vci_param_int>( 180 sxicu.str().c_str(), 174 181 mtd, // mapping table 175 182 IntTab(cluster_id, tgtid_xicu), // TGTID_D … … 179 186 nb_procs); // number of output IRQs 180 187 181 wt_xicu = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>( 188 wt_xicu = new VciDspinTargetWrapper<vci_param_int, 189 dspin_cmd_width, 190 dspin_rsp_width>( 182 191 "wt_xicu", 183 192 x_width + y_width + l_width); … … 186 195 std::cout << " - building mdma_" << x_id << "_" << y_id << std::endl; 187 196 188 mdma = new VciMultiDma<vci_param_d>( 189 "mdma", 197 std::ostringstream smdma; 198 smdma << "mdma_" << x_id << "_" << y_id; 199 mdma = new VciMultiDma<vci_param_int>( 200 smdma.str().c_str(), 190 201 mtd, 191 202 IntTab(cluster_id, nb_procs), // SRCID … … 194 205 nb_dmas); // number of IRQs 195 206 196 wt_mdma = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>( 207 wt_mdma = new VciDspinTargetWrapper<vci_param_int, 208 dspin_cmd_width, 209 dspin_rsp_width>( 197 210 "wt_mdma", 198 211 x_width + y_width + l_width); 199 212 200 wi_mdma = new VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>( 213 wi_mdma = new VciDspinInitiatorWrapper<vci_param_int, 214 dspin_cmd_width, 215 dspin_rsp_width>( 201 216 "wi_mdma", 202 217 x_width + y_width + l_width); … … 213 228 } 214 229 215 xbar_cmd_d = new DspinLocalCrossbar< cmd_width>(230 xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>( 216 231 "xbar_cmd_d", 217 232 mtd, // mapping table … … 227 242 std::cout << " - building xbar_rsp_d_" << x_id << "_" << y_id << std::endl; 228 243 229 xbar_rsp_d = new DspinLocalCrossbar< rsp_width>(244 xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>( 230 245 "xbar_rsp_d", 231 246 mtd, // mapping table … … 241 256 std::cout << " - building xbar_m2p_c" << x_id << "_" << y_id << std::endl; 242 257 243 xbar_m2p_c = new DspinLocalCrossbar< cmd_width>(258 xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>( 244 259 "xbar_m2p_c", 245 260 mtd, // mapping table … … 255 270 std::cout << " - building xbar_p2m_c_" << x_id << "_" << y_id << std::endl; 256 271 257 xbar_p2m_c = new DspinLocalCrossbar< rsp_width>(272 xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>( 258 273 "xbar_p2m_c", 259 274 mtd, // mapping table … … 269 284 std::cout << " - building router_cmd_" << x_id << "_" << y_id << std::endl; 270 285 271 router_cmd = new VirtualDspinRouter< cmd_width>(286 router_cmd = new VirtualDspinRouter<dspin_cmd_width>( 272 287 "router_cmd", 273 288 x_id,y_id, // coordinate in the mesh … … 278 293 std::cout << " - building router_rsp_" << x_id << "_" << y_id << std::endl; 279 294 280 router_rsp = new VirtualDspinRouter< rsp_width>(295 router_rsp = new VirtualDspinRouter<dspin_rsp_width>( 281 296 "router_rsp", 282 297 x_id,y_id, // coordinates in mesh … … 290 305 std::cout << " - building brom" << std::endl; 291 306 292 brom = new VciSimpleRam<vci_param_d>( 293 "brom", 294 IntTab(cluster_id, tgtid_brom), 295 mtd, 296 loader); 297 298 wt_brom = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_brom", 307 brom = new VciSimpleRam<vci_param_int>( 308 "brom", 309 IntTab(cluster_id, tgtid_brom), 310 mtd, 311 loader); 312 313 wt_brom = new VciDspinTargetWrapper<vci_param_int, 314 dspin_cmd_width, 315 dspin_rsp_width>( 316 "wt_brom", 299 317 x_width + y_width + l_width); 300 318 … … 302 320 std::cout << " - building fbuf" << std::endl; 303 321 304 fbuf = new VciFrameBuffer<vci_param_d>( 305 "fbuf", 306 IntTab(cluster_id, tgtid_fbuf), 307 mtd, 308 xfb, yfb); 309 310 wt_fbuf = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_fbuf", 322 fbuf = new VciFrameBuffer<vci_param_int>( 323 "fbuf", 324 IntTab(cluster_id, tgtid_fbuf), 325 mtd, 326 xfb, yfb); 327 328 wt_fbuf = new VciDspinTargetWrapper<vci_param_int, 329 dspin_cmd_width, 330 dspin_rsp_width>( 331 "wt_fbuf", 311 332 x_width + y_width + l_width); 312 333 … … 314 335 std::cout << " - building bdev" << std::endl; 315 336 316 bdev = new VciBlockDeviceTsar<vci_param_d>( 317 "bdev", 318 mtd, 319 IntTab(cluster_id, nb_procs+1), 320 IntTab(cluster_id, tgtid_bdev), 321 disk_name, 322 block_size, 323 64); // burst size 324 325 wt_bdev = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_bdev", 326 x_width + y_width + l_width); 327 wi_bdev = new VciDspinInitiatorWrapper<vci_param_d,cmd_width,rsp_width>("wi_bdev", 337 bdev = new VciBlockDeviceTsar<vci_param_int>( 338 "bdev", 339 mtd, 340 IntTab(cluster_id, nb_procs+1), 341 IntTab(cluster_id, tgtid_bdev), 342 disk_name, 343 block_size, 344 64); // burst size 345 346 wt_bdev = new VciDspinTargetWrapper<vci_param_int, 347 dspin_cmd_width, 348 dspin_rsp_width>( 349 "wt_bdev", 350 x_width + y_width + l_width); 351 352 wi_bdev = new VciDspinInitiatorWrapper<vci_param_int, 353 dspin_cmd_width, 354 dspin_rsp_width>( 355 "wi_bdev", 328 356 x_width + y_width + l_width); 329 357 … … 331 359 std::cout << " - building mnic" << std::endl; 332 360 333 mnic = new VciMultiNic<vci_param_d>( 334 "mnic", 335 IntTab(cluster_id, tgtid_mnic), 336 mtd, 337 nic_channels, 338 nic_rx_name, 339 nic_tx_name, 340 0, // mac_4 address 341 0 ); // mac_2 address 342 343 wt_mnic = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_mnic", 361 mnic = new VciMultiNic<vci_param_int>( 362 "mnic", 363 IntTab(cluster_id, tgtid_mnic), 364 mtd, 365 nic_channels, 366 nic_rx_name, 367 nic_tx_name, 368 0, // mac_4 address 369 0 ); // mac_2 address 370 371 wt_mnic = new VciDspinTargetWrapper<vci_param_int, 372 dspin_cmd_width, 373 dspin_rsp_width>( 374 "wt_mnic", 344 375 x_width + y_width + l_width); 345 376 … … 354 385 vect_names.push_back(term_name.str().c_str()); 355 386 } 356 mtty = new VciMultiTty<vci_param_d>( 357 "mtty", 358 IntTab(cluster_id, tgtid_mtty), 359 mtd, 360 vect_names); 361 362 wt_mtty = new VciDspinTargetWrapper<vci_param_d,cmd_width,rsp_width>("wt_mtty", 363 x_width + y_width + l_width); 364 387 mtty = new VciMultiTty<vci_param_int>( 388 "mtty", 389 IntTab(cluster_id, tgtid_mtty), 390 mtd, 391 vect_names); 392 393 wt_mtty = new VciDspinTargetWrapper<vci_param_int, 394 dspin_cmd_width, 395 dspin_rsp_width>( 396 "wt_mtty", 397 x_width + y_width + l_width); 365 398 } 366 399 … … 679 712 } // end constructor 680 713 681 /////////////////////////////////////////////////////////////////////////// 682 // destructor 683 /////////////////////////////////////////////////////////////////////////// 684 tmpl(/**/)::~TsarXbarCluster() {} 685 } 686 } 687 714 }} 688 715 689 716 // Local Variables:
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