Changeset 400 for trunk/modules/vci_block_device_tsar/caba/source/include
- Timestamp:
- Jun 3, 2013, 10:25:33 AM (12 years ago)
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- 1 edited
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trunk/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h
r392 r400 30 30 ////////////////////////////////////////////////////////////////////////////////////// 31 31 // This component is a simplified disk controller with a VCI interface. 32 // It supports only 32 or 64 bits VCI DATA width, but all addressable registers 33 // contain 32 bits words. It supports VCI addresss lartger than 32 bits. 34 // 32 35 // This component can perform data transfers between one single file belonging 33 36 // to the host system and a buffer in the memory of the virtual prototype. … … 36 39 // The block size (bytes), and the burst size (bytes) must be power of 2. 37 40 // The burst size is typically a cache line. 38 // If the memory buffer is not constrained to be aligned on a burst boundary. 41 // The memory buffer is not constrained to be aligned on a burst boundary, 42 // but must be aligned on a 32 bits word boundary. 39 43 // Both read and write transfers are supported. An IRQ is optionally 40 44 // asserted when the transfer is completed. 41 45 // 42 // As a target this block device controler contains 9 memory mapped registers,46 // As a target this block device controler contains 9 32 bits memory mapped registers, 43 47 // taking 36 bytes in the address space. 44 // - BLOCK_DEVICE_BUFFER 0x00 (read/write) Memory buffer base address (32LSB bits)45 // - BLOCK_DEVICE_COUNT 0x04 (read/write) 46 // - BLOCK_DEVICE_LBA 0x08 (read/write) 47 // - BLOCK_DEVICE_OP 0x0C (write-only) 48 // - BLOCK_DEVICE_STATUS 0x10 (read-only) 49 // - BLOCK_DEVICE_IRQ_ENABLE 0x14 (read/write) 50 // - BLOCK_DEVICE_SIZE 0x18 (read-only) 51 // - BLOCK_DEVICE_BLOCK_SIZE 0x1C (read_only) 52 // - BLOCK_DEVICE_BUFFER_EXT 0x20 (read_only) Memory buffer base address (32MSB bits)48 // - BLOCK_DEVICE_BUFFER 0x00 (read/write) Memory buffer base address (LSB bits) 49 // - BLOCK_DEVICE_COUNT 0x04 (read/write) Number of blocks to be transfered. 50 // - BLOCK_DEVICE_LBA 0x08 (read/write) Index of first block in the file. 51 // - BLOCK_DEVICE_OP 0x0C (write-only) Writing here starts the operation. 52 // - BLOCK_DEVICE_STATUS 0x10 (read-only) Block Device status. 53 // - BLOCK_DEVICE_IRQ_ENABLE 0x14 (read/write) IRQ enabled if non zero. 54 // - BLOCK_DEVICE_SIZE 0x18 (read-only) Number of addressable blocks. 55 // - BLOCK_DEVICE_BLOCK_SIZE 0x1C (read_only) Block size in bytes. 56 // - BLOCK_DEVICE_BUFFER_EXT 0x20 (read_only) Memory buffer base address (MSB bits) 53 57 // 54 58 // The following operations codes are supported: … … 104 108 sc_signal<uint32_t> r_lba; // first block index 105 109 sc_signal<bool> r_read; // requested operation 106 sc_signal<uint32_t> r_index; // flitindex in local buffer110 sc_signal<uint32_t> r_index; // word index in local buffer 107 111 sc_signal<uint32_t> r_latency_count; // latency counter 108 sc_signal<uint32_t> r_ flit_count; // flitcounter (in a burst)112 sc_signal<uint32_t> r_words_count; // word counter (in a burst) 109 113 sc_signal<uint32_t> r_burst_count; // burst counter (in a block) 110 114 sc_signal<uint32_t> r_block_count; // block counter (in a transfer) 111 sc_signal<uint32_t> r_burst_offset; // number of non aligned flits112 sc_signal<uint32_t> r_burst_n flits; // number of flits in a burst115 sc_signal<uint32_t> r_burst_offset; // number of non aligned words 116 sc_signal<uint32_t> r_burst_nwords; // number of words in a burst 113 117 sc_signal<bool> r_go; // command from T_FSM to M_FSM 114 118 … … 124 128 int m_fd; // File descriptor 125 129 uint64_t m_device_size; // Total number of blocks 126 const uint32_t m_ flits_per_block; // number of flits in a block127 const uint32_t m_ flits_per_burst; // number of flits in a burst130 const uint32_t m_words_per_block; // number of words in a block 131 const uint32_t m_words_per_burst; // number of words in a burst 128 132 const uint32_t m_bursts_per_block; // number of bursts in a block 129 133 const uint32_t m_latency; // device latency
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