- Timestamp:
- Jul 12, 2013, 12:16:30 PM (11 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r431 r434 34 34 #include "../include/vci_mem_cache.h" 35 35 36 ////// debug services /////////////////////////////////////////////////////// 36 ////// debug services ///////////////////////////////////////////////////////////// 37 37 // All debug messages are conditionned by two variables: 38 38 // - compile time : DEBUG_MEMC_*** : defined below 39 // - execution time : m_debug_*** : defined by constructor arguments 40 // m_debug_* = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle) 41 ///////////////////////////////////////////////////////////////////////////////// 39 // - execution time : m_debug = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle) 40 /////////////////////////////////////////////////////////////////////////////////////// 42 41 43 42 #define DEBUG_MEMC_GLOBAL 0 // synthetic trace of all FSMs 43 #define DEBUG_MEMC_CONFIG 1 // detailed trace of CONFIG FSM 44 44 #define DEBUG_MEMC_READ 1 // detailed trace of READ FSM 45 45 #define DEBUG_MEMC_WRITE 1 // detailed trace of WRITE FSM … … 64 64 "TGT_CMD_READ", 65 65 "TGT_CMD_WRITE", 66 "TGT_CMD_CAS" 66 "TGT_CMD_CAS", 67 "TGT_CMD_CONFIG" 67 68 }; 68 69 const char *tgt_rsp_fsm_str[] = … … 118 119 "MULTI_ACK_UPT_LOCK", 119 120 "MULTI_ACK_UPT_CLEAR", 120 "MULTI_ACK_WRITE_RSP" 121 "MULTI_ACK_WRITE_RSP", 122 "MULTI_ACK_CONFIG_ACK" 121 123 }; 122 124 const char *read_fsm_str[] = … … 237 239 "CLEANUP_UPT_CLEAR", 238 240 "CLEANUP_WRITE_RSP", 239 "CLEANUP_SEND_ACK" 241 "CLEANUP_CONFIG_ACK", 242 "CLEANUP_SEND_CLACK" 240 243 }; 241 244 const char *alloc_dir_fsm_str[] = … … 457 460 for(seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++) 458 461 { 462 if ( seg->special() ) m_seg_config = i; 459 463 m_seg[i] = & (*seg); 460 464 i++; … … 631 635 // Initializing FSMs 632 636 r_tgt_cmd_fsm = TGT_CMD_IDLE; 637 r_config_fsm = CONFIG_IDLE; 633 638 r_tgt_rsp_fsm = TGT_RSP_TGT_CMD_IDLE; 634 639 r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; … … 647 652 r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; 648 653 649 m_debug_global = false; 650 m_debug_tgt_cmd_fsm = false; 651 m_debug_tgt_rsp_fsm = false; 652 m_debug_cc_send_fsm = false; 653 m_debug_cc_receive_fsm = false; 654 m_debug_multi_ack_fsm = false; 655 m_debug_read_fsm = false; 656 m_debug_write_fsm = false; 657 m_debug_cas_fsm = false; 658 m_debug_cleanup_fsm = false; 659 m_debug_ixr_cmd_fsm = false; 660 m_debug_ixr_rsp_fsm = false; 661 m_debug_xram_rsp_fsm = false; 654 m_debug = false; 662 655 m_debug_previous_hit = false; 663 656 m_debug_previous_count = 0; … … 690 683 m_cmd_cas_eop_fifo.init() ; 691 684 685 r_config_cmd = MEMC_CMD_NOP; 686 r_config_lock = false; 687 692 688 r_tgt_cmd_to_tgt_rsp_req = false; 693 689 … … 697 693 r_write_to_tgt_rsp_req = false; 698 694 r_write_to_ixr_cmd_req = false; 699 r_write_to_cc_send_multi_req = false;700 r_write_to_cc_send_brdcast_req = false;695 r_write_to_cc_send_multi_req = false; 696 r_write_to_cc_send_brdcast_req = false; 701 697 r_write_to_multi_ack_req = false; 702 698 … … 816 812 #endif 817 813 818 m_debug_global = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 819 m_debug_tgt_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 820 m_debug_tgt_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 821 m_debug_cc_send_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 822 m_debug_cc_receive_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 823 m_debug_multi_ack_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 824 m_debug_read_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 825 m_debug_write_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 826 m_debug_cas_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 827 m_debug_cleanup_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 828 m_debug_ixr_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 829 m_debug_ixr_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 830 m_debug_xram_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 814 m_debug = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; 831 815 832 816 #if DEBUG_MEMC_GLOBAL 833 if(m_debug_global)834 817 if(m_debug) 818 { 835 819 std::cout 836 820 << "---------------------------------------------" << std::dec << std::endl … … 853 837 << " - ALLOC_UPT FSM = " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()] << std::endl 854 838 << " - ALLOC_HEAP FSM = " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; 855 839 } 856 840 #endif 857 841 … … 859 843 // TGT_CMD FSM 860 844 //////////////////////////////////////////////////////////////////////////////////// 861 // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors 845 // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors, 846 // and dispatch these commands to the proper FSM through dedicated FIFOs. 862 847 // 863 // There are 5 types of accepted commands : 864 // - READ : A READ request has a length of 1 VCI cell. It can be a single word 865 // or an entire cache line, depending on the PLEN value. 866 // - WRITE : A WRITE request has a maximum length of 16 cells, and can only 867 // concern words in a same line. 868 // - CAS : A CAS request has a length of 2 cells or 4 cells. 869 // - LL : An LL request has a length of 1 cell. 870 // - SC : An SC request has a length of 2 cells. First cell contains the 871 // acces key, second cell the data to write in case of success. 848 // There are 5 types of commands accepted in the XRAM segment: 849 // - READ : A READ request has a length of 1 VCI flit. It can be a single word 850 // or an entire cache line, depending on the PLEN value => READ FSM 851 // - WRITE : A WRITE request has a maximum length of 16 flits, and can only 852 // concern words in a same line => WRITE FSM 853 // - CAS : A CAS request has a length of 2 flits or 4 flits => CAS FSM 854 // - LL : An LL request has a length of 1 flit => READ FSM 855 // - SC : An SC request has a length of 2 flits. First flit contains the 856 // acces key, second flit the data to write => WRITE FSM. 857 // 858 // The READ/WRITE commands accepted in the configuration segment are targeting, 859 // configuration or status registers. They must contain one single flit. 860 // - For almost all addressable registers, the response is returned immediately. 861 // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed. 872 862 //////////////////////////////////////////////////////////////////////////////////// 873 863 874 864 switch(r_tgt_cmd_fsm.read()) 875 865 { 876 877 case TGT_CMD_IDLE: 878 879 866 ////////////////// 867 case TGT_CMD_IDLE: // waiting a VCI command (RAM or CONFIG) 868 if(p_vci_tgt.cmdval) 869 { 880 870 881 871 #if DEBUG_MEMC_TGT_CMD 882 if(m_debug_tgt_cmd_fsm) 883 { 884 std::cout 885 << " <MEMC " << name() 886 << " TGT_CMD_IDLE> Receive command from srcid " 887 << std::dec << p_vci_tgt.srcid.read() 888 << " / for address " 889 << std::hex << p_vci_tgt.address.read() 890 << std::endl; 891 } 872 if(m_debug) 873 std::cout << " <MEMC " << name() 874 << " TGT_CMD_IDLE> Receive command from srcid " 875 << std::dec << p_vci_tgt.srcid.read() 876 << " / address " << std::hex << p_vci_tgt.address.read() << std::endl; 892 877 #endif 893 878 // checking segmentation violation 894 addr_t address = p_vci_tgt.address.read(); 895 uint32_t plen = p_vci_tgt.plen.read(); 896 bool found = false; 897 for(size_t seg_id = 0 ; seg_id < m_nseg ; seg_id++) 898 { 899 if(m_seg[seg_id]->contains(address) && 900 m_seg[seg_id]->contains(address + plen - vci_param_int::B)) 901 { 902 found = true; 903 } 904 } 905 906 if(not found) 907 { 908 r_tgt_cmd_fsm = TGT_CMD_ERROR; 909 } 910 else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) 911 { 912 // check that the pktid is either : 913 // TYPE_READ_DATA_UNC 914 // TYPE_READ_DATA_MISS 915 // TYPE_READ_INS_UNC 916 // TYPE_READ_INS_MISS 917 // ==> bit2 must be zero with the TSAR encoding 918 // ==> mask = 0b0100 = 0x4 919 assert(((p_vci_tgt.pktid.read() & 0x4) == 0x0) && 920 "The type specified in the pktid field is incompatible with the READ CMD"); 921 r_tgt_cmd_fsm = TGT_CMD_READ; 922 } 923 else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) 924 { 925 // check that the pktid is TYPE_WRITE 926 // ==> TYPE_WRITE = X100 with the TSAR encoding 927 // ==> mask = 0b0111 = 0x7 928 assert(((p_vci_tgt.pktid.read() & 0x7) == 0x4) && 929 "The type specified in the pktid field is incompatible with the WRITE CMD"); 930 r_tgt_cmd_fsm = TGT_CMD_WRITE; 931 } 932 else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) 933 { 934 // check that the pktid is TYPE_LL 935 // ==> TYPE_LL = X110 with the TSAR encoding 936 // ==> mask = 0b0111 = 0x7 937 assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) && 938 "The type specified in the pktid field is incompatible with the LL CMD"); 939 r_tgt_cmd_fsm = TGT_CMD_READ; 940 } 941 else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) 942 { 943 // check that the pktid is either : 944 // TYPE_CAS 945 // TYPE_SC 946 // ==> TYPE_CAS = X101 with the TSAR encoding 947 // ==> TYPE_SC = X111 with the TSAR encoding 948 // ==> mask = 0b0101 = 0x5 949 assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5) && 950 "The type specified in the pktid field is incompatible with the NOP CMD"); 951 952 if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) 953 r_tgt_cmd_fsm = TGT_CMD_CAS; 954 else // TYPE_SC 955 r_tgt_cmd_fsm = TGT_CMD_WRITE; 956 } 957 else 958 { 959 std::cout << "VCI_MEM_CACHE ERROR " << name() 960 << " TGT_CMD_IDLE state" << std::endl; 961 std::cout << " illegal VCI command type" << std::endl; 962 exit(0); 963 } 964 } 965 break; 966 967 case TGT_CMD_ERROR: 968 // A segmentation violation has been detected, thus a response with error 969 // must be sent 970 971 // wait if pending TGT_CMD request to TGT_RSP FSM 972 if(r_tgt_cmd_to_tgt_rsp_req.read()) break; 973 974 // consume all the command packet flits and set new request to the 975 // TGT_RSP FSM 976 if(p_vci_tgt.cmdval and p_vci_tgt.eop) 977 { 978 r_tgt_cmd_to_tgt_rsp_req = true; 879 addr_t address = p_vci_tgt.address.read(); 880 uint32_t plen = p_vci_tgt.plen.read(); 881 bool found = false; 882 bool config = false; 883 884 // register arguments for response (segmentation violation or config) 979 885 r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); 980 886 r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read(); 981 887 r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read(); 982 888 983 r_tgt_cmd_fsm = TGT_CMD_IDLE; 889 for(size_t seg_id = 0 ; (seg_id < m_nseg) and not found ; seg_id++) 890 { 891 if( m_seg[seg_id]->contains(address) and 892 m_seg[seg_id]->contains(address + plen - vci_param_int::B) ) 893 { 894 found = true; 895 if ( m_seg[seg_id]->special() ) config = true; 896 } 897 } 898 899 if ( not found ) /////////// out of segment error 900 { 901 r_tgt_cmd_fsm = TGT_CMD_ERROR; 902 } 903 else if ( config ) /////////// configuration command 904 { 905 if ( not p_vci_tgt.eop.read() ) r_tgt_cmd_fsm = TGT_CMD_ERROR; 906 else r_tgt_cmd_fsm = TGT_CMD_CONFIG; 907 } 908 else //////////// memory access 909 { 910 if ( p_vci_tgt.cmd.read() == vci_param_int::CMD_READ ) 911 { 912 // check that the pktid is either : 913 // TYPE_READ_DATA_UNC 914 // TYPE_READ_DATA_MISS 915 // TYPE_READ_INS_UNC 916 // TYPE_READ_INS_MISS 917 // ==> bit2 must be zero with the TSAR encoding 918 // ==> mask = 0b0100 = 0x4 919 assert( ((p_vci_tgt.pktid.read() & 0x4) == 0x0) and 920 "The type specified in the pktid field is incompatible with the READ CMD"); 921 r_tgt_cmd_fsm = TGT_CMD_READ; 922 } 923 else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) 924 { 925 // check that the pktid is TYPE_WRITE 926 // ==> TYPE_WRITE = X100 with the TSAR encoding 927 // ==> mask = 0b0111 = 0x7 928 assert(((p_vci_tgt.pktid.read() & 0x7) == 0x4) and 929 "The type specified in the pktid field is incompatible with the WRITE CMD"); 930 r_tgt_cmd_fsm = TGT_CMD_WRITE; 931 } 932 else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) 933 { 934 // check that the pktid is TYPE_LL 935 // ==> TYPE_LL = X110 with the TSAR encoding 936 // ==> mask = 0b0111 = 0x7 937 assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) and 938 "The type specified in the pktid field is incompatible with the LL CMD"); 939 r_tgt_cmd_fsm = TGT_CMD_READ; 940 } 941 else if(p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) 942 { 943 // check that the pktid is either : 944 // TYPE_CAS 945 // TYPE_SC 946 // ==> TYPE_CAS = X101 with the TSAR encoding 947 // ==> TYPE_SC = X111 with the TSAR encoding 948 // ==> mask = 0b0101 = 0x5 949 assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5) and 950 "The type specified in the pktid field is incompatible with the NOP CMD"); 951 952 if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS; 953 else r_tgt_cmd_fsm = TGT_CMD_WRITE; 954 } 955 else 956 { 957 r_tgt_cmd_fsm = TGT_CMD_ERROR; 958 } 959 } 960 } 961 break; 962 963 /////////////////// 964 case TGT_CMD_ERROR: // response error must be sent 965 966 // wait if pending TGT_CMD request to TGT_RSP FSM 967 if(r_tgt_cmd_to_tgt_rsp_req.read()) break; 968 969 // consume all the command packet flits before sending response error 970 if ( p_vci_tgt.cmdval and p_vci_tgt.eop ) 971 { 972 r_tgt_cmd_to_tgt_rsp_req = true; 973 r_tgt_cmd_to_tgt_rsp_error = 1; 974 r_tgt_cmd_fsm = TGT_CMD_IDLE; 984 975 985 976 #if DEBUG_MEMC_TGT_CMD 986 if(m_debug _tgt_cmd_fsm)977 if(m_debug) 987 978 std::cout << " <MEMC " << name() 988 979 << " TGT_CMD_ERROR> Segmentation violation:" … … 993 984 << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 994 985 #endif 995 } 996 997 break; 998 999 ////////////////// 1000 case TGT_CMD_READ: 1001 // This test checks that the read does not cross a cache line limit. 1002 // It must not be taken into account when dealing with an LL CMD. 1003 if(((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) && 986 987 } 988 break; 989 990 //////////////////// 991 case TGT_CMD_CONFIG: // execute config request and return response 992 { 993 if ( r_tgt_cmd_to_tgt_rsp_req.read() ) break; 994 995 addr_t seg_base = m_seg[m_seg_config]->baseAddress(); 996 addr_t address = p_vci_tgt.address.read(); 997 size_t cell = (address - seg_base)/vci_param_int::B; 998 bool need_rsp = true; // default value 999 size_t error = 0; // default value 1000 uint32_t rdata = 0; // default value 1001 1002 if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock 1003 and (cell == MEMC_LOCK) ) 1004 { 1005 rdata = (uint32_t)r_config_lock.read(); 1006 r_config_lock = true; 1007 } 1008 else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock 1009 and (cell == MEMC_LOCK) ) 1010 { 1011 r_config_lock = false; 1012 } 1013 else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type 1014 and (cell == MEMC_CMD_TYPE) ) 1015 { 1016 r_config_cmd = p_vci_tgt.wdata.read(); 1017 need_rsp = false; 1018 } 1019 else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo 1020 and (cell == MEMC_ADDR_LO) ) 1021 { 1022 r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) | 1023 (addr_t)p_vci_tgt.wdata.read(); 1024 } 1025 else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi 1026 and (cell == MEMC_ADDR_HI) ) 1027 { 1028 r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | 1029 ((addr_t)p_vci_tgt.wdata.read())<<32; 1030 } 1031 else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines 1032 and (cell == MEMC_BUF_LENGTH) ) 1033 { 1034 size_t lines = (size_t)(p_vci_tgt.wdata.read()/(m_words*vci_param_int::B)); 1035 if ( r_config_address.read()/(m_words*vci_param_int::B) ) lines++; 1036 r_config_nlines = lines; 1037 } 1038 else 1039 { 1040 error = 1; 1041 } 1042 1043 if ( need_rsp ) 1044 { 1045 // blocked if previous pending request to TGT_RSP FSM 1046 if ( r_tgt_cmd_to_tgt_rsp_req.read() ) break; 1047 1048 r_tgt_cmd_to_tgt_rsp_req = true; 1049 r_tgt_cmd_to_tgt_rsp_error = error; 1050 r_tgt_cmd_to_tgt_rsp_rdata = rdata; 1051 r_tgt_cmd_fsm = TGT_CMD_IDLE; 1052 } 1053 else 1054 { 1055 r_tgt_cmd_fsm = TGT_CMD_IDLE; 1056 } 1057 1058 #if DEBUG_MEMC_TGT_CMD 1059 if(m_debug) 1060 std::cout << " <MEMC " << name() << " TGT_CMD_CONFIG> Configuration request:" 1061 << " address = " << std::hex << p_vci_tgt.address.read() 1062 << " / wdata = " << p_vci_tgt.wdata.read() 1063 << " / error = " << error << std::endl; 1064 #endif 1065 break; 1066 } 1067 ////////////////// 1068 case TGT_CMD_READ: // Push a read request into read fifo 1069 1070 // check that the read does not cross a cache line limit. 1071 if ( ((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) and 1004 1072 (p_vci_tgt.cmd.read() != vci_param_int::CMD_LOCKED_READ)) 1005 { 1006 std::cout 1007 << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" 1008 << std::endl; 1009 std::cout 1010 << " illegal address/plen combination for VCI read command" << std::endl; 1073 { 1074 std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" 1075 << " illegal address/plen for VCI read command" << std::endl; 1011 1076 exit(0); 1012 } 1013 if(!p_vci_tgt.eop.read()) 1014 { 1015 std::cout 1016 << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" 1017 << std::endl; 1018 std::cout 1019 << " read or ll command packets must contain one single flit" 1020 << std::endl; 1077 } 1078 // check single flit 1079 if(!p_vci_tgt.eop.read()) 1080 { 1081 std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" 1082 << " read command packet must contain one single flit" << std::endl; 1021 1083 exit(0); 1022 } 1023 if((p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) && (p_vci_tgt.plen.read() != 8)) 1024 { 1025 std::cout 1026 << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" 1027 << std::endl; 1028 std::cout 1029 << " ll command packets must have a plen of 8" 1030 << std::endl; 1084 } 1085 // check plen for LL 1086 if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and 1087 (p_vci_tgt.plen.read() != 8) ) 1088 { 1089 std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" 1090 << " ll command packets must have a plen of 8" << std::endl; 1031 1091 exit(0); 1032 1033 1034 if(p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok())1035 1092 } 1093 1094 if ( p_vci_tgt.cmdval and m_cmd_read_addr_fifo.wok() ) 1095 { 1036 1096 1037 1097 #if DEBUG_MEMC_TGT_CMD 1038 if(m_debug _tgt_cmd_fsm)1098 if(m_debug) 1039 1099 std::cout << " <MEMC " << name() << " TGT_CMD_READ> Push into read_fifo:" 1040 1100 << " address = " << std::hex << p_vci_tgt.address.read() … … 1045 1105 #endif 1046 1106 cmd_read_fifo_put = true; 1047 if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) 1048 m_cpt_ll++; 1049 else 1050 m_cpt_read++; 1107 if(p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) m_cpt_ll++; 1108 else m_cpt_read++; 1051 1109 r_tgt_cmd_fsm = TGT_CMD_IDLE; 1052 1053 1054 1055 1110 } 1111 break; 1112 1113 /////////////////// 1056 1114 case TGT_CMD_WRITE: 1057 if(p_vci_tgt.cmdval &&m_cmd_write_addr_fifo.wok())1058 1115 if(p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok()) 1116 { 1059 1117 1060 1118 #if DEBUG_MEMC_TGT_CMD 1061 if(m_debug _tgt_cmd_fsm)1119 if(m_debug) 1062 1120 std::cout << " <MEMC " << name() << " TGT_CMD_WRITE> Push into write_fifo:" 1063 1121 << " address = " << std::hex << p_vci_tgt.address.read() … … 1071 1129 cmd_write_fifo_put = true; 1072 1130 if(p_vci_tgt.eop) r_tgt_cmd_fsm = TGT_CMD_IDLE; 1073 1074 1075 1076 ////////////////////1131 } 1132 break; 1133 1134 ///////////////// 1077 1135 case TGT_CMD_CAS: 1078 if((p_vci_tgt.plen.read() != 8) && (p_vci_tgt.plen.read() != 16)) 1079 { 1080 std::cout 1081 << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state" 1082 << std::endl 1083 << "illegal format for CAS command " << std::endl; 1084 1136 if((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16)) 1137 { 1138 std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state" 1139 << "illegal format for CAS command " << std::endl; 1085 1140 exit(0); 1086 1087 1088 if(p_vci_tgt.cmdval &&m_cmd_cas_addr_fifo.wok())1089 1141 } 1142 1143 if(p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok()) 1144 { 1090 1145 1091 1146 #if DEBUG_MEMC_TGT_CMD 1092 if(m_debug _tgt_cmd_fsm)1147 if(m_debug) 1093 1148 std::cout << " <MEMC " << name() << " TGT_CMD_CAS> Pushing command into cmd_cas_fifo:" 1094 1149 << " address = " << std::hex << p_vci_tgt.address.read() … … 1102 1157 cmd_cas_fifo_put = true; 1103 1158 if(p_vci_tgt.eop) r_tgt_cmd_fsm = TGT_CMD_IDLE; 1104 1105 1159 } 1160 break; 1106 1161 } // end switch tgt_cmd_fsm 1107 1162 … … 1115 1170 // It can be update or inval requests initiated by the WRITE or CAS FSM, 1116 1171 // or inval requests initiated by the XRAM_RSP FSM. 1117 // It can also be a direct request from the WRITE FSM.1118 1172 // 1119 1173 // The FSM decrements the proper entry in UPT. … … 1129 1183 switch(r_multi_ack_fsm.read()) 1130 1184 { 1131 /////////////////// 1185 //////////////////// 1132 1186 case MULTI_ACK_IDLE: 1133 1187 { 1134 1188 bool multi_ack_fifo_rok = m_cc_receive_to_multi_ack_fifo.rok(); 1135 1189 … … 1165 1219 1166 1220 #if DEBUG_MEMC_MULTI_ACK 1167 if(m_debug_multi_ack_fsm) 1168 { 1169 if (multi_ack_fifo_rok) 1170 { 1171 std::cout 1172 << " <MEMC " << name() 1173 << " MULTI_ACK_IDLE> Response for UPT entry " 1174 << updt_index 1175 << std::endl; 1176 } 1177 else 1178 { 1179 std::cout 1180 << " <MEMC " << name() 1181 << " MULTI_ACK_IDLE> Write FSM request to decrement UPT entry " 1182 << updt_index 1183 << std::endl; 1184 } 1185 } 1221 if(m_debug) 1222 { 1223 if (multi_ack_fifo_rok) 1224 { 1225 std::cout << " <MEMC " << name() 1226 << " MULTI_ACK_IDLE> Response for UPT entry " 1227 << updt_index << std::endl; 1228 } 1229 else 1230 { 1231 std::cout << " <MEMC " << name() 1232 << " MULTI_ACK_IDLE> Write FSM request to decrement UPT entry " 1233 << updt_index << std::endl; 1234 } 1235 } 1186 1236 #endif 1187 1237 break; … … 1190 1240 //////////////////////// 1191 1241 case MULTI_ACK_UPT_LOCK: 1192 1242 { 1193 1243 // get lock to the UPDATE table 1194 1244 if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break; … … 1200 1250 if(not valid) 1201 1251 { 1202 std::cout 1203 << "VCI_MEM_CACHE ERROR " << name() 1204 << " MULTI_ACK_UPT_LOCK state" << std::endl 1205 << "unsuccessful access to decrement the UPT" 1206 << std::endl; 1207 1208 exit(0); 1252 std::cout << "VCI_MEM_CACHE ERROR " << name() 1253 << " MULTI_ACK_UPT_LOCK state" << std::endl 1254 << "unsuccessful access to decrement the UPT" << std::endl; 1255 exit(0); 1209 1256 } 1210 1257 … … 1219 1266 1220 1267 #if DEBUG_MEMC_MULTI_ACK 1221 if(m_debug_multi_ack_fsm) 1222 { 1223 std::cout 1224 << " <MEMC " << name() 1225 << " MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT:" 1226 << " entry = " << r_multi_ack_upt_index.read() 1227 << " / rsp_count = " << std::dec << count 1228 << std::endl; 1229 } 1268 if(m_debug) 1269 std::cout << " <MEMC " << name() 1270 << " MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT:" 1271 << " entry = " << r_multi_ack_upt_index.read() 1272 << " / rsp_count = " << std::dec << count << std::endl; 1230 1273 #endif 1231 1274 break; 1232 1275 } 1233 1276 1234 1277 ///////////////////////// 1235 case MULTI_ACK_UPT_CLEAR: 1236 1278 case MULTI_ACK_UPT_CLEAR: // Clear UPT entry / Test if rsp or ack required 1279 { 1237 1280 if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) 1238 1281 { 1239 std::cout 1240 << "VCI_MEM_CACHE ERROR " << name() 1241 << " MULTI_ACK_UPT_CLEAR state" 1242 << " bad UPT allocation" 1243 << std::endl; 1244 1245 exit(0); 1282 std::cout << "VCI_MEM_CACHE ERROR " << name() 1283 << " MULTI_ACK_UPT_CLEAR state" 1284 << " bad UPT allocation" << std::endl; 1285 exit(0); 1246 1286 } 1247 1287 … … 1251 1291 r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read()); 1252 1292 bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read()); 1293 bool need_ack = m_upt.need_ack(r_multi_ack_upt_index.read()); 1253 1294 1254 1295 // clear the UPT entry 1255 1296 m_upt.clear(r_multi_ack_upt_index.read()); 1256 1297 1257 if(need_rsp) 1258 { 1259 r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; 1260 } 1261 else 1262 { 1263 r_multi_ack_fsm = MULTI_ACK_IDLE; 1264 } 1298 if ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; 1299 else if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK; 1300 else r_multi_ack_fsm = MULTI_ACK_IDLE; 1265 1301 1266 1302 #if DEBUG_MEMC_MULTI_ACK 1267 if(m_debug_multi_ack_fsm) 1268 { 1269 std::cout 1270 << " <MEMC " << name() 1271 << " MULTI_ACK_UPT_CLEAR> Clear UPT entry " 1272 << r_multi_ack_upt_index.read() 1273 << std::endl; 1274 } 1303 if(m_debug) 1304 std::cout << " <MEMC " << name() 1305 << " MULTI_ACK_UPT_CLEAR> Clear UPT entry " 1306 << std::dec << r_multi_ack_upt_index.read() << std::endl; 1275 1307 #endif 1276 1308 break; 1277 } 1278 1309 } 1279 1310 ///////////////////////// 1280 case MULTI_ACK_WRITE_RSP: 1281 { 1282 // Post a request to TGT_RSP FSM 1283 // Wait if pending request to the TGT_RSP FSM 1284 if(r_multi_ack_to_tgt_rsp_req.read()) break; 1311 case MULTI_ACK_WRITE_RSP: // Post a response request to TGT_RSP FSM 1312 // Wait if pending request 1313 { 1314 if ( r_multi_ack_to_tgt_rsp_req.read() ) break; 1285 1315 1286 1316 r_multi_ack_to_tgt_rsp_req = true; … … 1291 1321 1292 1322 #if DEBUG_MEMC_MULTI_ACK 1293 if(m_debug_multi_ack_fsm) 1294 { 1295 std::cout 1296 << " <MEMC " << name() 1297 << " MULTI_ACK_WRITE_RSP> Request TGT_RSP FSM to send a response to srcid " 1298 << r_multi_ack_srcid.read() 1299 << std::endl; 1300 } 1323 if(m_debug) 1324 std::cout << " <MEMC " << name() << " MULTI_ACK_WRITE_RSP>" 1325 << " Request TGT_RSP FSM to send a response to srcid " 1326 << std::hex << r_multi_ack_srcid.read() << std::endl; 1301 1327 #endif 1302 1328 break; 1303 } 1329 } 1330 ////////////////////////// 1331 case MULTI_ACK_CONFIG_ACK: // Signals multi-inval completion to CONFIG FSM 1332 // Wait if pending request 1333 { 1334 if ( r_multi_ack_to_config_ack.read() ) break; 1335 1336 r_multi_ack_to_config_ack = true; 1337 r_multi_ack_fsm = MULTI_ACK_IDLE; 1338 1339 #if DEBUG_MEMC_MULTI_ACK 1340 if(m_debug) 1341 std::cout << " <MEMC " << name() << " MULTI_ACK_CONFIG_ACK>" 1342 << " Signals inval completion to CONFIG FSM" << std::endl; 1343 #endif 1344 break; 1345 } 1304 1346 } // end switch r_multi_ack_fsm 1347 1348 //////////////////////////////////////////////////////////////////////////////////// 1349 // CONFIG FSM 1350 //////////////////////////////////////////////////////////////////////////////////// 1351 // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC). 1352 // The target buffer can have any size, and there is one single command for 1353 // all cache lines covered by the target buffer. 1354 // An INVAL or SYNC configuration request is defined by the followinf registers: 1355 // - bool r_config_cmd : INVAL / SYNC / NOP) 1356 // - uint64_t r_config_address : buffer base address 1357 // - uint32_t r_config_nlines : number of lines covering buffer 1358 // 1359 // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling 1360 // all cache lines covered by the target buffer. 1361 // 1362 // - INVAL request: 1363 // For each line, it access to the DIR array. 1364 // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 1365 // In case of hit, with no copies in L1 caches, the line is invalidated and 1366 // a response is requested to TGT_RSP FSM. 1367 // If there is copies, a multi-inval, or a broadcast-inval coherence transaction 1368 // is launched and registered in UPT. The multi-inval transaction is signaled 1369 // by the r_multi_ack_to config_ack or r_cleanup_to_config_ack flip-flops. 1370 // The config inval response is sent only when the last line has been invalidated. 1371 // 1372 // - SYNC request: Not implemented yet 1373 // 1374 // From the software point of view, a configuration request is a sequence 1375 // of 6 atomic accesses: 1376 // - Read MEMC_LOCK : Get the lock 1377 // - Write MEMC_ADDR_LO : Set the buffer address LSB 1378 // - Write MEMC_ADDR_HI : Set the buffer address MSB 1379 // - Write MEMC_BUF_LENGTH : set buffer length (bytes) 1380 // - Write MEMC_CMD_TYPE : launch the actual operation 1381 // - WRITE MEMC_LOCK : release the lock 1382 //////////////////////////////////////////////////////////////////////////////////// 1383 1384 switch( r_config_fsm.read() ) 1385 { 1386 ///////////////// 1387 case CONFIG_IDLE: // waiting a config request 1388 { 1389 if ( r_config_cmd.read() != MEMC_CMD_NOP ) 1390 { 1391 r_config_fsm = CONFIG_LOOP; 1392 } 1393 1394 #if DEBUG_MEMC_CONFIG 1395 if(m_debug) 1396 std::cout << " <MEMC " << name() << " CONFIG_IDLE> Config Request received" 1397 << " address = " << std::hex << r_config_address.read() 1398 << " / nlines = " << std::dec << r_config_nlines.read() 1399 << " / type = " << r_config_cmd.read() << std::endl; 1400 #endif 1401 break; 1402 } 1403 ///////////////// 1404 case CONFIG_LOOP: // test last line 1405 { 1406 if ( r_config_nlines.read() == 0 ) 1407 { 1408 r_config_cmd = MEMC_CMD_NOP; 1409 r_config_fsm = CONFIG_RSP; 1410 } 1411 else 1412 { 1413 r_config_fsm = CONFIG_DIR_REQ; 1414 } 1415 1416 #if DEBUG_MEMC_CONFIG 1417 if(m_debug) 1418 std::cout << " <MEMC " << name() << " CONFIG_SYNC_LOOP>" 1419 << " address = " << std::hex << r_config_address.read() 1420 << " / nlines = " << std::dec << r_config_nlines.read() 1421 << " / type = " << r_config_cmd.read() << std::endl; 1422 #endif 1423 break; 1424 } 1425 //////////////////// 1426 case CONFIG_DIR_REQ: // Request directory lock 1427 { 1428 if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG ) 1429 { 1430 r_config_fsm = CONFIG_DIR_ACCESS; 1431 } 1432 1433 #if DEBUG_MEMC_CONFIG 1434 if(m_debug) 1435 std::cout << " <MEMC " << name() << " CONFIG_INVAL_DIR_REQ>" 1436 << " Request DIR access" << std::endl; 1437 #endif 1438 break; 1439 } 1440 /////////////////////// 1441 case CONFIG_DIR_ACCESS: // Access directory and decode cmd 1442 { 1443 size_t way = 0; 1444 DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way); 1445 1446 if ( entry.valid and // hit & inval command 1447 (r_config_cmd.read() == MEMC_CMD_INVAL) ) 1448 { 1449 r_config_way = way; 1450 r_config_is_cnt = entry.is_cnt; 1451 r_config_count = entry.count; 1452 r_config_fsm = CONFIG_DIR_INVAL; 1453 } 1454 else if ( entry.valid and // hit & sync command 1455 entry.dirty and 1456 (r_config_cmd.read() == MEMC_CMD_SYNC) ) 1457 { 1458 std::cout << "VCI_MEM_CACHE ERROR: " 1459 << "SYNC config request not implemented yet" << std::endl; 1460 exit(0); 1461 } 1462 else // nothing to do : return to LOOP 1463 { 1464 r_config_nlines = r_config_nlines.read() - 1; 1465 r_config_address = r_config_address.read() + (m_words*vci_param_int::B); 1466 r_config_fsm = CONFIG_LOOP; 1467 } 1468 1469 #if DEBUG_MEMC_CONFIG 1470 if(m_debug) 1471 std::cout << " <MEMC " << name() << " CONFIG_DIR_ACCESS> Accessing directory: " 1472 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 1473 << " / hit = " << std::dec << entry.valid 1474 << " / dirty = " <<std::dec << entry.dirty 1475 << " / count = " <<std::dec << entry.count 1476 << " / is_cnt = " << entry.is_cnt << std::endl; 1477 #endif 1478 break; 1479 } 1480 ////////////////////// 1481 case CONFIG_DIR_INVAL: // Invalidate the directory entry 1482 { 1483 size_t set = m_y[(addr_t)(r_config_address.read())]; 1484 size_t way = r_config_way.read(); 1485 1486 m_cache_directory.inval( way, set ); 1487 1488 if ( r_config_count.read() == 0 ) // return to LOOP 1489 { 1490 r_config_nlines = r_config_nlines.read() - 1; 1491 r_config_address = r_config_address.read() + (m_words*vci_param_int::B); 1492 r_config_fsm = CONFIG_LOOP; 1493 } 1494 else if ( r_config_is_cnt.read() ) // broacast required 1495 { 1496 r_config_fsm = CONFIG_BC_UPT_LOCK; 1497 } 1498 else 1499 { 1500 r_config_fsm = CONFIG_UPT_LOCK; 1501 } 1502 1503 #if DEBUG_MEMC_CONFIG 1504 if(m_debug) 1505 std::cout << " <MEMC " << name() << " CONFIG_DIR_INVAL> Inval directory entry" << std::endl; 1506 #endif 1507 break; 1508 } 1509 //////////////////////// 1510 case CONFIG_BC_UPT_LOCK: // try to register BC transaction in UPT 1511 { 1512 if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG ) 1513 { 1514 bool wok = false; 1515 size_t index = 0; 1516 size_t srcid = r_config_srcid.read(); 1517 size_t trdid = r_config_trdid.read(); 1518 size_t pktid = r_config_pktid.read(); 1519 addr_t nline = m_nline[(addr_t)(r_config_address.read())]; 1520 size_t nb_copies = r_config_count.read(); 1521 1522 wok = m_upt.set(false, // it's an inval transaction 1523 true, // it's a broadcast 1524 false, // no response required 1525 true, // acknowledge required 1526 srcid, 1527 trdid, 1528 pktid, 1529 nline, 1530 nb_copies, 1531 index); 1532 if ( wok ) 1533 { 1534 r_config_fsm = CONFIG_BC_SEND; 1535 r_config_upt_index = index; 1536 1537 #if DEBUG_MEMC_CONFIG 1538 if( m_debug ) 1539 std::cout << " <MEMC " << name() 1540 << " CONFIG_BC_UPT_LOCK> Register broadcast inval in UPT" << std::endl; 1541 #endif 1542 } 1543 else 1544 { 1545 r_config_fsm = CONFIG_UPT_WAIT; 1546 1547 #if DEBUG_MEMC_CONFIG 1548 if( m_debug ) 1549 std::cout << " <MEMC " << name() << " CONFIG_BC_UPT_LOCK>" 1550 << " UPT full" << std::endl; 1551 #endif 1552 } 1553 } 1554 break; 1555 } 1556 //////////////////// 1557 case CONFIG_BC_SEND: // Post a broadcast inval request to CC_SEND FSM 1558 { 1559 if( not r_config_to_cc_send_multi_req.read() and 1560 not r_config_to_cc_send_brdcast_req.read() ) 1561 { 1562 r_config_to_cc_send_multi_req = false; 1563 r_config_to_cc_send_brdcast_req = true; 1564 r_config_to_cc_send_trdid = r_config_upt_index.read(); 1565 r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; 1566 1567 r_cleanup_to_config_ack = false; 1568 1569 r_config_fsm = CONFIG_BC_WAIT; 1570 1571 #if DEBUG_MEMC_CONFIG 1572 if(m_debug) 1573 std::cout << " <MEMC " << name() << " CONFIG_BC_SEND>" 1574 << " Post a broadcast inval request to CC_SEND FSM" 1575 << " / address = " << r_config_address.read() <<std::endl; 1576 #endif 1577 } 1578 break; 1579 } 1580 //////////////////// 1581 case CONFIG_BC_WAIT: // wait broadcast completion to return to LOOP 1582 { 1583 if ( r_cleanup_to_config_ack.read() ) r_config_fsm = CONFIG_LOOP; 1584 1585 #if DEBUG_MEMC_CONFIG 1586 if(m_debug) 1587 std::cout << " <MEMC " << name() << " CONFIG_BC_WAIT>" 1588 << " Waiting broadcast inval completion" << std::endl; 1589 #endif 1590 break; 1591 } 1592 ///////////////////// 1593 case CONFIG_UPT_LOCK: // Try to register multi-update in UPT 1594 { 1595 if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CONFIG ) 1596 { 1597 bool wok = false; 1598 size_t index = 0; 1599 size_t srcid = r_config_srcid.read(); 1600 size_t trdid = r_config_trdid.read(); 1601 size_t pktid = r_config_pktid.read(); 1602 addr_t nline = m_nline[(addr_t)(r_config_address.read())]; 1603 size_t nb_copies = r_config_count.read(); 1604 1605 wok = m_upt.set(false, // it's an inval transaction 1606 false, // not a broadcast 1607 false, // no response required 1608 true, // acknowledge required 1609 srcid, 1610 trdid, 1611 pktid, 1612 nline, 1613 nb_copies, 1614 index); 1615 if ( wok ) 1616 { 1617 r_config_fsm = CONFIG_BC_SEND; 1618 r_config_upt_index = index; 1619 1620 #if DEBUG_MEMC_CONFIG 1621 if( m_debug ) 1622 std::cout << " <MEMC " << name() 1623 << " CONFIG_BC_UPT_LOCK> Register broadcast inval in UPT" << std::endl; 1624 #endif 1625 } 1626 else 1627 { 1628 r_config_fsm = CONFIG_UPT_WAIT; 1629 1630 #if DEBUG_MEMC_CONFIG 1631 if( m_debug ) 1632 std::cout << " <MEMC " << name() << " CONFIG_BC_UPT_LOCK>" 1633 << " UPT full" << std::endl; 1634 #endif 1635 } 1636 1637 #if DEBUG_MEMC_CONFIG 1638 if(m_debug) 1639 std::cout << " <MEMC " << name() << " CONFIG_UPT_LOCK> Request access to UPT" << std::endl; 1640 #endif 1641 } 1642 break; 1643 } 1644 ///////////////////// 1645 case CONFIG_HEAP_REQ: // request access to the heap 1646 { 1647 break; 1648 } 1649 1650 //////////////// 1651 case CONFIG_RSP: // request TGT_RSP FSM to return response 1652 { 1653 if ( not r_config_to_tgt_rsp_req ) 1654 { 1655 r_config_to_tgt_rsp_srcid = r_config_srcid.read(); 1656 r_config_to_tgt_rsp_trdid = r_config_trdid.read(); 1657 r_config_to_tgt_rsp_pktid = r_config_pktid.read(); 1658 r_config_to_tgt_rsp_error = false; 1659 r_config_to_tgt_rsp_req = true; 1660 r_config_fsm = CONFIG_IDLE; 1661 1662 #if DEBUG_MEMC_CONFIG 1663 if(m_debug) 1664 std::cout << " <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to return response:" 1665 << " error = " << r_config_to_tgt_rsp_error.read() 1666 << " / rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; 1667 #endif 1668 } 1669 break; 1670 1671 } 1672 ///////////////////// 1673 case CONFIG_UPT_WAIT: // release the lock on UPT for one cycle, and retry 1674 { 1675 if ( r_config_is_cnt.read() ) r_config_fsm = CONFIG_BC_UPT_LOCK; 1676 else r_config_fsm = CONFIG_UPT_LOCK; 1677 1678 #if DEBUG_MEMC_CONFIG 1679 if(m_debug) 1680 std::cout << " <MEMC " << name() << " CONFIG_UPT_WAIT>" 1681 << " Release UPT lock" << std::endl; 1682 #endif 1683 break; 1684 } 1685 } // end switch r_config_fsm 1305 1686 1306 1687 //////////////////////////////////////////////////////////////////////////////////// … … 1329 1710 switch(r_read_fsm.read()) 1330 1711 { 1331 /////////////// 1332 case READ_IDLE: 1333 // waiting a read request 1334 { 1712 /////////////// 1713 case READ_IDLE: // waiting a read request 1714 { 1335 1715 if(m_cmd_read_addr_fifo.rok()) 1336 1716 { 1337 1717 1338 1718 #if DEBUG_MEMC_READ 1339 if(m_debug _read_fsm)1719 if(m_debug) 1340 1720 std::cout << " <MEMC " << name() << " READ_IDLE> Read request" 1341 1721 << " : address = " << std::hex << m_cmd_read_addr_fifo.read() … … 1350 1730 } 1351 1731 1732 ////////////////// 1733 case READ_DIR_REQ: // Get the lock to the directory 1734 { 1735 if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) 1736 { 1737 r_read_fsm = READ_DIR_LOCK; 1738 } 1739 1740 #if DEBUG_MEMC_READ 1741 if(m_debug) 1742 std::cout << " <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl; 1743 #endif 1744 break; 1745 } 1746 1352 1747 /////////////////// 1353 case READ_DIR_REQ: 1354 // Get the lock to the directory 1355 { 1356 if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) 1357 { 1358 r_read_fsm = READ_DIR_LOCK; 1359 } 1360 1361 #if DEBUG_MEMC_READ 1362 if(m_debug_read_fsm) 1363 std::cout << " <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl; 1364 #endif 1365 break; 1366 } 1367 1368 /////////////////// 1369 case READ_DIR_LOCK: 1370 // check directory for hit / miss 1748 case READ_DIR_LOCK: // check directory for hit / miss 1371 1749 { 1372 1750 if(r_alloc_dir_fsm.read() == ALLOC_DIR_READ) … … 1400 1778 { 1401 1779 // test if we need to register a new copy in the heap 1402 if(entry.is_cnt || (entry.count == 0) ||!cached_read)1780 if(entry.is_cnt or (entry.count == 0) or !cached_read) 1403 1781 { 1404 1782 r_read_fsm = READ_DIR_HIT; … … 1415 1793 1416 1794 #if DEBUG_MEMC_READ 1417 if(m_debug _read_fsm)1795 if(m_debug) 1418 1796 { 1419 1797 std::cout << " <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: " … … 1503 1881 1504 1882 #if DEBUG_MEMC_READ 1505 if(m_debug _read_fsm)1883 if(m_debug) 1506 1884 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 1507 1885 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() … … 1539 1917 1540 1918 #if DEBUG_MEMC_READ 1541 if(m_debug _read_fsm)1919 if(m_debug) 1542 1920 std::cout << " <MEMC " << name() << " READ_HEAP_REQ>" 1543 1921 << " Requesting HEAP lock " << std::endl; … … 1553 1931 { 1554 1932 // enter counter mode when we reach the limit of copies or the heap is full 1555 bool go_cnt = (r_read_count.read() >= m_max_copies) ||m_heap.is_full();1933 bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full(); 1556 1934 1557 1935 // read data in the cache … … 1626 2004 1627 2005 #if DEBUG_MEMC_READ 1628 if(m_debug _read_fsm)2006 if(m_debug) 1629 2007 std::cout << " <MEMC " << name() << " READ_HEAP_LOCK> Update directory:" 1630 2008 << " tag = " << std::hex << entry.tag … … 1670 2048 1671 2049 #if DEBUG_MEMC_READ 1672 if(m_debug _read_fsm)2050 if(m_debug) 1673 2051 std::cout << " <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:" 1674 2052 << " owner_id = " << std::hex << heap_entry.owner.srcid … … 1758 2136 1759 2137 #if DEBUG_MEMC_READ 1760 if(m_debug _read_fsm)2138 if(m_debug) 1761 2139 std::cout << " <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:" 1762 2140 << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() … … 1778 2156 bool wok = !m_trt.full(index); 1779 2157 1780 if(hit_read || !wok ||hit_write) // missing line already requested or no space2158 if(hit_read or !wok or hit_write) // missing line already requested or no space 1781 2159 { 1782 2160 if(!wok) m_cpt_trt_full++; 1783 if(hit_read ||hit_write) m_cpt_trt_rb++;2161 if(hit_read or hit_write) m_cpt_trt_rb++; 1784 2162 r_read_fsm = READ_IDLE; 1785 2163 } … … 1792 2170 1793 2171 #if DEBUG_MEMC_READ 1794 if(m_debug _read_fsm)2172 if(m_debug) 1795 2173 std::cout << " <MEMC " << name() << " READ_TRT_LOCK> Check TRT:" 1796 2174 << " hit_read = " << hit_read … … 1820 2198 r_read_ll_key.read()); 1821 2199 #if DEBUG_MEMC_READ 1822 if(m_debug _read_fsm)2200 if(m_debug) 1823 2201 std::cout << " <MEMC " << name() << " READ_TRT_SET> Write in Transaction Table:" 1824 2202 << " address = " << std::hex << m_cmd_read_addr_fifo.read() 1825 << " / srcid = " << std:: dec<< m_cmd_read_srcid_fifo.read() << std::endl;2203 << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; 1826 2204 #endif 1827 2205 r_read_fsm = READ_TRT_REQ; … … 1842 2220 1843 2221 #if DEBUG_MEMC_READ 1844 if(m_debug _read_fsm)2222 if(m_debug) 1845 2223 std::cout << " <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address " 1846 2224 << std::hex << m_cmd_read_addr_fifo.read() << std::endl; … … 1884 2262 switch(r_write_fsm.read()) 1885 2263 { 1886 2264 //////////////// 1887 2265 case WRITE_IDLE: // copy first word of a write burst in local buffer 1888 2266 { … … 1917 2295 } 1918 2296 1919 if (m_cmd_write_eop_fifo.read() ||((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC))2297 if (m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)) 1920 2298 { 1921 2299 r_write_fsm = WRITE_DIR_REQ; … … 1927 2305 1928 2306 #if DEBUG_MEMC_WRITE 1929 if(m_debug _write_fsm)2307 if(m_debug) 1930 2308 { 1931 2309 std::cout << " <MEMC " << name() << " WRITE_IDLE> Write request " … … 1946 2324 1947 2325 #if DEBUG_MEMC_WRITE 1948 if(m_debug _write_fsm)2326 if(m_debug) 1949 2327 { 1950 2328 std::cout << " <MEMC " << name() … … 1999 2377 if(not m_cmd_write_addr_fifo.rok()) break; 2000 2378 2001 assert(m_cmd_write_eop_fifo.read() &&2379 assert(m_cmd_write_eop_fifo.read() and 2002 2380 "Error in VCI_MEM_CACHE : " 2003 2381 "invalid packet format for SC command"); … … 2030 2408 2031 2409 #if DEBUG_MEMC_WRITE 2032 if(m_debug _write_fsm)2410 if(m_debug) 2033 2411 { 2034 2412 std::cout … … 2065 2443 r_write_way = way; 2066 2444 2067 if(entry.is_cnt &&entry.count)2445 if(entry.is_cnt and entry.count) 2068 2446 { 2069 2447 r_write_fsm = WRITE_DIR_READ; … … 2080 2458 2081 2459 #if DEBUG_MEMC_WRITE 2082 if(m_debug _write_fsm)2460 if(m_debug) 2083 2461 { 2084 2462 std::cout << " <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: " … … 2130 2508 2131 2509 #if DEBUG_MEMC_WRITE 2132 if(m_debug _write_fsm)2510 if(m_debug) 2133 2511 { 2134 2512 std::cout << " <MEMC " << name() << " WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl; … … 2172 2550 // no_update is true when there is no need for coherence transaction 2173 2551 // (tests for sc requests) 2174 bool no_update = ((r_write_count.read() ==0) || (owner && (r_write_count.read() ==1) && (r_write_pktid.read() != TYPE_SC))); 2552 bool no_update = ( (r_write_count.read() == 0) or 2553 (owner and (r_write_count.read() ==1) and (r_write_pktid.read() != TYPE_SC))); 2175 2554 2176 2555 // write data in the cache if no coherence transaction … … 2205 2584 // coherence update required 2206 2585 { 2207 if(!r_write_to_cc_send_multi_req.read() &&2586 if(!r_write_to_cc_send_multi_req.read() and 2208 2587 !r_write_to_cc_send_brdcast_req.read()) 2209 2588 { … … 2217 2596 2218 2597 #if DEBUG_MEMC_WRITE 2219 if(m_debug_write_fsm)2220 2221 2222 2223 std::cout << " <MEMC " << name() << " WRITE_DIR_HIT> Write into cache / No coherence transaction"2224 << std::endl;2225 }2226 else2227 {2228 std::cout << " <MEMC " << name() << " WRITE_DIR_HIT> Coherence update required:"2229 << " is_cnt = " << r_write_is_cnt.read()2230 << " nb_copies = " << std::dec << r_write_count.read() << std::endl;2231 if(owner)2232 2233 2234 2598 if(m_debug) 2599 { 2600 if(no_update) 2601 { 2602 std::cout << " <MEMC " << name() 2603 << " WRITE_DIR_HIT> Write into cache / No coherence transaction" 2604 << std::endl; 2605 } 2606 else 2607 { 2608 std::cout << " <MEMC " << name() << " WRITE_DIR_HIT> Coherence update required:" 2609 << " is_cnt = " << r_write_is_cnt.read() 2610 << " nb_copies = " << std::dec << r_write_count.read() << std::endl; 2611 if(owner) std::cout << " ... but the first copy is the writer" << std::endl; 2612 } 2613 } 2235 2614 #endif 2236 2615 break; … … 2253 2632 2254 2633 wok = m_upt.set(true, // it's an update transaction 2255 false, // it's not a broadcast 2256 true, // it needs a response 2257 srcid, 2258 trdid, 2259 pktid, 2260 nline, 2261 nb_copies, 2262 index); 2634 false, // it's not a broadcast 2635 true, // response required 2636 false, // no acknowledge required 2637 srcid, 2638 trdid, 2639 pktid, 2640 nline, 2641 nb_copies, 2642 index); 2263 2643 if(wok) // write data in cache 2264 2644 { … … 2282 2662 2283 2663 #if DEBUG_MEMC_WRITE 2284 if(m_debug_write_fsm) 2285 { 2286 if(wok) 2287 { 2288 std::cout << " <MEMC " << name() << " WRITE_UPT_LOCK> Register the multicast update in UPT / " 2289 << " nb_copies = " << r_write_count.read() << std::endl; 2290 } 2291 } 2664 if(m_debug) 2665 { 2666 if(wok) 2667 { 2668 std::cout << " <MEMC " << name() 2669 << " WRITE_UPT_LOCK> Register the multicast update in UPT / " 2670 << " nb_copies = " << r_write_count.read() << std::endl; 2671 } 2672 } 2292 2673 #endif 2293 2674 r_write_upt_index = index; … … 2306 2687 2307 2688 #if DEBUG_MEMC_WRITE 2308 if(m_debug_write_fsm) 2309 { 2310 std::cout << " <MEMC " << name() << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl; 2311 } 2689 if(m_debug) 2690 std::cout << " <MEMC " << name() 2691 << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl; 2312 2692 #endif 2313 2693 r_write_fsm = WRITE_UPT_REQ; … … 2317 2697 2318 2698 ////////////////// 2319 case WRITE_UPT_REQ: 2320 { 2321 // prepare the coherence transaction for the CC_SEND FSM 2322 // and write the first copy in the FIFO 2323 // send the request if only one copy 2324 2699 case WRITE_UPT_REQ: // prepare the coherence transaction for the CC_SEND FSM 2700 // and write the first copy in the FIFO 2701 // send the request if only one copy 2702 { 2325 2703 assert(not r_write_to_cc_send_multi_req.read() and 2326 2704 not r_write_to_cc_send_brdcast_req.read() and … … 2373 2751 2374 2752 #if DEBUG_MEMC_WRITE 2375 if(m_debug _write_fsm)2753 if(m_debug) 2376 2754 { 2377 2755 std::cout … … 2404 2782 bool dec_upt_counter; 2405 2783 2406 if(((entry.owner.srcid != r_write_srcid.read()) ||(r_write_pktid.read() == TYPE_SC)) or2784 if(((entry.owner.srcid != r_write_srcid.read()) or (r_write_pktid.read() == TYPE_SC)) or 2407 2785 #if L1_MULTI_CACHE 2408 2786 (entry.owner.cache_id != r_write_pktid.read()) or … … 2419 2797 2420 2798 #if DEBUG_MEMC_WRITE 2421 if(m_debug _write_fsm)2799 if(m_debug) 2422 2800 { 2423 2801 std::cout << " <MEMC " << name() << " WRITE_UPT_NEXT> Post another request to CC_SEND FSM" … … 2435 2813 2436 2814 #if DEBUG_MEMC_WRITE 2437 if(m_debug _write_fsm)2815 if(m_debug) 2438 2816 { 2439 2817 std::cout << " <MEMC " << name() << " WRITE_UPT_NEXT> Skip one entry in heap matching the writer" … … 2533 2911 } 2534 2912 2535 if(m_cmd_write_eop_fifo.read() ||((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC))2913 if(m_cmd_write_eop_fifo.read() or ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)) 2536 2914 { 2537 2915 r_write_fsm = WRITE_DIR_REQ; … … 2548 2926 2549 2927 #if DEBUG_MEMC_WRITE 2550 if(m_debug _write_fsm)2928 if(m_debug) 2551 2929 { 2552 2930 std::cout << " <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM" … … 2572 2950 2573 2951 #if DEBUG_MEMC_WRITE 2574 if(m_debug _write_fsm)2952 if(m_debug) 2575 2953 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl; 2576 2954 #endif … … 2588 2966 m_cpt_write_miss++; 2589 2967 } 2590 else if(wok &&!hit_write) // set a new entry in TRT2968 else if(wok and !hit_write) // set a new entry in TRT 2591 2969 { 2592 2970 r_write_trt_index = wok_index; … … 2608 2986 2609 2987 #if DEBUG_MEMC_WRITE 2610 if(m_debug _write_fsm)2988 if(m_debug) 2611 2989 std::cout << " <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl; 2612 2990 #endif … … 2643 3021 2644 3022 #if DEBUG_MEMC_WRITE 2645 if(m_debug _write_fsm)3023 if(m_debug) 2646 3024 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl; 2647 3025 #endif … … 2670 3048 2671 3049 #if DEBUG_MEMC_WRITE 2672 if(m_debug _write_fsm)3050 if(m_debug) 2673 3051 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl; 2674 3052 #endif … … 2689 3067 2690 3068 #if DEBUG_MEMC_WRITE 2691 if(m_debug _write_fsm)3069 if(m_debug) 2692 3070 std::cout << " <MEMC " << name() << " WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl; 2693 3071 #endif … … 2714 3092 2715 3093 #if DEBUG_MEMC_WRITE 2716 if(m_debug _write_fsm)3094 if(m_debug) 2717 3095 std::cout << " <MEMC " << name() << " WRITE_BC_TRT_LOCK> Check TRT" 2718 3096 << " : wok = " << wok << " / index = " << wok_index << std::endl; … … 2735 3113 size_t nb_copies = r_write_count.read(); 2736 3114 2737 wok =m_upt.set(false, // it's an inval transaction 2738 true, // it's a broadcast 2739 true, // it needs a response 2740 srcid, 2741 trdid, 2742 pktid, 2743 nline, 2744 nb_copies, 2745 index); 3115 wok = m_upt.set(false, // it's an inval transaction 3116 true, // it's a broadcast 3117 true, // response required 3118 false, // no acknowledge required 3119 srcid, 3120 trdid, 3121 pktid, 3122 nline, 3123 nb_copies, 3124 index); 2746 3125 2747 3126 #if DEBUG_MEMC_WRITE 2748 if( m_debug _write_fsmand wok )3127 if( m_debug and wok ) 2749 3128 std::cout << " <MEMC " << name() << " WRITE_BC_UPT_LOCK> Register broadcast inval in UPT" 2750 3129 << " / nb_copies = " << r_write_count.read() << std::endl; … … 2763 3142 // Register a put transaction to XRAM in TRT 2764 3143 // and invalidate the line in directory 2765 if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) ||2766 (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) ||3144 if((r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) or 3145 (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE) or 2767 3146 (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE)) 2768 3147 { … … 2805 3184 2806 3185 #if DEBUG_MEMC_WRITE 2807 if(m_debug _write_fsm)3186 if(m_debug) 2808 3187 std::cout << " <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = " 2809 3188 << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; … … 2816 3195 case WRITE_BC_CC_SEND: // Post a coherence broadcast request to CC_SEND FSM 2817 3196 { 2818 if(!r_write_to_cc_send_multi_req.read() &&!r_write_to_cc_send_brdcast_req.read())3197 if(!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read()) 2819 3198 { 2820 3199 r_write_to_cc_send_multi_req = false; … … 2833 3212 2834 3213 #if DEBUG_MEMC_WRITE 2835 if(m_debug_write_fsm) 2836 { 2837 std::cout << " <MEMC " << name() 2838 << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl; 2839 } 3214 if(m_debug) 3215 std::cout << " <MEMC " << name() 3216 << " WRITE_BC_CC_SEND> Post a broadcast request to CC_SEND FSM" << std::endl; 2840 3217 #endif 2841 3218 } … … 2858 3235 2859 3236 #if DEBUG_MEMC_WRITE 2860 if(m_debug_write_fsm) 2861 { 2862 std::cout << " <MEMC " << name() 2863 << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl; 2864 } 3237 if(m_debug) 3238 std::cout << " <MEMC " << name() 3239 << " WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl; 2865 3240 #endif 2866 3241 } … … 2934 3309 2935 3310 #if DEBUG_MEMC_IXR_CMD 2936 if(m_debug _ixr_cmd_fsm)3311 if(m_debug) 2937 3312 std::cout << " <MEMC " << name() << " IXR_CMD_READ>" 2938 3313 << " Send a get request to xram / address = " << std::hex … … 2961 3336 2962 3337 #if DEBUG_MEMC_IXR_CMD 2963 if(m_debug _ixr_cmd_fsm)3338 if(m_debug) 2964 3339 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE>" 2965 3340 << " Send a put request to xram / address = " << std::hex … … 2974 3349 2975 3350 #if DEBUG_MEMC_IXR_CMD 2976 if(m_debug _ixr_cmd_fsm)3351 if(m_debug) 2977 3352 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE>" 2978 3353 << " Send a get request to xram / address = " << std::hex … … 3002 3377 3003 3378 #if DEBUG_MEMC_IXR_CMD 3004 if(m_debug _ixr_cmd_fsm)3379 if(m_debug) 3005 3380 std::cout << " <MEMC " << name() << " IXR_CMD_CAS>" 3006 3381 << " Send a put request to xram / address = " << std::hex … … 3015 3390 3016 3391 #if DEBUG_MEMC_IXR_CMD 3017 if(m_debug _ixr_cmd_fsm)3392 if(m_debug) 3018 3393 std::cout << " <MEMC " << name() << " IXR_CMD_CAS>" 3019 3394 << " Send a get request to xram / address = " << std::hex … … 3041 3416 3042 3417 #if DEBUG_MEMC_IXR_CMD 3043 if(m_debug _ixr_cmd_fsm)3418 if(m_debug) 3044 3419 std::cout << " <MEMC " << name() << " IXR_CMD_XRAM>" 3045 3420 << " Send a put request to xram / address = " << std::hex … … 3081 3456 r_ixr_rsp_cpt = 0; 3082 3457 r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); 3083 if(p_vci_ixr.reop.read() &&!(p_vci_ixr.rerror.read() &0x1)) // PUT transaction3458 if(p_vci_ixr.reop.read() and !(p_vci_ixr.rerror.read() &0x1)) // PUT transaction 3084 3459 { 3085 3460 r_ixr_rsp_fsm = IXR_RSP_ACK; 3086 3461 3087 3462 #if DEBUG_MEMC_IXR_RSP 3088 if(m_debug_ixr_rsp_fsm) 3089 { 3090 std::cout << " <MEMC " << name() 3091 << " IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl; 3092 } 3463 if(m_debug) 3464 std::cout << " <MEMC " << name() 3465 << " IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl; 3093 3466 #endif 3094 3467 } … … 3098 3471 3099 3472 #if DEBUG_MEMC_IXR_RSP 3100 if(m_debug_ixr_rsp_fsm) 3101 { 3102 std::cout << " <MEMC " << name() 3103 << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl; 3104 } 3473 if(m_debug) 3474 std::cout << " <MEMC " << name() 3475 << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl; 3105 3476 #endif 3106 3477 } … … 3114 3485 3115 3486 #if DEBUG_MEMC_IXR_RSP 3116 if(m_debug_ixr_rsp_fsm) 3117 { 3118 std::cout << " <MEMC " << name() << " IXR_RSP_ACK>" << std::endl; 3119 } 3487 if(m_debug) 3488 std::cout << " <MEMC " << name() << " IXR_RSP_ACK>" << std::endl; 3120 3489 #endif 3121 3490 break; … … 3130 3499 3131 3500 #if DEBUG_MEMC_IXR_RSP 3132 if(m_debug_ixr_rsp_fsm) 3133 { 3134 std::cout << " <MEMC " << name() << " IXR_RSP_TRT_ERASE> Erase TRT entry " 3135 << r_ixr_rsp_trt_index.read() << std::endl; 3136 } 3501 if(m_debug) 3502 std::cout << " <MEMC " << name() << " IXR_RSP_TRT_ERASE> Erase TRT entry " 3503 << r_ixr_rsp_trt_index.read() << std::endl; 3137 3504 #endif 3138 3505 } … … 3142 3509 case IXR_RSP_TRT_READ: // write a 64 bits data in the TRT 3143 3510 { 3144 if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&p_vci_ixr.rspval)3511 if((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) 3145 3512 { 3146 3513 size_t index = r_ixr_rsp_trt_index.read(); … … 3149 3516 bool error = ((p_vci_ixr.rerror.read() & 0x1) == 1); 3150 3517 3151 assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) ||p_vci_ixr.rerror.read())3518 assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-2))) or p_vci_ixr.rerror.read()) 3152 3519 and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM"); 3153 3520 … … 3166 3533 3167 3534 #if DEBUG_MEMC_IXR_RSP 3168 if(m_debug_ixr_rsp_fsm) 3169 { 3170 std::cout << " <MEMC " << name() << " IXR_RSP_TRT_READ> Writing a word in TRT : " 3171 << " index = " << std::dec << index 3172 << " / word = " << r_ixr_rsp_cpt.read() 3173 << " / data = " << std::hex << data << std::endl; 3174 } 3535 if(m_debug) 3536 std::cout << " <MEMC " << name() << " IXR_RSP_TRT_READ> Writing a word in TRT : " 3537 << " index = " << std::dec << index 3538 << " / word = " << r_ixr_rsp_cpt.read() 3539 << " / data = " << std::hex << data << std::endl; 3175 3540 #endif 3176 3541 } … … 3219 3584 3220 3585 #if DEBUG_MEMC_XRAM_RSP 3221 if(m_debug _xram_rsp_fsm)3586 if(m_debug) 3222 3587 std::cout << " <MEMC " << name() << " XRAM_RSP_IDLE>" 3223 3588 << " Available cache line in TRT:" … … 3233 3598 // Copy the TRT entry in a local buffer 3234 3599 { 3235 if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) &&3600 if((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and 3236 3601 (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)) 3237 3602 { … … 3242 3607 r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; 3243 3608 3244 // TransactionTabEntry trt_entry(m_trt.read(index));3245 // r_xram_rsp_trt_buf.copy(trt_entry); // TRT entry local buffer3246 3247 3609 #if DEBUG_MEMC_XRAM_RSP 3248 if(m_debug _xram_rsp_fsm)3610 if(m_debug) 3249 3611 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_LOCK>" 3250 3612 << " Get access to DIR and TRT" << std::endl; … … 3266 3628 DirectoryEntry victim(m_cache_directory.select(set, way)); 3267 3629 3268 bool inval = (victim.count &&victim.valid) ;3630 bool inval = (victim.count and victim.valid) ; 3269 3631 3270 3632 // copy the victim line in a local buffer … … 3296 3658 3297 3659 #if DEBUG_MEMC_XRAM_RSP 3298 if(m_debug _xram_rsp_fsm)3660 if(m_debug) 3299 3661 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_COPY>" 3300 3662 << " Select a slot: " … … 3323 3685 3324 3686 #if DEBUG_MEMC_XRAM_RSP 3325 if(m_debug _xram_rsp_fsm)3687 if(m_debug) 3326 3688 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 3327 3689 << " Get acces to UPT, but line invalidation registered" … … 3331 3693 3332 3694 } 3333 else if(m_upt.is_full() &&r_xram_rsp_victim_inval.read()) // UPT full3695 else if(m_upt.is_full() and r_xram_rsp_victim_inval.read()) // UPT full 3334 3696 { 3335 3697 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 3336 3698 3337 3699 #if DEBUG_MEMC_XRAM_RSP 3338 if(m_debug _xram_rsp_fsm)3700 if(m_debug) 3339 3701 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 3340 3702 << " Get acces to UPT, but inval required and UPT full" << std::endl; … … 3346 3708 3347 3709 #if DEBUG_MEMC_XRAM_RSP 3348 if(m_debug _xram_rsp_fsm)3710 if(m_debug) 3349 3711 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_LOCK>" 3350 3712 << " Get acces to UPT" << std::endl; … … 3359 3721 3360 3722 #if DEBUG_MEMC_XRAM_RSP 3361 if(m_debug _xram_rsp_fsm)3723 if(m_debug) 3362 3724 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_WAIT>" 3363 3725 << " Release all locks and retry" << std::endl; … … 3373 3735 // TYPE_READ_INS_UNC 0bX010 with TSAR encoding 3374 3736 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 3375 bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) &&r_xram_rsp_trt_buf.proc_read;3737 bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read; 3376 3738 3377 3739 // check if this is a cached read, this means pktid is either 3378 3740 // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding 3379 3741 // TYPE_READ_INS_MISS 0bX011 with TSAR encoding 3380 bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) &&r_xram_rsp_trt_buf.proc_read;3742 bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read; 3381 3743 3382 3744 bool dirty = false; … … 3389 3751 m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]); 3390 3752 3391 dirty = dirty ||(r_xram_rsp_trt_buf.wdata_be[word] != 0);3753 dirty = dirty or (r_xram_rsp_trt_buf.wdata_be[word] != 0); 3392 3754 3393 3755 if(m_monitor_ok) … … 3435 3797 bool wok = m_upt.set(false, // it's an inval transaction 3436 3798 broadcast, // set broadcast bit 3437 false, // it does not need a response 3799 false, // no response required 3800 false, // no acknowledge required 3438 3801 0, // srcid 3439 3802 0, // trdid … … 3454 3817 3455 3818 #if DEBUG_MEMC_XRAM_RSP 3456 if(m_debug _xram_rsp_fsm)3819 if(m_debug) 3457 3820 { 3458 3821 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_UPDT>" … … 3500 3863 3501 3864 #if DEBUG_MEMC_XRAM_RSP 3502 if(m_debug _xram_rsp_fsm)3865 if(m_debug) 3503 3866 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>" 3504 3867 << " Set TRT entry for the put transaction" … … 3534 3897 3535 3898 #if DEBUG_MEMC_XRAM_RSP 3536 if(m_debug _xram_rsp_fsm)3899 if(m_debug) 3537 3900 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_RSP>" 3538 3901 << " Request the TGT_RSP FSM to return data:" … … 3547 3910 case XRAM_RSP_INVAL: // send invalidate request to CC_SEND FSM 3548 3911 { 3549 if(!r_xram_rsp_to_cc_send_multi_req.read() &&3912 if(!r_xram_rsp_to_cc_send_multi_req.read() and 3550 3913 !r_xram_rsp_to_cc_send_brdcast_req.read()) 3551 3914 { 3552 3915 bool multi_req = !r_xram_rsp_victim_is_cnt.read(); 3553 bool last_multi_req = multi_req &&(r_xram_rsp_victim_count.read() == 1);3554 bool not_last_multi_req = multi_req &&(r_xram_rsp_victim_count.read() != 1);3916 bool last_multi_req = multi_req and (r_xram_rsp_victim_count.read() == 1); 3917 bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); 3555 3918 3556 3919 r_xram_rsp_to_cc_send_multi_req = last_multi_req; … … 3571 3934 3572 3935 #if DEBUG_MEMC_XRAM_RSP 3573 if(m_debug _xram_rsp_fsm)3936 if(m_debug) 3574 3937 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL>" 3575 3938 << " Send an inval request to CC_SEND FSM" … … 3593 3956 m_cpt_write_dirty++; 3594 3957 3595 bool multi_req = !r_xram_rsp_victim_is_cnt.read() &&r_xram_rsp_victim_inval.read();3596 bool not_last_multi_req = multi_req &&(r_xram_rsp_victim_count.read() != 1);3958 bool multi_req = !r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read(); 3959 bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); 3597 3960 3598 3961 if(not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; … … 3600 3963 3601 3964 #if DEBUG_MEMC_XRAM_RSP 3602 if(m_debug _xram_rsp_fsm)3965 if(m_debug) 3603 3966 std::cout << " <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY>" 3604 3967 << " Send the put request to IXR_CMD FSM" … … 3617 3980 3618 3981 #if DEBUG_MEMC_XRAM_RSP 3619 if(m_debug _xram_rsp_fsm)3982 if(m_debug) 3620 3983 std::cout << " <MEMC " << name() << " XRAM_RSP_HEAP_REQ>" 3621 3984 << " Requesting HEAP lock" << std::endl; … … 3655 4018 3656 4019 #if DEBUG_MEMC_XRAM_RSP 3657 if(m_debug _xram_rsp_fsm)4020 if(m_debug) 3658 4021 std::cout << " <MEMC " << name() << " XRAM_RSP_HEAP_ERASE>" 3659 4022 << " Erase copy:" 3660 << " srcid = " << std:: dec<< entry.owner.srcid4023 << " srcid = " << std::hex << entry.owner.srcid 3661 4024 << " / inst = " << std::dec << entry.owner.inst << std::endl; 3662 4025 #endif … … 3697 4060 3698 4061 #if DEBUG_MEMC_XRAM_RSP 3699 if(m_debug _xram_rsp_fsm)4062 if(m_debug) 3700 4063 std::cout << " <MEMC " << name() << " XRAM_RSP_HEAP_LAST>" 3701 4064 << " Heap housekeeping" << std::endl; … … 3713 4076 3714 4077 #if DEBUG_MEMC_XRAM_RSP 3715 if(m_debug _xram_rsp_fsm)4078 if(m_debug) 3716 4079 std::cout << " <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>" 3717 4080 << " Error reported by XRAM / erase the TRT entry" << std::endl; … … 3739 4102 3740 4103 #if DEBUG_MEMC_XRAM_RSP 3741 if(m_debug _xram_rsp_fsm)3742 3743 3744 4104 if(m_debug) 4105 std::cout << " <MEMC " << name() 4106 << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:" 4107 << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; 3745 4108 #endif 3746 4109 } … … 3803 4166 3804 4167 #if DEBUG_MEMC_CLEANUP 3805 if(m_debug_cleanup_fsm) 3806 { 3807 std::cout 3808 << " <MEMC " << name() 3809 << " CLEANUP_IDLE> Cleanup request:" << std::hex 3810 << " / owner_id = " << srcid 3811 << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) 3812 << std::endl; 3813 } 4168 if(m_debug) 4169 std::cout << " <MEMC " << name() 4170 << " CLEANUP_IDLE> Cleanup request:" << std::hex 4171 << " / owner_id = " << srcid 4172 << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl; 3814 4173 #endif 3815 4174 break; … … 3831 4190 3832 4191 #if DEBUG_MEMC_CLEANUP 3833 if(m_debug_cleanup_fsm) 3834 { 3835 std::cout 3836 << " <MEMC " << name() 3837 << " CLEANUP_GET_NLINE> Cleanup request:" 3838 << std::hex 3839 << " / address = " << nline * m_words * 4 3840 << std::endl; 3841 } 4192 if(m_debug) 4193 std::cout << " <MEMC " << name() 4194 << " CLEANUP_GET_NLINE> Cleanup request:" 4195 << " / address = " << std::hex << nline * m_words * 4 << std::endl; 3842 4196 #endif 3843 4197 break; … … 3845 4199 3846 4200 ///////////////////// 3847 case CLEANUP_DIR_REQ: 3848 { 3849 // Get the lock to the directory 4201 case CLEANUP_DIR_REQ: // Get the lock to the directory 4202 { 3850 4203 if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; 3851 4204 … … 3853 4206 3854 4207 #if DEBUG_MEMC_CLEANUP 3855 if(m_debug_cleanup_fsm) 3856 { 3857 std::cout 3858 << " <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock " 3859 << std::endl; 3860 } 4208 if(m_debug) 4209 std::cout << " <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock" << std::endl; 3861 4210 #endif 3862 4211 break; … … 3895 4244 #endif 3896 4245 3897 // hit : 3898 // the copy must be cleared 3899 if(entry.valid) 4246 if(entry.valid) // hit : the copy must be cleared 3900 4247 { 3901 4248 assert( 3902 (entry.count > 0) &&4249 (entry.count > 0) and 3903 4250 "VCI MEM CACHE ERROR: " 3904 4251 "In CLEANUP_DIR_LOCK, CLEANUP command on a valid entry " … … 3906 4253 3907 4254 // no access to the heap 3908 if((entry.count == 1) ||(entry.is_cnt))4255 if((entry.count == 1) or (entry.is_cnt)) 3909 4256 { 3910 4257 r_cleanup_fsm = CLEANUP_DIR_WRITE; … … 3916 4263 } 3917 4264 } 3918 // miss : 3919 // we must check the update table for a pending 3920 // invalidation transaction 3921 else 4265 else // miss : check UPT for a pending invalidation transaction 3922 4266 { 3923 4267 r_cleanup_fsm = CLEANUP_UPT_LOCK; … … 3925 4269 3926 4270 #if DEBUG_MEMC_CLEANUP 3927 if(m_debug _cleanup_fsm)4271 if(m_debug) 3928 4272 { 3929 4273 std::cout … … 3968 4312 3969 4313 bool match_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); 3970 bool match = match_srcid &&match_inst;4314 bool match = match_srcid and match_inst; 3971 4315 3972 4316 if(not r_cleanup_is_cnt.read() and not match) … … 3999 4343 m_cache_directory.write(set, way, entry); 4000 4344 4001 r_cleanup_fsm = CLEANUP_SEND_ ACK;4345 r_cleanup_fsm = CLEANUP_SEND_CLACK; 4002 4346 4003 4347 #if DEBUG_MEMC_CLEANUP 4004 if(m_debug _cleanup_fsm)4348 if(m_debug) 4005 4349 { 4006 4350 std::cout … … 4029 4373 4030 4374 #if DEBUG_MEMC_CLEANUP 4031 if(m_debug _cleanup_fsm)4375 if(m_debug) 4032 4376 { 4033 4377 std::cout … … 4182 4526 4183 4527 #if DEBUG_MEMC_CLEANUP 4184 if(m_debug _cleanup_fsm)4528 if(m_debug) 4185 4529 { 4186 4530 std::cout … … 4220 4564 bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); 4221 4565 bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); 4222 bool match_heap = match_heap_srcid &&match_heap_inst;4566 bool match_heap = match_heap_srcid and match_heap_inst; 4223 4567 4224 4568 #if L1_MULTI_CACHE … … 4260 4604 4261 4605 #if DEBUG_MEMC_CLEANUP 4262 if(m_debug _cleanup_fsm)4606 if(m_debug) 4263 4607 { 4264 4608 if(not match_heap) … … 4289 4633 break; 4290 4634 } 4291 4292 case CLEANUP_HEAP_CLEAN: 4293 { 4294 // remove a copy in the linked list 4635 //////////////////////// 4636 case CLEANUP_HEAP_CLEAN: // remove a copy in the linked list 4637 { 4295 4638 if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) 4296 4639 { … … 4329 4672 4330 4673 #if DEBUG_MEMC_CLEANUP 4331 if(m_debug_cleanup_fsm) 4332 { 4333 std::cout 4334 << " <MEMC " << name() 4335 << " CLEANUP_HEAP_SEARCH> Remove the copy in the linked list" 4336 << std::endl; 4337 } 4338 #endif 4339 break; 4340 } 4341 4342 case CLEANUP_HEAP_FREE: 4343 { 4344 // The heap entry pointed by r_cleanup_next_ptr is freed 4345 // and becomes the head of the list of free entries 4674 if(m_debug) 4675 std::cout << " <MEMC " << name() << " CLEANUP_HEAP_SEARCH>" 4676 << " Remove the copy in the linked list" << std::endl; 4677 #endif 4678 break; 4679 } 4680 /////////////////////// 4681 case CLEANUP_HEAP_FREE: // The heap entry pointed by r_cleanup_next_ptr is freed 4682 // and becomes the head of the list of free entries 4683 { 4346 4684 if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) 4347 4685 { … … 4375 4713 m_heap.unset_full(); 4376 4714 4377 r_cleanup_fsm = CLEANUP_SEND_ ACK;4715 r_cleanup_fsm = CLEANUP_SEND_CLACK; 4378 4716 4379 4717 #if DEBUG_MEMC_CLEANUP 4380 if(m_debug_cleanup_fsm) 4381 { 4382 std::cout 4383 << " <MEMC " << name() 4384 << " CLEANUP_HEAP_SEARCH> Update the list of free entries" 4385 << std::endl; 4386 } 4387 #endif 4388 break; 4389 } 4390 4391 case CLEANUP_UPT_LOCK: 4392 { 4393 // search pending invalidate transaction matching the Cleanup NLINE in the UPDATE TABLE 4394 // get the lock in the UPDATE_TABLE 4718 if(m_debug) 4719 std::cout << " <MEMC " << name() << " CLEANUP_HEAP_FREE>" 4720 << " Update the list of free entries" << std::endl; 4721 #endif 4722 break; 4723 } 4724 ////////////////////// 4725 case CLEANUP_UPT_LOCK: // get the lock protecting the UPT to search a pending 4726 // invalidate transaction matching the cleanup 4727 { 4395 4728 if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) break; 4396 4729 … … 4400 4733 match_inval = m_upt.search_inval(r_cleanup_nline.read(), index); 4401 4734 4402 // no pending inval 4403 if(not match_inval) 4404 { 4405 r_cleanup_fsm = CLEANUP_SEND_ACK; 4735 if ( not match_inval ) // no pending inval 4736 { 4737 r_cleanup_fsm = CLEANUP_SEND_CLACK; 4406 4738 4407 4739 #if DEBUG_MEMC_CLEANUP 4408 if(m_debug_cleanup_fsm) 4409 { 4410 std::cout 4411 << " <MEMC " << name() 4412 << " CLEANUP_UPT_LOCK> Unexpected cleanup" 4413 << " with no corresponding UPT entry:" 4414 << " address = " << std::hex 4415 << (r_cleanup_nline.read() *4*m_words) 4416 << std::endl; 4417 } 4418 #endif 4419 break; 4740 if(m_debug) 4741 std::cout << " <MEMC " << name() 4742 << " CLEANUP_UPT_LOCK> Unexpected cleanup" 4743 << " with no corresponding UPT entry:" 4744 << " address = " << std::hex 4745 << (r_cleanup_nline.read() *4*m_words) 4746 << std::endl; 4747 #endif 4748 break; 4420 4749 } 4421 4750 4422 4751 // pending inval 4423 r_cleanup_write_srcid = m_upt.srcid(index); 4424 r_cleanup_write_trdid = m_upt.trdid(index); 4425 r_cleanup_write_pktid = m_upt.pktid(index); 4426 r_cleanup_write_need_rsp = m_upt.need_rsp(index); 4427 r_cleanup_index = index; 4752 r_cleanup_write_srcid = m_upt.srcid(index); 4753 r_cleanup_write_trdid = m_upt.trdid(index); 4754 r_cleanup_write_pktid = m_upt.pktid(index); 4755 r_cleanup_need_rsp = m_upt.need_rsp(index); 4756 r_cleanup_need_ack = m_upt.need_ack(index); 4757 r_cleanup_index = index; 4428 4758 4429 4759 r_cleanup_fsm = CLEANUP_UPT_DECREMENT; 4430 4760 4431 4761 #if DEBUG_MEMC_CLEANUP 4432 if(m_debug_cleanup_fsm) 4433 { 4434 std::cout 4435 << " <MEMC " << name() 4436 << " CLEANUP_UPT_LOCK> Cleanup matching pending" 4437 << " invalidate transaction on UPT:" 4438 << std::hex 4439 << " address = " << r_cleanup_nline.read() * m_words * 4 4440 << " upt_entry = " << index 4441 << std::endl; 4442 } 4443 #endif 4444 break; 4445 } 4446 4447 case CLEANUP_UPT_DECREMENT: 4448 { 4449 // decrement response counter in UPT matching entry 4762 if(m_debug) 4763 std::cout << " <MEMC " << name() 4764 << " CLEANUP_UPT_LOCK> Cleanup matching pending" 4765 << " invalidate transaction on UPT:" 4766 << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 4767 << " / upt_entry = " << index << std::endl; 4768 #endif 4769 break; 4770 } 4771 /////////////////////////// 4772 case CLEANUP_UPT_DECREMENT: // decrement response counter in UPT matching entry 4773 { 4450 4774 if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) 4451 4775 { … … 4462 4786 m_upt.decrement(r_cleanup_index.read(), count); 4463 4787 4464 // invalidation transaction finished 4465 // (all acknowledgements received) 4466 if(count == 0) 4788 if(count == 0) // multi inval transaction completed 4467 4789 { 4468 4790 r_cleanup_fsm = CLEANUP_UPT_CLEAR; 4469 4791 } 4470 // invalidation transaction not finished 4471 else 4472 { 4473 r_cleanup_fsm = CLEANUP_SEND_ACK ; 4792 else // multi inval transaction not completed 4793 { 4794 r_cleanup_fsm = CLEANUP_SEND_CLACK ; 4474 4795 } 4475 4796 4476 4797 #if DEBUG_MEMC_CLEANUP 4477 if(m_debug_cleanup_fsm) 4478 { 4479 std::cout 4480 << " <MEMC " << name() 4481 << " CLEANUP_UPT_DECREMENT> Decrement response counter in UPT:" 4798 if(m_debug) 4799 std::cout << " <MEMC " << name() << " CLEANUP_UPT_DECREMENT>" 4800 << " Decrement response counter in UPT:" 4482 4801 << " UPT_index = " << r_cleanup_index.read() 4483 << " rsp_count = " << count 4484 << std::endl; 4485 } 4486 #endif 4487 break; 4488 } 4489 4490 case CLEANUP_UPT_CLEAR: 4491 { 4492 // Clear UPT entry of finished invalidation transaction 4802 << " / rsp_count = " << count << std::endl; 4803 #endif 4804 break; 4805 } 4806 /////////////////////// 4807 case CLEANUP_UPT_CLEAR: // Clear UPT entry 4808 { 4493 4809 if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) 4494 4810 { … … 4504 4820 m_upt.clear(r_cleanup_index.read()); 4505 4821 4506 if(r_cleanup_write_need_rsp.read()) 4507 { 4508 r_cleanup_fsm = CLEANUP_WRITE_RSP; 4509 } 4510 else 4511 { 4512 r_cleanup_fsm = CLEANUP_SEND_ACK; 4513 } 4822 if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; 4823 else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK; 4824 else r_cleanup_fsm = CLEANUP_SEND_CLACK; 4514 4825 4515 4826 #if DEBUG_MEMC_CLEANUP 4516 if(m_debug_cleanup_fsm) 4517 { 4518 std::cout 4519 << " <MEMC " << name() 4520 << " CLEANUP_UPT_CLEAR> Clear entry in UPT:" 4521 << " UPT_index = " << r_cleanup_index.read() 4522 << std::endl; 4523 } 4524 #endif 4525 break; 4526 } 4527 4528 case CLEANUP_WRITE_RSP: 4529 { 4530 // response to a previous write on the direct network 4531 // wait if pending request to the TGT_RSP FSM 4827 if(m_debug) 4828 std::cout << " <MEMC " << name() 4829 << " CLEANUP_UPT_CLEAR> Clear entry in UPT:" 4830 << " UPT_index = " << r_cleanup_index.read() << std::endl; 4831 #endif 4832 break; 4833 } 4834 /////////////////////// 4835 case CLEANUP_WRITE_RSP: // response to a previous write on the direct network 4836 // wait if pending request to the TGT_RSP FSM 4837 { 4532 4838 if(r_cleanup_to_tgt_rsp_req.read()) break; 4533 4839 … … 4538 4844 r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); 4539 4845 4540 r_cleanup_fsm = CLEANUP_SEND_ ACK;4846 r_cleanup_fsm = CLEANUP_SEND_CLACK; 4541 4847 4542 4848 #if DEBUG_MEMC_CLEANUP 4543 if(m_debug_cleanup_fsm) 4544 { 4545 std::cout 4546 << " <MEMC " << name() 4547 << " CLEANUP_WRITE_RSP> Send a response to a previous" 4548 << " write request waiting for coherence transaction completion: " 4549 << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() 4550 << " / rtrdid = " << std::hex << r_cleanup_write_trdid.read() 4551 << std::endl; 4552 } 4553 #endif 4554 break; 4555 } 4556 4557 case CLEANUP_SEND_ACK: 4558 { 4559 // acknowledgement to a cleanup command 4560 // on the coherence network (request to the CC_SEND FSM). 4561 // wait if pending request to the CC_SEND FSM 4849 if(m_debug) 4850 std::cout << " <MEMC " << name() << " CLEANUP_WRITE_RSP>" 4851 << " Send a response to a previous write request: " 4852 << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() 4853 << " / rtrdid = " << r_cleanup_write_trdid.read() 4854 << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl; 4855 #endif 4856 break; 4857 } 4858 //////////////////////// 4859 case CLEANUP_CONFIG_ACK: // signals inval completion to CONFIG FSM 4860 // wait if pending request 4861 { 4862 if ( r_cleanup_to_config_ack.read() ) break; 4863 4864 r_cleanup_to_config_ack = true; 4865 r_cleanup_fsm = CLEANUP_SEND_CLACK; 4866 4867 #if DEBUG_MEMC_CLEANUP 4868 if(m_debug) 4869 std::cout << " <MEMC " << name() << " CLEANUP_CONFIG_ACK>" 4870 << " Acknowledge broacast inval completion" << std::endl; 4871 #endif 4872 break; 4873 } 4874 //////////////////////// 4875 case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command 4876 // on the coherence network (request to the CC_SEND FSM). 4877 // wait if pending request to the CC_SEND FSM 4878 { 4562 4879 if(r_cleanup_to_cc_send_req.read()) break; 4563 4880 … … 4571 4888 4572 4889 #if DEBUG_MEMC_CLEANUP 4573 if(m_debug_cleanup_fsm) 4574 { 4575 std::cout 4576 << " <MEMC " << name() 4577 << " CLEANUP_SEND_ACK> Send the response to a cleanup request:" 4578 << " srcid = " << std::dec << r_cleanup_srcid.read() 4579 << std::endl; 4580 } 4890 if(m_debug) 4891 std::cout << " <MEMC " << name() 4892 << " CLEANUP_SEND_CLACK> Send the response to a cleanup request:" 4893 << " srcid = " << std::dec << r_cleanup_srcid.read() << std::endl; 4581 4894 #endif 4582 4895 break; … … 4618 4931 4619 4932 #if DEBUG_MEMC_CAS 4620 if(m_debug _cas_fsm)4933 if(m_debug) 4621 4934 { 4622 4935 std::cout << " <MEMC " << name() << " CAS_IDLE> CAS command: " << std::hex … … 4641 4954 r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read(); 4642 4955 4643 if((r_cas_cpt.read() == 1) &&m_cmd_cas_eop_fifo.read())4956 if((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read()) 4644 4957 r_cas_wdata = m_cmd_cas_wdata_fifo.read(); 4645 4958 … … 4668 4981 4669 4982 #if DEBUG_MEMC_CAS 4670 if(m_debug _cas_fsm)4983 if(m_debug) 4671 4984 { 4672 4985 std::cout … … 4702 5015 4703 5016 #if DEBUG_MEMC_CAS 4704 if(m_debug _cas_fsm)5017 if(m_debug) 4705 5018 { 4706 5019 std::cout << " <MEMC " << name() << " CAS_DIR_LOCK> Directory acces" … … 4754 5067 4755 5068 #if DEBUG_MEMC_CAS 4756 if(m_debug _cas_fsm)5069 if(m_debug) 4757 5070 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from " 4758 5071 << " cache and store it in buffer" << std::endl; … … 4772 5085 4773 5086 // to avoid livelock, force the atomic access to fail pseudo-randomly 4774 bool forced_fail = ((r_cas_lfsr % (64) == 0) &&RANDOMIZE_CAS);5087 bool forced_fail = ((r_cas_lfsr % (64) == 0) and RANDOMIZE_CAS); 4775 5088 r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001); 4776 5089 … … 4787 5100 4788 5101 #if DEBUG_MEMC_CAS 4789 if(m_debug _cas_fsm)5102 if(m_debug) 4790 5103 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare the old" 4791 5104 << " and the new data" … … 4810 5123 r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required 4811 5124 } 4812 else if(!r_cas_to_cc_send_multi_req.read() &&5125 else if(!r_cas_to_cc_send_multi_req.read() and 4813 5126 !r_cas_to_cc_send_brdcast_req.read()) 4814 5127 { … … 4847 5160 4848 5161 #if DEBUG_MEMC_CAS 4849 if(m_debug _cas_fsm)5162 if(m_debug) 4850 5163 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:" 4851 5164 << " way = " << std::dec << way … … 4874 5187 size_t nb_copies = r_cas_count.read(); 4875 5188 4876 wok = m_upt.set(true, // it's an update transaction 4877 false, // it's not a broadcast 4878 true, // it needs a response 4879 srcid, 4880 trdid, 4881 pktid, 4882 nline, 4883 nb_copies, 4884 index); 5189 wok = m_upt.set(true, // it's an update transaction 5190 false, // it's not a broadcast 5191 true, // response required 5192 false, // no acknowledge required 5193 srcid, 5194 trdid, 5195 pktid, 5196 nline, 5197 nb_copies, 5198 index); 4885 5199 if(wok) // coherence transaction registered in UPT 4886 5200 { … … 4916 5230 4917 5231 #if DEBUG_MEMC_CAS 4918 if(m_debug _cas_fsm)5232 if(m_debug) 4919 5233 std::cout << " <MEMC " << name() 4920 5234 << " CAS_UPT_LOCK> Register multi-update transaction in UPT" … … 4931 5245 4932 5246 #if DEBUG_MEMC_CAS 4933 if(m_debug _cas_fsm)5247 if(m_debug) 4934 5248 { 4935 5249 std::cout << " <MEMC " << name() … … 4947 5261 4948 5262 #if DEBUG_MEMC_CAS 4949 if(m_debug _cas_fsm)5263 if(m_debug) 4950 5264 { 4951 5265 std::cout << " <MEMC " << name() … … 4963 5277 "VCI_MEM_CACHE ERROR : bad HEAP allocation"); 4964 5278 4965 if(!r_cas_to_cc_send_multi_req.read() &&!r_cas_to_cc_send_brdcast_req.read())5279 if(!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read()) 4966 5280 { 4967 5281 r_cas_to_cc_send_brdcast_req = false; … … 5003 5317 5004 5318 #if DEBUG_MEMC_CAS 5005 if(m_debug _cas_fsm)5319 if(m_debug) 5006 5320 { 5007 5321 std::cout << " <MEMC " << name() << " CAS_UPT_REQ> Send the first update request to CC_SEND FSM " … … 5043 5357 5044 5358 #if DEBUG_MEMC_CAS 5045 if(m_debug _cas_fsm)5359 if(m_debug) 5046 5360 { 5047 5361 std::cout << " <MEMC " << name() << " CAS_UPT_NEXT> Send the next update request to CC_SEND FSM " … … 5069 5383 r_cas_to_ixr_cmd_data[i] = r_cas_wdata.read(); 5070 5384 } 5071 else if((i == word+1) &&(r_cas_cpt.read() == 4)) // 64 bit CAS5385 else if((i == word+1) and (r_cas_cpt.read() == 4)) // 64 bit CAS 5072 5386 { 5073 5387 r_cas_to_ixr_cmd_data[i] = m_cmd_cas_wdata_fifo.read(); … … 5113 5427 // register a broadcast inval transaction in UPT 5114 5428 wok = m_upt.set(false, // it's an inval transaction 5115 true, // it's a broadcast 5116 true, // it needs a response 5117 srcid, 5118 trdid, 5119 pktid, 5120 nline, 5121 nb_copies, 5122 index); 5429 true, // it's a broadcast 5430 true, // response required 5431 false, // no acknowledge required 5432 srcid, 5433 trdid, 5434 pktid, 5435 nline, 5436 nb_copies, 5437 index); 5123 5438 5124 5439 if(wok) // UPT not full … … 5148 5463 5149 5464 #if DEBUG_MEMC_CAS 5150 if(m_debug _cas_fsm)5465 if(m_debug) 5151 5466 std::cout << " <MEMC " << name() 5152 5467 << " CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT" … … 5166 5481 case CAS_BC_DIR_INVAL: // Register the PUT transaction in TRT, and inval the DIR entry 5167 5482 { 5168 if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) &&5169 (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) &&5483 if((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and 5484 (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) and 5170 5485 (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)) 5171 5486 { … … 5204 5519 5205 5520 #if DEBUG_MEMC_CAS 5206 if(m_debug _cas_fsm)5521 if(m_debug) 5207 5522 std::cout << " <MEMC " << name() 5208 5523 << " CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry" … … 5220 5535 case CAS_BC_CC_SEND: // Request the broadcast inval to CC_SEND FSM 5221 5536 { 5222 if(!r_cas_to_cc_send_multi_req.read() &&5537 if(!r_cas_to_cc_send_multi_req.read() and 5223 5538 !r_cas_to_cc_send_brdcast_req.read()) 5224 5539 { … … 5248 5563 5249 5564 #if DEBUG_MEMC_CAS 5250 if(m_debug _cas_fsm)5565 if(m_debug) 5251 5566 std::cout << " <MEMC " << name() 5252 5567 << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex … … 5277 5592 5278 5593 #if DEBUG_MEMC_CAS 5279 if(m_debug _cas_fsm)5594 if(m_debug) 5280 5595 std::cout << " <MEMC " << name() 5281 5596 << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl; … … 5299 5614 5300 5615 #if DEBUG_MEMC_CAS 5301 if(m_debug _cas_fsm)5616 if(m_debug) 5302 5617 std::cout << " <MEMC " << name() 5303 5618 << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl; … … 5319 5634 5320 5635 #if DEBUG_MEMC_CAS 5321 if(m_debug _cas_fsm)5636 if(m_debug) 5322 5637 { 5323 5638 std::cout << " <MEMC " << name() << " CAS_MISS_TRT_LOCK> Check TRT state" … … 5329 5644 #endif 5330 5645 5331 if(hit_read || !wok ||hit_write) // missing line already requested or no space in TRT5646 if(hit_read or !wok or hit_write) // missing line already requested or no space in TRT 5332 5647 { 5333 5648 r_cas_fsm = CAS_WAIT; … … 5370 5685 5371 5686 #if DEBUG_MEMC_CAS 5372 if(m_debug _cas_fsm)5687 if(m_debug) 5373 5688 { 5374 5689 std::cout << " <MEMC " << name() << " CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex … … 5392 5707 5393 5708 #if DEBUG_MEMC_CAS 5394 if(m_debug _cas_fsm)5709 if(m_debug) 5395 5710 { 5396 5711 std::cout << " <MEMC " << name() << " CAS_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex … … 5438 5753 { 5439 5754 // XRAM_RSP FSM has highest priority 5440 if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||5755 if(m_xram_rsp_to_cc_send_inst_fifo.rok() or 5441 5756 r_xram_rsp_to_cc_send_multi_req.read()) 5442 5757 { … … 5453 5768 } 5454 5769 5455 if(m_cas_to_cc_send_inst_fifo.rok() ||5770 if(m_cas_to_cc_send_inst_fifo.rok() or 5456 5771 r_cas_to_cc_send_multi_req.read()) 5457 5772 { … … 5474 5789 } 5475 5790 5476 if(m_write_to_cc_send_inst_fifo.rok() ||5791 if(m_write_to_cc_send_inst_fifo.rok() or 5477 5792 r_write_to_cc_send_multi_req.read()) 5478 5793 { … … 5493 5808 { 5494 5809 // CAS FSM has highest priority 5495 if(m_cas_to_cc_send_inst_fifo.rok() ||5810 if(m_cas_to_cc_send_inst_fifo.rok() or 5496 5811 r_cas_to_cc_send_multi_req.read()) 5497 5812 { … … 5514 5829 } 5515 5830 5516 if(m_write_to_cc_send_inst_fifo.rok() ||5831 if(m_write_to_cc_send_inst_fifo.rok() or 5517 5832 r_write_to_cc_send_multi_req.read()) 5518 5833 { … … 5529 5844 } 5530 5845 5531 if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||5846 if(m_xram_rsp_to_cc_send_inst_fifo.rok() or 5532 5847 r_xram_rsp_to_cc_send_multi_req.read()) 5533 5848 { … … 5555 5870 } 5556 5871 5557 if(m_write_to_cc_send_inst_fifo.rok() ||5872 if(m_write_to_cc_send_inst_fifo.rok() or 5558 5873 r_write_to_cc_send_multi_req.read()) 5559 5874 { … … 5570 5885 } 5571 5886 5572 if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||5887 if(m_xram_rsp_to_cc_send_inst_fifo.rok() or 5573 5888 r_xram_rsp_to_cc_send_multi_req.read()) 5574 5889 { … … 5585 5900 } 5586 5901 5587 if(m_cas_to_cc_send_inst_fifo.rok() ||5902 if(m_cas_to_cc_send_inst_fifo.rok() or 5588 5903 r_cas_to_cc_send_multi_req.read()) 5589 5904 { … … 5604 5919 { 5605 5920 // WRITE FSM has highest priority 5606 if(m_write_to_cc_send_inst_fifo.rok() ||5921 if(m_write_to_cc_send_inst_fifo.rok() or 5607 5922 r_write_to_cc_send_multi_req.read()) 5608 5923 { … … 5619 5934 } 5620 5935 5621 if(m_xram_rsp_to_cc_send_inst_fifo.rok() ||5936 if(m_xram_rsp_to_cc_send_inst_fifo.rok() or 5622 5937 r_xram_rsp_to_cc_send_multi_req.read()) 5623 5938 { … … 5634 5949 } 5635 5950 5636 if(m_cas_to_cc_send_inst_fifo.rok() ||5951 if(m_cas_to_cc_send_inst_fifo.rok() or 5637 5952 r_cas_to_cc_send_multi_req.read()) 5638 5953 { … … 5666 5981 5667 5982 #if DEBUG_MEMC_CC_SEND 5668 if(m_debug _cc_send_fsm)5983 if(m_debug) 5669 5984 std::cout << " <MEMC " << name() 5670 5985 << " CC_SEND_CLEANUP_ACK> Cleanup Ack for srcid " … … 5705 6020 5706 6021 #if DEBUG_MEMC_CC_SEND 5707 if(m_debug _cc_send_fsm)6022 if(m_debug) 5708 6023 std::cout << " <MEMC " << name() 5709 6024 << " CC_SEND_XRAM_RSP_INVAL_NLINE> BC-Inval for line " … … 5733 6048 5734 6049 #if DEBUG_MEMC_CC_SEND 5735 if(m_debug _cc_send_fsm)6050 if(m_debug) 5736 6051 std::cout << " <MEMC " << name() 5737 6052 << " CC_SEND_XRAM_RSP_BRDCAST_NLINE> BC-Inval for line " … … 5761 6076 5762 6077 #if DEBUG_MEMC_CC_SEND 5763 if(m_debug _cc_send_fsm)6078 if(m_debug) 5764 6079 std::cout << " <MEMC " << name() 5765 6080 << " CC_SEND_WRITE_BRDCAST_NLINE> BC-Inval for line " … … 5800 6115 5801 6116 #if DEBUG_MEMC_CC_SEND 5802 if(m_debug _cc_send_fsm)6117 if(m_debug) 5803 6118 { 5804 6119 std::cout … … 5848 6163 5849 6164 #if DEBUG_MEMC_CC_SEND 5850 if(m_debug _cc_send_fsm)6165 if(m_debug) 5851 6166 { 5852 6167 std::cout … … 5892 6207 5893 6208 #if DEBUG_MEMC_CC_SEND 5894 if(m_debug_cc_send_fsm) 5895 { 5896 std::cout 5897 << " <MEMC " << name() 5898 << " CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line " 5899 << r_cas_to_cc_send_nline.read() 5900 << std::endl; 5901 } 6209 if(m_debug) 6210 std::cout << " <MEMC " << name() 6211 << " CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line " 6212 << r_cas_to_cc_send_nline.read() << std::endl; 5902 6213 #endif 5903 6214 break; … … 5951 6262 DspinDhccpParam::FROM_L1_TYPE); 5952 6263 5953 if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) ||6264 if((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or 5954 6265 (type == DspinDhccpParam::TYPE_CLEANUP_INST)) 5955 6266 { … … 5964 6275 } 5965 6276 5966 assert(false &&6277 assert(false and 5967 6278 "VCI_MEM_CACHE ERROR in CC_RECEIVE : " 5968 6279 "Illegal type in coherence request"); … … 6049 6360 r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); 6050 6361 } 6051 else if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; 6052 else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; 6362 else if(r_write_to_tgt_rsp_req) 6363 { 6364 r_tgt_rsp_fsm = TGT_RSP_WRITE; 6365 } 6366 else if(r_cas_to_tgt_rsp_req) 6367 { 6368 r_tgt_rsp_fsm = TGT_RSP_CAS ; 6369 } 6053 6370 else if(r_xram_rsp_to_tgt_rsp_req) 6054 6371 { … … 6056 6373 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6057 6374 } 6058 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6059 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6060 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 6375 else if(r_multi_ack_to_tgt_rsp_req) 6376 { 6377 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6378 } 6379 else if(r_cleanup_to_tgt_rsp_req) 6380 { 6381 r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6382 } 6383 else if(r_tgt_cmd_to_tgt_rsp_req) 6384 { 6385 r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 6386 } 6061 6387 break; 6062 6388 } … … 6185 6511 ///////////////////// 6186 6512 case TGT_RSP_TGT_CMD: // send the response after a segmentation violation 6513 // or after a config transaction 6187 6514 { 6188 6515 if ( p_vci_tgt.rspack ) … … 6192 6519 6193 6520 #if DEBUG_MEMC_TGT_RSP 6194 if( m_debug _tgt_rsp_fsm)6521 if( m_debug ) 6195 6522 { 6196 6523 std::cout 6197 6524 << " <MEMC " << name() 6198 << " TGT_RSP_TGT_CMD> Segmentation violation from TGT_CMDresponse"6525 << " TGT_RSP_TGT_CMD> Segmentation violation ior config access response" 6199 6526 << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read() 6200 6527 << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read() … … 6214 6541 6215 6542 #if DEBUG_MEMC_TGT_RSP 6216 if( m_debug _tgt_rsp_fsm)6543 if( m_debug ) 6217 6544 { 6218 6545 std::cout … … 6260 6587 6261 6588 #if DEBUG_MEMC_TGT_RSP 6262 if(m_debug _tgt_rsp_fsm)6589 if(m_debug) 6263 6590 std::cout << " <MEMC " << name() << " TGT_RSP_WRITE> Write response" 6264 6591 << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read() … … 6271 6598 break; 6272 6599 } 6273 /////////////////// 6600 ///////////////////// 6274 6601 case TGT_RSP_CLEANUP: // pas clair pour moi (AG) 6275 6602 { … … 6278 6605 6279 6606 #if DEBUG_MEMC_TGT_RSP 6280 if(m_debug _tgt_rsp_fsm)6607 if(m_debug) 6281 6608 std::cout << " <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response" 6282 6609 << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read() … … 6289 6616 break; 6290 6617 } 6291 ///////////////// /6618 ///////////////// 6292 6619 case TGT_RSP_CAS: // send one atomic word response 6293 6620 { … … 6296 6623 6297 6624 #if DEBUG_MEMC_TGT_RSP 6298 if(m_debug _tgt_rsp_fsm)6625 if(m_debug) 6299 6626 std::cout << " <MEMC " << name() << " TGT_RSP_CAS> CAS response" 6300 6627 << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read() … … 6308 6635 } 6309 6636 6310 ////////////////// /////6637 ////////////////// 6311 6638 case TGT_RSP_XRAM: // send the response after XRAM access 6312 6639 { … … 6315 6642 6316 6643 #if DEBUG_MEMC_TGT_RSP 6317 if( m_debug _tgt_rsp_fsm)6644 if( m_debug ) 6318 6645 std::cout << " <MEMC " << name() << " TGT_RSP_XRAM> Response following XRAM access" 6319 6646 << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read() … … 6351 6678 break; 6352 6679 } 6353 ////////////////// 6680 /////////////////////// 6354 6681 case TGT_RSP_MULTI_ACK: // send the write response after coherence transaction 6355 6682 { … … 6358 6685 6359 6686 #if DEBUG_MEMC_TGT_RSP 6360 if(m_debug _tgt_rsp_fsm)6687 if(m_debug) 6361 6688 std::cout << " <MEMC " << name() << " TGT_RSP_MULTI_ACK> Write response after coherence transaction" 6362 6689 << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read() … … 6374 6701 // ALLOC_UPT FSM 6375 6702 //////////////////////////////////////////////////////////////////////////////////// 6376 // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT) .6377 // with a round robin priority between three FSMs : MULTI_ACK > WRITE > XRAM_RSP > CLEANUP6378 // - The WRITE FSM initiates update transactions and sets new entry in UPT.6379 // - The XRAM_RSP FSM initiates inval transactions and setsnew entry in UPT.6703 // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT), 6704 // with a round robin priority between six FSMs, with the following order: 6705 // CONFIG > MULTI_ACK > WRITE > XRAM_RSP > CLEANUP > CAS 6706 // - The CONFIG FSM initiates an inval transaction and sets a new entry in UPT. 6380 6707 // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry. 6708 // - The WRITE FSM initiates update transaction and sets a new entry in UPT. 6709 // - The XRAM_RSP FSM initiates an inval transactions and sets a new entry in UPT. 6381 6710 // - The CLEANUP FSM decrement an entry in UPT. 6711 // - The CAS FSM does the same thing as the WRITE FSM. 6382 6712 // The resource is always allocated. 6383 6713 ///////////////////////////////////////////////////////////////////////////////////// … … 6385 6715 switch(r_alloc_upt_fsm.read()) 6386 6716 { 6387 6388 //////////////////////// 6389 case ALLOC_UPT_MULTI_ACK: 6390 if((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) && 6717 ////////////////////// 6718 case ALLOC_UPT_CONFIG: // allocated to CONFIG FSM 6719 if ( (r_config_fsm.read() != CONFIG_UPT_LOCK) and 6720 (r_config_fsm.read() != CONFIG_BC_UPT_LOCK) ) 6721 { 6722 if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 6723 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 6724 6725 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 6726 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 6727 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 6728 6729 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 6730 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 6731 6732 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 6733 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 6734 6735 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 6736 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 6737 r_alloc_upt_fsm = ALLOC_UPT_CAS; 6738 } 6739 break; 6740 6741 ///////////////////////// 6742 case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM 6743 if( (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) and 6391 6744 (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) 6392 6745 { 6393 if((r_write_fsm.read() == WRITE_UPT_LOCK) ||6746 if((r_write_fsm.read() == WRITE_UPT_LOCK) or 6394 6747 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 6395 6748 r_alloc_upt_fsm = ALLOC_UPT_WRITE; … … 6401 6754 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 6402 6755 6403 else if((r_cas_fsm.read() == CAS_UPT_LOCK) ||6756 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 6404 6757 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 6405 6758 r_alloc_upt_fsm = ALLOC_UPT_CAS; 6759 6760 else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or 6761 (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) 6762 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 6406 6763 } 6407 6764 break; 6408 6765 6409 6766 ///////////////////// 6410 case ALLOC_UPT_WRITE:6411 if((r_write_fsm.read() != WRITE_UPT_LOCK) &&6767 case ALLOC_UPT_WRITE: // allocated to WRITE FSM 6768 if((r_write_fsm.read() != WRITE_UPT_LOCK) and 6412 6769 (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) 6413 6770 { … … 6418 6775 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 6419 6776 6420 else if((r_cas_fsm.read() == CAS_UPT_LOCK) ||6777 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 6421 6778 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 6422 6779 r_alloc_upt_fsm = ALLOC_UPT_CAS; 6423 6780 6781 else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or 6782 (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) 6783 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 6784 6424 6785 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 6425 6786 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; … … 6428 6789 6429 6790 //////////////////////// 6430 case ALLOC_UPT_XRAM_RSP:6791 case ALLOC_UPT_XRAM_RSP: 6431 6792 if(r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 6432 6793 { … … 6434 6795 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 6435 6796 6436 else if((r_cas_fsm.read() == CAS_UPT_LOCK) ||6797 else if((r_cas_fsm.read() == CAS_UPT_LOCK) or 6437 6798 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 6438 6799 r_alloc_upt_fsm = ALLOC_UPT_CAS; 6439 6800 6801 else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or 6802 (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) 6803 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 6804 6440 6805 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 6441 6806 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 6442 6807 6443 else if((r_write_fsm.read() == WRITE_UPT_LOCK) ||6808 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 6444 6809 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 6445 6810 r_alloc_upt_fsm = ALLOC_UPT_WRITE; … … 6448 6813 6449 6814 ////////////////////////// 6450 case ALLOC_UPT_CLEANUP:6451 if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) &&6815 case ALLOC_UPT_CLEANUP: 6816 if((r_cleanup_fsm.read() != CLEANUP_UPT_LOCK ) and 6452 6817 (r_cleanup_fsm.read() != CLEANUP_UPT_DECREMENT)) 6453 6818 { 6454 if((r_cas_fsm.read() == CAS_UPT_LOCK) ||6819 if((r_cas_fsm.read() == CAS_UPT_LOCK) or 6455 6820 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 6456 6821 r_alloc_upt_fsm = ALLOC_UPT_CAS; 6457 6822 6823 else if((r_config_fsm.read() == CONFIG_UPT_LOCK) or 6824 (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) 6825 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 6826 6458 6827 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 6459 6828 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 6460 6829 6461 else if((r_write_fsm.read() == WRITE_UPT_LOCK) ||6830 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 6462 6831 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 6463 6832 r_alloc_upt_fsm = ALLOC_UPT_WRITE; … … 6469 6838 6470 6839 ////////////////////////// 6471 case ALLOC_UPT_CAS:6472 if((r_cas_fsm.read() != CAS_UPT_LOCK) &&6840 case ALLOC_UPT_CAS: 6841 if((r_cas_fsm.read() != CAS_UPT_LOCK) and 6473 6842 (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) 6474 6843 { 6475 if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 6844 if((r_config_fsm.read() == CONFIG_UPT_LOCK) or 6845 (r_config_fsm.read() == CONFIG_BC_UPT_LOCK)) 6846 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 6847 6848 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 6476 6849 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 6477 6850 6478 else if((r_write_fsm.read() == WRITE_UPT_LOCK) ||6851 else if((r_write_fsm.read() == WRITE_UPT_LOCK) or 6479 6852 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 6480 6853 r_alloc_upt_fsm = ALLOC_UPT_WRITE; … … 6494 6867 //////////////////////////////////////////////////////////////////////////////////// 6495 6868 // The ALLOC_DIR FSM allocates the access to the directory and 6496 // the data cache with a round robin priority between 5user FSMs :6497 // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP6869 // the data cache with a round robin priority between 6 user FSMs : 6870 // The cyclic ordering is CONFIG > READ > WRITE > CAS > CLEANUP > XRAM_RSP 6498 6871 // The ressource is always allocated. 6499 6872 ///////////////////////////////////////////////////////////////////////////////////// … … 6501 6874 switch(r_alloc_dir_fsm.read()) 6502 6875 { 6876 ///////////////////// 6503 6877 case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle. 6504 6878 // All the WAYS of a SET initialized in parallel … … 6513 6887 break; 6514 6888 6889 ////////////////////// 6890 case ALLOC_DIR_CONFIG: // allocated to CONFIG FSM 6891 if ( (r_config_fsm.read() != CONFIG_DIR_REQ) and 6892 (r_config_fsm.read() != CONFIG_DIR_ACCESS) and 6893 (r_config_fsm.read() != CONFIG_DIR_INVAL) ) 6894 { 6895 if(r_read_fsm.read() == READ_DIR_REQ) 6896 r_alloc_dir_fsm = ALLOC_DIR_READ; 6897 6898 else if(r_write_fsm.read() == WRITE_DIR_REQ) 6899 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 6900 6901 else if(r_cas_fsm.read() == CAS_DIR_REQ) 6902 r_alloc_dir_fsm = ALLOC_DIR_CAS; 6903 6904 else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 6905 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 6906 6907 else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 6908 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 6909 } 6910 break; 6911 6515 6912 //////////////////// 6516 case ALLOC_DIR_READ: 6517 if(((r_read_fsm.read() != READ_DIR_REQ) &&6518 (r_read_fsm.read() != READ_DIR_LOCK) &&6519 (r_read_fsm.read() != READ_TRT_LOCK) &&6520 (r_read_fsm.read()!= READ_HEAP_REQ))6521 ||6522 ((r_read_fsm.read() == READ_TRT_LOCK) &&6523 (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)))6524 6913 case ALLOC_DIR_READ: // allocated to READ FSM 6914 if( ((r_read_fsm.read() != READ_DIR_REQ) and 6915 (r_read_fsm.read() != READ_DIR_LOCK) and 6916 (r_read_fsm.read() != READ_TRT_LOCK) and 6917 (r_read_fsm.read() != READ_HEAP_REQ)) 6918 or 6919 ((r_read_fsm.read() == READ_TRT_LOCK) and 6920 (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)) ) 6921 { 6525 6922 if(r_write_fsm.read() == WRITE_DIR_REQ) 6526 6923 r_alloc_dir_fsm = ALLOC_DIR_WRITE; … … 6534 6931 else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 6535 6932 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 6536 } 6537 break; 6538 6539 ///////////////////// 6540 case ALLOC_DIR_WRITE: 6541 if(((r_write_fsm.read() != WRITE_DIR_REQ) && 6542 (r_write_fsm.read() != WRITE_DIR_LOCK) && 6543 (r_write_fsm.read() != WRITE_DIR_READ) && 6544 (r_write_fsm.read() != WRITE_DIR_HIT) && 6545 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) && 6546 (r_write_fsm.read() != WRITE_BC_UPT_LOCK) && 6547 (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) && 6548 (r_write_fsm.read() != WRITE_UPT_LOCK) && 6549 (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)) 6550 || 6551 ((r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) && 6552 (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)) 6553 || 6554 ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) && 6555 (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE))) 6556 { 6933 6934 else if(r_config_fsm.read() == CONFIG_DIR_REQ) 6935 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 6936 } 6937 break; 6938 6939 ///////////////////// 6940 case ALLOC_DIR_WRITE: // allocated to WRITE FSM 6941 if(((r_write_fsm.read() != WRITE_DIR_REQ) and 6942 (r_write_fsm.read() != WRITE_DIR_LOCK) and 6943 (r_write_fsm.read() != WRITE_DIR_READ) and 6944 (r_write_fsm.read() != WRITE_DIR_HIT) and 6945 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 6946 (r_write_fsm.read() != WRITE_BC_UPT_LOCK) and 6947 (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 6948 (r_write_fsm.read() != WRITE_UPT_LOCK) and 6949 (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)) 6950 or 6951 ((r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) and 6952 (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)) 6953 or 6954 ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) and 6955 (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE))) 6956 { 6557 6957 if(r_cas_fsm.read() == CAS_DIR_REQ) 6558 6958 r_alloc_dir_fsm = ALLOC_DIR_CAS; … … 6564 6964 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 6565 6965 6966 else if(r_config_fsm.read() == CONFIG_DIR_REQ) 6967 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 6968 6566 6969 else if(r_read_fsm.read() == READ_DIR_REQ) 6567 6970 r_alloc_dir_fsm = ALLOC_DIR_READ; 6568 6569 6570 6571 ////////////////////6572 case ALLOC_DIR_CAS: 6573 if(((r_cas_fsm.read() != CAS_DIR_REQ) &&6574 (r_cas_fsm.read() != CAS_DIR_LOCK) &&6575 (r_cas_fsm.read() != CAS_DIR_HIT_READ) &&6576 (r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) &&6577 (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) &&6578 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) &&6579 (r_cas_fsm.read() != CAS_BC_UPT_LOCK) &&6580 (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) &&6581 (r_cas_fsm.read() != CAS_UPT_LOCK) &&6582 6583 ||6584 ((r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) &&6585 6586 ||6587 ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) &&6588 6589 6971 } 6972 break; 6973 6974 /////////////////// 6975 case ALLOC_DIR_CAS: // allocated to CAS FSM 6976 if(((r_cas_fsm.read() != CAS_DIR_REQ) and 6977 (r_cas_fsm.read() != CAS_DIR_LOCK) and 6978 (r_cas_fsm.read() != CAS_DIR_HIT_READ) and 6979 (r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) and 6980 (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and 6981 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 6982 (r_cas_fsm.read() != CAS_BC_UPT_LOCK) and 6983 (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 6984 (r_cas_fsm.read() != CAS_UPT_LOCK) and 6985 (r_cas_fsm.read() != CAS_UPT_HEAP_LOCK)) 6986 or 6987 ((r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) and 6988 (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)) 6989 or 6990 ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) and 6991 (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS))) 6992 { 6590 6993 if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 6591 6994 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; … … 6594 6997 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 6595 6998 6999 else if(r_config_fsm.read() == CONFIG_DIR_REQ) 7000 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 7001 6596 7002 else if(r_read_fsm.read() == READ_DIR_REQ) 6597 7003 r_alloc_dir_fsm = ALLOC_DIR_READ; … … 6599 7005 else if(r_write_fsm.read() == WRITE_DIR_REQ) 6600 7006 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 6601 6602 break; 6603 6604 6605 case ALLOC_DIR_CLEANUP: 6606 if((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) &&6607 (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) &&6608 (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) &&6609 6610 7007 } 7008 break; 7009 7010 /////////////////////// 7011 case ALLOC_DIR_CLEANUP: // allocated to CLEANUP FSM 7012 if((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and 7013 (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and 7014 (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and 7015 (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK)) 7016 { 6611 7017 if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 6612 7018 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 6613 7019 7020 else if(r_config_fsm.read() == CONFIG_DIR_REQ) 7021 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 7022 6614 7023 else if(r_read_fsm.read() == READ_DIR_REQ) 6615 7024 r_alloc_dir_fsm = ALLOC_DIR_READ; … … 6620 7029 else if(r_cas_fsm.read() == CAS_DIR_REQ) 6621 7030 r_alloc_dir_fsm = ALLOC_DIR_CAS; 6622 } 6623 break; 6624 6625 //////////////////////// 6626 case ALLOC_DIR_XRAM_RSP: 6627 if((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) && 6628 (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) && 6629 (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) 6630 { 6631 if(r_read_fsm.read() == READ_DIR_REQ) 7031 } 7032 break; 7033 7034 //////////////////////// 7035 case ALLOC_DIR_XRAM_RSP: // allocated to XRAM_RSP FSM 7036 if( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and 7037 (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and 7038 (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) 7039 { 7040 if(r_config_fsm.read() == CONFIG_DIR_REQ) 7041 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 7042 7043 else if(r_read_fsm.read() == READ_DIR_REQ) 6632 7044 r_alloc_dir_fsm = ALLOC_DIR_READ; 6633 7045 … … 6640 7052 else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 6641 7053 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 6642 6643 7054 } 7055 break; 6644 7056 6645 7057 } // end switch alloc_dir_fsm … … 6660 7072 if(r_read_fsm.read() != READ_TRT_LOCK) 6661 7073 { 6662 if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||7074 if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 6663 7075 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 6664 7076 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 6665 7077 6666 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||7078 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 6667 7079 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 6668 7080 r_alloc_trt_fsm = ALLOC_TRT_CAS; 6669 7081 6670 else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) &&7082 else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 6671 7083 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 6672 7084 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 6673 7085 6674 else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||7086 else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 6675 7087 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 6676 7088 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; … … 6680 7092 ///////////////////// 6681 7093 case ALLOC_TRT_WRITE: 6682 if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) &&6683 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) &&7094 if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 7095 (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and 6684 7096 (r_write_fsm.read() != WRITE_BC_UPT_LOCK)) 6685 7097 { 6686 if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||7098 if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 6687 7099 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 6688 7100 r_alloc_trt_fsm = ALLOC_TRT_CAS; 6689 7101 6690 else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) &&7102 else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 6691 7103 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 6692 7104 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 6693 7105 6694 else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||7106 else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 6695 7107 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 6696 7108 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; … … 6703 7115 //////////////////// 6704 7116 case ALLOC_TRT_CAS: 6705 if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) &&6706 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) &&7117 if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 7118 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 6707 7119 (r_cas_fsm.read() != CAS_BC_UPT_LOCK)) 6708 7120 { 6709 if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) &&7121 if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 6710 7122 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 6711 7123 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 6712 7124 6713 else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||7125 else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 6714 7126 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 6715 7127 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; … … 6718 7130 r_alloc_trt_fsm = ALLOC_TRT_READ; 6719 7131 6720 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||7132 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 6721 7133 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 6722 7134 r_alloc_trt_fsm = ALLOC_TRT_WRITE; … … 6726 7138 //////////////////////// 6727 7139 case ALLOC_TRT_XRAM_RSP: 6728 if(((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) ||6729 (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) &&6730 (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) &&6731 (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) &&7140 if(((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) or 7141 (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and 7142 (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and 7143 (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) and 6732 7144 (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) 6733 7145 { 6734 if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||7146 if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 6735 7147 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 6736 7148 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; … … 6739 7151 r_alloc_trt_fsm = ALLOC_TRT_READ; 6740 7152 6741 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||7153 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 6742 7154 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 6743 7155 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 6744 7156 6745 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||7157 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 6746 7158 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 6747 7159 r_alloc_trt_fsm = ALLOC_TRT_CAS; … … 6751 7163 //////////////////////// 6752 7164 case ALLOC_TRT_IXR_RSP: 6753 if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) &&7165 if((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and 6754 7166 (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) 6755 7167 { … … 6757 7169 r_alloc_trt_fsm = ALLOC_TRT_READ; 6758 7170 6759 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) ||7171 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 6760 7172 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 6761 7173 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 6762 7174 6763 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) ||7175 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 6764 7176 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 6765 7177 r_alloc_trt_fsm = ALLOC_TRT_CAS; 6766 7178 6767 else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) &&7179 else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 6768 7180 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 6769 7181 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; … … 6800 7212 //////////////////// 6801 7213 case ALLOC_HEAP_READ: 6802 if((r_read_fsm.read() != READ_HEAP_REQ) &&6803 (r_read_fsm.read() != READ_HEAP_LOCK) &&7214 if((r_read_fsm.read() != READ_HEAP_REQ) and 7215 (r_read_fsm.read() != READ_HEAP_LOCK) and 6804 7216 (r_read_fsm.read() != READ_HEAP_ERASE)) 6805 7217 { … … 6820 7232 ///////////////////// 6821 7233 case ALLOC_HEAP_WRITE: 6822 if((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) &&6823 (r_write_fsm.read() != WRITE_UPT_REQ) &&7234 if((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) and 7235 (r_write_fsm.read() != WRITE_UPT_REQ) and 6824 7236 (r_write_fsm.read() != WRITE_UPT_NEXT)) 6825 7237 { … … 6840 7252 //////////////////// 6841 7253 case ALLOC_HEAP_CAS: 6842 if((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) &&6843 (r_cas_fsm.read() != CAS_UPT_REQ) &&7254 if((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) and 7255 (r_cas_fsm.read() != CAS_UPT_REQ) and 6844 7256 (r_cas_fsm.read() != CAS_UPT_NEXT)) 6845 7257 { … … 6860 7272 /////////////////////// 6861 7273 case ALLOC_HEAP_CLEANUP: 6862 if((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) &&6863 (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) &&6864 (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) &&7274 if((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and 7275 (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and 7276 (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) and 6865 7277 (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN)) 6866 7278 { … … 6881 7293 //////////////////////// 6882 7294 case ALLOC_HEAP_XRAM_RSP: 6883 if((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) &&7295 if((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and 6884 7296 (r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE)) 6885 7297 { … … 6901 7313 } // end switch alloc_heap_fsm 6902 7314 6903 6904 //////////////////////////////////////////////////////////////////////////////////// 7315 ///////////////////////////////////////////////////////////////////// 6905 7316 // TGT_CMD to READ FIFO 6906 //////////////////////////////////////////////////////////////////////////////////// 6907 6908 if(cmd_read_fifo_put) 6909 { 6910 if(cmd_read_fifo_get) 6911 { 6912 m_cmd_read_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read())); 6913 m_cmd_read_length_fifo.put_and_get(p_vci_tgt.plen.read() >>2); 6914 m_cmd_read_srcid_fifo.put_and_get(p_vci_tgt.srcid.read()); 6915 m_cmd_read_trdid_fifo.put_and_get(p_vci_tgt.trdid.read()); 6916 m_cmd_read_pktid_fifo.put_and_get(p_vci_tgt.pktid.read()); 6917 } 6918 else 6919 { 6920 m_cmd_read_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read())); 6921 m_cmd_read_length_fifo.simple_put(p_vci_tgt.plen.read() >>2); 6922 m_cmd_read_srcid_fifo.simple_put(p_vci_tgt.srcid.read()); 6923 m_cmd_read_trdid_fifo.simple_put(p_vci_tgt.trdid.read()); 6924 m_cmd_read_pktid_fifo.simple_put(p_vci_tgt.pktid.read()); 6925 } 6926 } 6927 else 6928 { 6929 if(cmd_read_fifo_get) 6930 { 6931 m_cmd_read_addr_fifo.simple_get(); 6932 m_cmd_read_length_fifo.simple_get(); 6933 m_cmd_read_srcid_fifo.simple_get(); 6934 m_cmd_read_trdid_fifo.simple_get(); 6935 m_cmd_read_pktid_fifo.simple_get(); 6936 } 6937 } 7317 ///////////////////////////////////////////////////////////////////// 7318 7319 m_cmd_read_addr_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 7320 p_vci_tgt.address.read() ); 7321 m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 7322 p_vci_tgt.plen.read()>>2 ); 7323 m_cmd_read_srcid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 7324 p_vci_tgt.srcid.read() ); 7325 m_cmd_read_trdid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 7326 p_vci_tgt.trdid.read() ); 7327 m_cmd_read_pktid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 7328 p_vci_tgt.pktid.read() ); 7329 6938 7330 ///////////////////////////////////////////////////////////////////// 6939 7331 // TGT_CMD to WRITE FIFO … … 7264 7656 //////////////////////////////////////////////////// 7265 7657 7266 if(((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&7267 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) ||7658 if(((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and 7659 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) or 7268 7660 (r_ixr_rsp_fsm.read() == IXR_RSP_ACK)) 7269 7661 … … 7333 7725 p_vci_tgt.rtrdid = r_tgt_cmd_to_tgt_rsp_trdid.read(); 7334 7726 p_vci_tgt.rpktid = r_tgt_cmd_to_tgt_rsp_pktid.read(); 7335 p_vci_tgt.rerror = 0x1;7727 p_vci_tgt.rerror = r_tgt_cmd_to_tgt_rsp_error.read(); 7336 7728 p_vci_tgt.reop = true; 7337 7729 … … 7368 7760 case TGT_RSP_WRITE: 7369 7761 p_vci_tgt.rspval = true; 7370 if(((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) &&r_write_to_tgt_rsp_sc_fail.read())7762 if(((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) and r_write_to_tgt_rsp_sc_fail.read()) 7371 7763 p_vci_tgt.rdata = 1; 7372 7764 else
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