- Timestamp:
- Jul 17, 2013, 2:42:13 PM (12 years ago)
- Location:
- branches/v5/modules/vci_cc_vcache_wrapper
- Files:
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- 2 edited
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. (modified) (1 prop)
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caba/source/include/vci_cc_vcache_wrapper.h (modified) (21 diffs)
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branches/v5/modules/vci_cc_vcache_wrapper
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/trunk/modules/vci_cc_vcache_wrapper merged eligible
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branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r351 r443 55 55 56 56 //////////////////////////////////////////// 57 template<typename vci_param, typename iss_t> 57 template<typename vci_param, 58 size_t dspin_in_width, 59 size_t dspin_out_width, 60 typename iss_t> 58 61 class VciCcVCacheWrapper 59 62 //////////////////////////////////////////// 60 63 : public soclib::caba::BaseModule 61 64 { 62 typedef uint32_t vaddr_t; 63 typedef uint32_t tag_t; 64 typedef uint32_t type_t; 65 typedef typename iss_t::DataOperationType data_op_t; 66 67 typedef typename vci_param::addr_t paddr_t; 68 typedef typename vci_param::data_t vci_data_t; 69 typedef typename vci_param::be_t vci_be_t; 70 typedef typename vci_param::srcid_t vci_srcid_t; 71 typedef typename vci_param::trdid_t vci_trdid_t; 72 typedef typename vci_param::pktid_t vci_pktid_t; 73 typedef typename vci_param::plen_t vci_plen_t; 74 75 enum icache_fsm_state_e { 65 66 typedef typename vci_param::fast_addr_t paddr_t; 67 68 enum icache_fsm_state_e 69 { 76 70 ICACHE_IDLE, 77 71 // handling XTN processor requests … … 101 95 }; 102 96 103 enum dcache_fsm_state_e { 97 enum dcache_fsm_state_e 98 { 104 99 DCACHE_IDLE, 105 100 // handling itlb & dtlb miss … … 151 146 }; 152 147 153 enum cmd_fsm_state_e { 148 enum cmd_fsm_state_e 149 { 154 150 CMD_IDLE, 155 151 CMD_INS_MISS, … … 163 159 }; 164 160 165 enum rsp_fsm_state_e { 161 enum rsp_fsm_state_e 162 { 166 163 RSP_IDLE, 167 164 RSP_INS_MISS, … … 173 170 }; 174 171 175 enum cc_receive_fsm_state_e { 172 enum cc_receive_fsm_state_e 173 { 176 174 CC_RECEIVE_IDLE, 177 175 CC_RECEIVE_CLACK, … … 185 183 }; 186 184 187 enum cc_send_fsm_state_e { 185 enum cc_send_fsm_state_e 186 { 188 187 CC_SEND_IDLE, 189 188 CC_SEND_CLEANUP_1, … … 221 220 222 221 // cc_send_type 223 typedef enum { 222 typedef enum 223 { 224 224 CC_TYPE_CLEANUP, 225 225 CC_TYPE_MULTI_ACK, … … 227 227 228 228 // cc_receive_type 229 typedef enum { 229 typedef enum 230 { 230 231 CC_TYPE_CLACK, 231 232 CC_TYPE_BRDCAST, … … 235 236 236 237 // TLB Mode : ITLB / DTLB / ICACHE / DCACHE 237 enum { 238 enum 239 { 238 240 INS_TLB_MASK = 0x8, 239 241 DATA_TLB_MASK = 0x4, … … 283 285 284 286 public: 285 sc_in<bool> p_clk;286 sc_in<bool> p_resetn;287 sc_in<bool> p_irq[iss_t::n_irq];288 soclib::caba::VciInitiator<vci_param> p_vci;289 soclib::caba::DspinInput < 40>p_dspin_in;290 soclib::caba::DspinOutput< 33>p_dspin_out;287 sc_in<bool> p_clk; 288 sc_in<bool> p_resetn; 289 sc_in<bool> p_irq[iss_t::n_irq]; 290 soclib::caba::VciInitiator<vci_param> p_vci; 291 soclib::caba::DspinInput <dspin_in_width> p_dspin_in; 292 soclib::caba::DspinOutput<dspin_out_width> p_dspin_out; 291 293 292 294 private: … … 295 297 soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table; 296 298 297 const vci_srcid_tm_srcid;299 const size_t m_srcid; 298 300 const size_t m_cc_global_id; 299 301 const size_t m_nline_width; … … 327 329 328 330 ///////////////////////////////////////////// 329 // debug variables (for each FSM)331 // debug variables 330 332 ///////////////////////////////////////////// 331 bool m_debug_previous_hit; 332 bool m_idebug_previous_hit; 333 bool m_debug_dcache_fsm; 334 bool m_debug_icache_fsm; 335 bool m_debug_inval_itlb_fsm; 336 bool m_debug_inval_dtlb_fsm; 333 bool m_debug_previous_i_hit; 334 bool m_debug_previous_d_hit; 335 bool m_debug_activated; 337 336 338 337 /////////////////////////////// … … 401 400 sc_signal<uint32_t> r_dcache_save_vaddr; // virtual address (from proc) 402 401 sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc) 403 sc_signal< vci_be_t> r_dcache_save_be; // byte enable (from proc)402 sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc) 404 403 sc_signal<paddr_t> r_dcache_save_paddr; // physical address 405 404 sc_signal<bool> r_dcache_save_cacheable; // address cacheable … … 416 415 sc_signal<bool> r_dcache_vci_miss_req; // read miss request 417 416 sc_signal<bool> r_dcache_vci_unc_req; // uncacheable read request 418 sc_signal< bool>r_dcache_vci_unc_be; // uncacheable read byte enable417 sc_signal<uint32_t> r_dcache_vci_unc_be; // uncacheable read byte enable 419 418 sc_signal<bool> r_dcache_vci_cas_req; // atomic write request CAS 420 419 sc_signal<uint32_t> r_dcache_vci_cas_old; // previous data value for a CAS … … 422 421 sc_signal<bool> r_dcache_vci_ll_req; // atomic read request LL 423 422 sc_signal<bool> r_dcache_vci_sc_req; // atomic write request SC 424 sc_signal< vci_data_t>r_dcache_vci_sc_data; // SC data (command)423 sc_signal<uint32_t> r_dcache_vci_sc_data; // SC data (command) 425 424 426 425 // register used for XTN inval … … 479 478 480 479 // dcache directory extension 481 bool *r_dcache_in_tlb; // copy exist in dtlb or itlb 482 bool *r_dcache_contains_ptd; // cache line contains a PTD 480 bool *r_dcache_in_tlb; // copy exist in dtlb or itlb 481 bool *r_dcache_contains_ptd; // cache line contains a PTD 482 483 // Physical address extension for data access 484 sc_signal<uint32_t> r_dcache_paddr_ext; // CP2 register (if vci_address > 32) 483 485 484 486 /////////////////////////////////// … … 486 488 /////////////////////////////////// 487 489 sc_signal<int> r_vci_cmd_fsm; 488 sc_signal<size_t> r_vci_cmd_min; // used for write bursts489 sc_signal<size_t> r_vci_cmd_max; // used for write bursts490 sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts491 sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss490 sc_signal<size_t> r_vci_cmd_min; // used for write bursts 491 sc_signal<size_t> r_vci_cmd_max; // used for write bursts 492 sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts 493 sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss 492 494 493 495 /////////////////////////////////// … … 498 500 sc_signal<bool> r_vci_rsp_ins_error; 499 501 sc_signal<bool> r_vci_rsp_data_error; 500 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM501 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM502 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM 503 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM 502 504 503 505 /////////////////////////////////// 504 506 // CC_SEND FSM REGISTER 505 507 /////////////////////////////////// 506 sc_signal<int> r_cc_send_fsm; // state register507 sc_signal<bool> r_cc_send_last_client; // round robin flip-flop :0 dcache / 1 icache508 sc_signal<int> r_cc_send_fsm; // state register 509 sc_signal<bool> r_cc_send_last_client; // 0 dcache / 1 icache 508 510 509 511 /////////////////////////////////// 510 512 // CC_RECEIVE FSM REGISTER 511 513 /////////////////////////////////// 512 sc_signal<int> r_cc_receive_fsm; // state register513 sc_signal<bool> r_cc_receive_data_ins; // request concerning: 0 dcache / 1 icache514 515 // communication cc updt FIFObetween CC_RECEIVE FSM and ICACHE/DCACHE FSM516 sc_signal<size_t> r_cc_receive_word_idx; // word index514 sc_signal<int> r_cc_receive_fsm; // state register 515 sc_signal<bool> r_cc_receive_data_ins; // request to : 0 dcache / 1 icache 516 517 // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM 518 sc_signal<size_t> r_cc_receive_word_idx; // word index 517 519 GenericFifo<uint32_t> r_cc_receive_updt_fifo_be; 518 520 GenericFifo<uint32_t> r_cc_receive_updt_fifo_data; … … 520 522 521 523 // communication between CC_RECEIVE FSM and ICACHE FSM 522 sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request523 sc_signal<cc_receive_t> r_cc_receive_icache_type; // cc_receive type of coherencerequest524 sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way525 sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set524 sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request 525 sc_signal<cc_receive_t> r_cc_receive_icache_type; // cc_receive type of request 526 sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way 527 sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set 526 528 sc_signal<size_t> r_cc_receive_icache_updt_tab_idx; // cc_receive update table index 527 sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address529 sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address 528 530 529 531 // communication between CC_RECEIVE FSM and DCACHE FSM 530 sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request531 sc_signal<cc_receive_t> r_cc_receive_dcache_type; // cc_receive type of coherencerequest532 sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way533 sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set532 sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request 533 sc_signal<cc_receive_t> r_cc_receive_dcache_type; // cc_receive type of request 534 sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way 535 sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set 534 536 sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index 535 sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address537 sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address 536 538 537 539 ////////////////////////////////////////////////////////////////// … … 675 677 676 678 uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen 679 bool m_monitor_ok; // used to debug cache output 680 uint32_t m_monitor_base; 681 uint32_t m_monitor_length; 677 682 678 683 protected: … … 711 716 void print_trace(size_t mode = 0); 712 717 void cache_monitor(paddr_t addr); 713 inline void iss_set_debug_mask(uint v) { 714 r_iss.set_debug_mask(v); 718 void start_monitor(paddr_t,paddr_t); 719 void stop_monitor(); 720 inline void iss_set_debug_mask(uint v) 721 { 722 r_iss.set_debug_mask(v); 715 723 } 716 724
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