Changeset 446 for branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include

Timestamp:

Jul 18, 2013, 11:37:47 AM (11 years ago)

Author:

cfuguet

Message:

Modifications in vci_cc_vcache_wrapper:

• Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.

• Adding third port for the clack coherence network.

• Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

File:

• branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (modified) (6 diffs)

branches/v5/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

@@ -89 +89 @@
         // handling coherence requests
         ICACHE_CC_CHECK,
+        ICACHE_CC_UPDT,
         ICACHE_CC_INVAL,
-        ICACHE_CC_UPDT,
-        ICACHE_CC_BROADCAST,
         ICACHE_CC_SEND_WAIT,
     };
@@ -138 +137 @@
         // handling coherence requests
         DCACHE_CC_CHECK,
+        DCACHE_CC_UPDT,
         DCACHE_CC_INVAL,
-        DCACHE_CC_UPDT,
-        DCACHE_CC_BROADCAST,
         DCACHE_CC_SEND_WAIT,
         // handling TLB inval (after a coherence or XTN request)
@@ -285 +283 @@
 
 public:
-    sc_in<bool>                                 p_clk;
-    sc_in<bool>                                 p_resetn;
-    sc_in<bool>                                 p_irq[iss_t::n_irq];
-    soclib::caba::VciInitiator<vci_param>       p_vci;
-    soclib::caba::DspinInput <dspin_in_width>   p_dspin_in;
-    soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
+    sc_in<bool>                                p_clk;
+    sc_in<bool>                                p_resetn;
+    sc_in<bool>                                p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>      p_vci;
+    soclib::caba::DspinInput<dspin_in_width>   p_dspin_m2p;
+    soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
+    soclib::caba::DspinInput<dspin_in_width>   p_dspin_clack;
 
 private:
@@ -371 +370 @@
     sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
 
+    // coherence clack handling
+    sc_signal<bool>         r_icache_clack_req;         // clack request
+    sc_signal<size_t>       r_icache_clack_way;             // clack way
+    sc_signal<size_t>       r_icache_clack_set;             // clack set
+
     // icache flush handling
     sc_signal<size_t>       r_icache_flush_count;           // slot counter used for cache flush
@@ -444 +448 @@
     sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
 
+    // coherence clack handling
+    sc_signal<bool>         r_dcache_clack_req;         // clack request
+    sc_signal<size_t>       r_dcache_clack_way;             // clack way
+    sc_signal<size_t>       r_dcache_clack_set;             // clack set
+
     // dcache flush handling
     sc_signal<size_t>       r_dcache_flush_count;           // slot counter used for cache flush
@@ -537 +546 @@
     sc_signal<paddr_t>      r_cc_receive_dcache_nline;      // cache line physical address
 
+    ///////////////////////////////////
+    //  DSPIN CLACK INTERFACE REGISTER
+    ///////////////////////////////////
+    sc_signal<bool>         r_dspin_clack_req;
+    sc_signal<uint64_t>     r_dspin_clack_flit;
+    
     //////////////////////////////////////////////////////////////////
     // processor, write buffer, caches , TLBs