- Timestamp:
- Jul 19, 2013, 2:34:03 PM (11 years ago)
- Location:
- branches/ODCCP/modules/vci_cc_vcache_wrapper
- Files:
-
- 1 edited
- 1 copied
-
. (copied) (copied from trunk/modules/vci_cc_vcache_wrapper)
-
caba/source/include/vci_cc_vcache_wrapper.h (modified) (14 diffs)
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branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r432 r460 117 117 DCACHE_XTN_IT_INVAL, 118 118 DCACHE_XTN_DC_FLUSH, 119 DCACHE_XTN_DC_FLUSH_DATA, 119 120 DCACHE_XTN_DC_FLUSH_GO, 120 121 DCACHE_XTN_DC_INVAL_VA, … … 122 123 DCACHE_XTN_DC_INVAL_END, 123 124 DCACHE_XTN_DC_INVAL_GO, 125 DCACHE_XTN_DC_INVAL_DATA, 124 126 DCACHE_XTN_DT_INVAL, 125 127 //handling dirty bit update … … 129 131 DCACHE_MISS_SELECT, 130 132 DCACHE_MISS_CLEAN, 133 DCACHE_MISS_DATA, 131 134 DCACHE_MISS_WAIT, 132 135 DCACHE_MISS_DATA_UPDT, … … 138 141 // handling coherence requests 139 142 DCACHE_CC_CHECK, 143 DCACHE_CC_INVAL_DATA, 140 144 DCACHE_CC_INVAL, 141 145 DCACHE_CC_UPDT, … … 188 192 CC_SEND_CLEANUP_1, 189 193 CC_SEND_CLEANUP_2, 194 CC_SEND_CLEANUP_DATA_UPDT, 190 195 CC_SEND_MULTI_ACK, 191 196 }; … … 194 199 enum transaction_type_e 195 200 { 196 // b3 unused201 // b3 ODCCP/RWT : COHERENT/NO COHERENT 197 202 // b2 READ / NOT READ 198 203 // if READ … … 202 207 // b1 accÚs table llsc type SW / other 203 208 // b2 WRITE/CAS/LL/SC 204 TYPE_READ_DATA_UNC = 0x0, 205 TYPE_READ_DATA_MISS = 0x1, 206 TYPE_READ_INS_UNC = 0x2, 207 TYPE_READ_INS_MISS = 0x3, 208 TYPE_WRITE = 0x4, 209 TYPE_CAS = 0x5, 210 TYPE_LL = 0x6, 211 TYPE_SC = 0x7 209 TYPE_READ_DATA_UNC = 0x0, 210 TYPE_READ_DATA_MISS = 0x1, 211 TYPE_READ_INS_UNC = 0x2, 212 TYPE_READ_INS_MISS = 0x3, 213 TYPE_WRITE = 0x4, 214 TYPE_CAS = 0x5, 215 TYPE_LL = 0x6, 216 TYPE_SC = 0x7, 217 TYPE_READ_DATA_MISS_NO_COHERENT = 0x9 212 218 }; 213 219 … … 283 289 TYPE_INS_MISS = 0x3, 284 290 }; 291 292 //////////////////MODIFIED//////////////// 293 enum content_line_cache_status_e 294 { 295 LINE_CACHE_DATA_NOT_DIRTY, 296 LINE_CACHE_DATA_DIRTY, 297 LINE_CACHE_IN_TLB, 298 LINE_CACHE_CONTAINS_PTD, 299 }; 300 ////////////////////////////////////////// 285 301 286 302 public: … … 384 400 // communication between ICACHE FSM and CC_SEND FSM 385 401 sc_signal<bool> r_icache_cc_send_req; // ICACHE cc_send request 386 sc_signal< cc_send_t>r_icache_cc_send_type; // ICACHE cc_send request type402 sc_signal<int> r_icache_cc_send_type; // ICACHE cc_send request type 387 403 sc_signal<paddr_t> r_icache_cc_send_nline; // ICACHE cc_send nline 388 404 sc_signal<size_t> r_icache_cc_send_way; // ICACHE cc_send way … … 472 488 // communication between DCACHE FSM and CC_SEND FSM 473 489 sc_signal<bool> r_dcache_cc_send_req; // DCACHE cc_send request 474 sc_signal< cc_send_t>r_dcache_cc_send_type; // DCACHE cc_send request type490 sc_signal<int> r_dcache_cc_send_type; // DCACHE cc_send request type 475 491 sc_signal<paddr_t> r_dcache_cc_send_nline; // DCACHE cc_send nline 476 492 sc_signal<size_t> r_dcache_cc_send_way; // DCACHE cc_send way 477 493 sc_signal<size_t> r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index 478 494 495 // special registers for ODCCP/RWT 496 sc_signal<bool> r_dcache_cc_cleanup_updt_data; // Register for cleanup with data (wb updt) 497 sc_signal<bool> r_dcache_cleanup_ncc; // Register for cleanup no coherent 498 sc_signal<bool> r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode 499 sc_signal<bool> r_dcache_line_no_coherence; // Register for line current in no coherence mode 500 sc_signal<bool> r_dcache_miss_no_coherent; // Register for miss on NCC line 501 sc_signal<bool> r_vci_rsp_read_data_miss_no_coherent; // Read miss rsp on line NCC 502 sc_signal<uint32_t> r_cc_send_cpt_word; 503 504 sc_signal<uint32_t> r_dcache_miss_data_cpt; // Cpt a word to read for sending Cleanup with data (MISS STATE) 505 sc_signal<paddr_t> r_dcache_miss_data_addr; // Addr for read word for sending Cleanup with data (MISS STATE) 506 507 sc_signal<int> r_dcache_xtn_state; 508 sc_signal<paddr_t> r_dcache_xtn_data_addr; // Cpt a word to read for sending Cleanup with data (XTN DC INVAL STATE) 509 sc_signal<uint32_t> r_dcache_xtn_data_cpt; // Addr for read word for sending Cleanup with data (XTN DC INVAL STATE) 510 511 sc_signal<paddr_t> r_dcache_cc_inval_addr; // Cpt a word to read for sending Cleanup with data (CC INVAL STATE) 512 sc_signal<uint32_t> r_dcache_cc_inval_data_cpt; // Addr for read word for sending Cleanup with data (CC INVAL STATE) 513 sc_signal<int> r_dcache_cc_state; 514 515 sc_signal<paddr_t> r_dcache_xtn_flush_addr_data; // Cpt a word to read for sending Cleanup with data (XTN DC FLUSH STATE) 516 sc_signal<uint32_t> r_dcache_xtn_flush_data_cpt; // Addr for read word for sending Cleanup with data (XTN DC FLUSH STATE) 517 518 /*STATS DIRTY*/ 519 bool *dirty_stats; 520 uint32_t m_cpt_words_dirty; // total number of words dirty when we send a cleanup with data 521 522 ////////////// 523 GenericFifo<uint32_t> r_cc_send_data_fifo; // Fifo for save data value (before sending cleanup with data) 479 524 // dcache directory extension 480 bool *r_dcache_in_tlb; // copy exist in dtlb or itlb 481 bool *r_dcache_contains_ptd; // cache line contains a PTD 525 ///////////////////////////MODIFIED/////////////////////////////////////////////////// 526 //bool *r_dcache_in_tlb; // copy exist in dtlb or itlb 527 //bool *r_dcache_contains_ptd; // cache line contains a PTD 528 int *r_dcache_content_state; // content state of one cache line 529 ////////////////////////////////////////////////////////////////////////////////////// 482 530 483 531 // Physical address extension for data access … … 502 550 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM 503 551 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM 552 504 553 505 554 /////////////////////////////////// … … 523 572 // communication between CC_RECEIVE FSM and ICACHE FSM 524 573 sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request 525 sc_signal< cc_receive_t>r_cc_receive_icache_type; // cc_receive type of request574 sc_signal<int> r_cc_receive_icache_type; // cc_receive type of request 526 575 sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way 527 576 sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set … … 531 580 // communication between CC_RECEIVE FSM and DCACHE FSM 532 581 sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request 533 sc_signal< cc_receive_t>r_cc_receive_dcache_type; // cc_receive type of request582 sc_signal<int> r_cc_receive_dcache_type; // cc_receive type of request 534 583 sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way 535 584 sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set … … 576 625 uint32_t m_cpt_data_read; // total number of read data 577 626 uint32_t m_cpt_data_write; // total number of write data 627 uint32_t m_cpt_data_write_back; // total number of write NCC 628 uint32_t m_cpt_data_cleanup; // total number of flits cleanup data 629 uint32_t m_cpt_data_cleanup_dirty; // total number of cleanup data dirty 630 uint32_t m_cpt_data_sc; 631 uint32_t m_cpt_data_write_miss_ncc; // total number of write NCC miss 578 632 uint32_t m_cpt_data_miss; // number of read miss 579 633 uint32_t m_cpt_ins_miss; // number of instruction miss
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