Changeset 479 for branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include

Timestamp:

Jul 29, 2013, 11:31:38 AM (11 years ago)

Author:

devigne

Message:

Merge with the lastest version of Trunk
Modification in vci_mem_cache : Using TRT's wdata field for
put request to ixr_cmd (just for INCLUSIVE mode)

Location:

branches/ODCCP/modules/vci_cc_vcache_wrapper

Files:

• . (modified) (1 prop)
• caba/source/include/vci_cc_vcache_wrapper.h (modified) (7 diffs)

branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

@@ -89 +89 @@
         // handling coherence requests
         ICACHE_CC_CHECK,
+        ICACHE_CC_UPDT,
         ICACHE_CC_INVAL,
-        ICACHE_CC_UPDT,
-        ICACHE_CC_BROADCAST,
-        ICACHE_CC_SEND_WAIT,
     };
 
@@ -141 +139 @@
         // handling coherence requests
         DCACHE_CC_CHECK,
+        DCACHE_CC_UPDT,
+        DCACHE_CC_INVAL,
         DCACHE_CC_INVAL_DATA,
-        DCACHE_CC_INVAL,
-        DCACHE_CC_UPDT,
-        DCACHE_CC_BROADCAST,
-        DCACHE_CC_SEND_WAIT,
         // handling TLB inval (after a coherence or XTN request)
         DCACHE_INVAL_TLB_SCAN,
@@ -177 +173 @@
     {
         CC_RECEIVE_IDLE,
-        CC_RECEIVE_CLACK,
         CC_RECEIVE_BRDCAST_HEADER,
         CC_RECEIVE_BRDCAST_NLINE,
-        CC_RECEIVE_INVAL_HEADER,
-        CC_RECEIVE_INVAL_NLINE,
-        CC_RECEIVE_UPDT_HEADER,
-        CC_RECEIVE_UPDT_NLINE,
-        CC_RECEIVE_UPDT_DATA,
+        CC_RECEIVE_INS_INVAL_HEADER,
+        CC_RECEIVE_INS_INVAL_NLINE,
+        CC_RECEIVE_INS_UPDT_HEADER,
+        CC_RECEIVE_INS_UPDT_NLINE,
+        CC_RECEIVE_INS_UPDT_DATA,
+        CC_RECEIVE_DATA_INVAL_HEADER,
+        CC_RECEIVE_DATA_INVAL_NLINE,
+        CC_RECEIVE_DATA_UPDT_HEADER,
+        CC_RECEIVE_DATA_UPDT_NLINE,
+        CC_RECEIVE_DATA_UPDT_DATA,
     };
 
@@ -301 +301 @@
 
 public:
-    sc_in<bool>                                 p_clk;
-    sc_in<bool>                                 p_resetn;
-    sc_in<bool>                                 p_irq[iss_t::n_irq];
-    soclib::caba::VciInitiator<vci_param>       p_vci;
-    soclib::caba::DspinInput <dspin_in_width>   p_dspin_in;
-    soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
+    sc_in<bool>                                p_clk;
+    sc_in<bool>                                p_resetn;
+    sc_in<bool>                                p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>      p_vci;
+    soclib::caba::DspinInput<dspin_in_width>   p_dspin_m2p;
+    soclib::caba::DspinOutput<dspin_out_width> p_dspin_p2m;
+    soclib::caba::DspinInput<dspin_in_width>   p_dspin_clack;
 
 private:
@@ -387 +388 @@
     sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
 
+    // coherence clack handling
+    sc_signal<bool>         r_icache_clack_req;         // clack request
+    sc_signal<size_t>       r_icache_clack_way;             // clack way
+    sc_signal<size_t>       r_icache_clack_set;             // clack set
+
     // icache flush handling
     sc_signal<size_t>       r_icache_flush_count;           // slot counter used for cache flush
@@ -459 +465 @@
     sc_signal<size_t>       r_dcache_cc_word;               // word counter for cc update
     sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
+
+    // coherence clack handling
+    sc_signal<bool>         r_dcache_clack_req;         // clack request
+    sc_signal<size_t>       r_dcache_clack_way;             // clack way
+    sc_signal<size_t>       r_dcache_clack_set;             // clack set
 
     // dcache flush handling
@@ -586 +597 @@
     sc_signal<paddr_t>      r_cc_receive_dcache_nline;      // cache line physical address
 
+    ///////////////////////////////////
+    //  DSPIN CLACK INTERFACE REGISTER
+    ///////////////////////////////////
+    sc_signal<bool>         r_dspin_clack_req;
+    sc_signal<uint64_t>     r_dspin_clack_flit;
+    
     //////////////////////////////////////////////////////////////////
     // processor, write buffer, caches , TLBs