Changeset 460 for branches/ODCCP/modules/vci_mem_cache/caba/source/src
- Timestamp:
- Jul 19, 2013, 2:34:03 PM (11 years ago)
- Location:
- branches/ODCCP/modules/vci_mem_cache
- Files:
-
- 1 edited
- 1 copied
Legend:
- Unmodified
- Added
- Removed
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branches/ODCCP/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r449 r460 217 217 "IXR_CMD_CAS_IDLE", 218 218 "IXR_CMD_XRAM_IDLE", 219 "IXR_CMD_CLEANUP_IDLE", 219 220 "IXR_CMD_READ", 220 221 "IXR_CMD_WRITE", 221 222 "IXR_CMD_CAS", 222 "IXR_CMD_XRAM" 223 "IXR_CMD_XRAM", 224 "IXR_CMD_CLEANUP_DATA" 223 225 }; 224 226 const char *cas_fsm_str[] = … … 250 252 "CLEANUP_IDLE", 251 253 "CLEANUP_GET_NLINE", 254 "CLEANUP_GET_DATA", 252 255 "CLEANUP_DIR_REQ", 253 256 "CLEANUP_DIR_LOCK", … … 263 266 "CLEANUP_WRITE_RSP", 264 267 "CLEANUP_CONFIG_ACK", 268 "CLEANUP_IXR_REQ", 269 "CLEANUP_WAIT", 265 270 "CLEANUP_SEND_CLACK" 266 271 }; … … 280 285 "ALLOC_TRT_CAS", 281 286 "ALLOC_TRT_XRAM_RSP", 282 "ALLOC_TRT_IXR_RSP" 287 "ALLOC_TRT_IXR_RSP", 288 "ALLOC_TRT_CLEANUP" 283 289 }; 284 290 const char *alloc_upt_fsm_str[] = … … 333 339 : soclib::caba::BaseModule(name), 334 340 341 m_monitor_ok(false), 342 335 343 p_clk( "p_clk" ), 336 344 p_resetn( "p_resetn" ), … … 496 504 // Allocation for IXR_RSP FSM 497 505 r_ixr_rsp_to_xram_rsp_rok = new sc_signal<bool>[m_trt_lines]; 506 //r_ixr_rsp_to_xram_rsp_no_coherent = new sc_signal<bool>[m_trt_lines]; 498 507 499 508 // Allocation for XRAM_RSP FSM … … 517 526 r_cas_data = new sc_signal<data_t>[nwords]; 518 527 r_cas_rdata = new sc_signal<data_t>[2]; 528 529 // Allocation for ODCCP 530 r_cleanup_data = new sc_signal<data_t>[nwords]; 531 r_cleanup_to_ixr_cmd_data = new sc_signal<data_t>[nwords]; 519 532 520 533 // Allocation for debug … … 631 644 632 645 ///////////////////////////////////////// 646 tmpl(void) ::clear_stats() 647 ///////////////////////////////////////// 648 { 649 m_cpt_cycles = 0; 650 m_cpt_read = 0; 651 m_cpt_read_miss = 0; 652 m_cpt_write = 0; 653 m_cpt_write_miss = 0; 654 m_cpt_write_cells = 0; 655 m_cpt_write_dirty = 0; 656 m_cpt_update = 0; 657 m_cpt_update_mult = 0; 658 m_cpt_inval_brdcast = 0; 659 m_cpt_inval = 0; 660 m_cpt_inval_mult = 0; 661 m_cpt_cleanup = 0; 662 m_cpt_cleanup_data = 0; 663 m_cpt_ll = 0; 664 m_cpt_sc = 0; 665 m_cpt_cas = 0; 666 m_cpt_trt_full = 0; 667 m_cpt_trt_rb = 0; 668 m_cpt_dir_unused = 0; 669 m_cpt_upt_unused = 0; 670 m_cpt_heap_unused = 0; 671 m_cpt_trt_unused = 0; 672 m_cpt_read_fsm_n_dir_lock = 0; 673 m_cpt_read_fsm_dir_lock = 0; 674 m_cpt_read_fsm_dir_used = 0; 675 m_cpt_read_fsm_trt_lock = 0; 676 m_cpt_read_fsm_heap_lock = 0; 677 m_cpt_write_fsm_dir_lock = 0; 678 m_cpt_write_fsm_n_dir_lock = 0; 679 m_cpt_write_fsm_upt_lock = 0; 680 m_cpt_write_fsm_heap_lock = 0; 681 m_cpt_write_fsm_dir_used = 0; 682 m_cpt_write_fsm_trt_lock = 0; 683 m_cpt_cas_fsm_n_dir_lock = 0; 684 m_cpt_cas_fsm_dir_lock = 0; 685 m_cpt_cas_fsm_upt_lock = 0; 686 m_cpt_cas_fsm_heap_lock = 0; 687 m_cpt_cas_fsm_trt_lock = 0; 688 m_cpt_cas_fsm_dir_used = 0; 689 m_cpt_xram_rsp_fsm_n_dir_lock = 0; 690 m_cpt_xram_rsp_fsm_dir_lock = 0; 691 m_cpt_xram_rsp_fsm_trt_lock = 0; 692 m_cpt_xram_rsp_fsm_upt_lock = 0; 693 m_cpt_xram_rsp_fsm_heap_lock = 0; 694 m_cpt_xram_rsp_fsm_dir_used = 0; 695 m_cpt_cleanup_fsm_dir_lock = 0; 696 m_cpt_cleanup_fsm_n_dir_lock = 0; 697 m_cpt_cleanup_fsm_heap_lock = 0; 698 m_cpt_cleanup_fsm_upt_lock = 0; 699 m_cpt_cleanup_fsm_dir_used = 0; 700 m_cpt_ixr_fsm_trt_lock = 0; 701 m_cpt_multi_ack_fsm_upt_lock = 0; 702 } 703 ///////////////////////////////////////// 633 704 tmpl(void) ::print_stats() 634 705 ///////////////////////////////////////// … … 637 708 std::cout 638 709 << "MEM_CACHE " << name() << " / Time = " << m_cpt_cycles << std::endl 639 << "- READ RATE = " << (double) m_cpt_read/m_cpt_cycles << std::endl 640 << "- READ TOTAL = " << m_cpt_read << std::endl 641 << "- READ MISS RATE = " << (double) m_cpt_read_miss/m_cpt_read << std::endl 642 << "- WRITE RATE = " << (double) m_cpt_write/m_cpt_cycles << std::endl 643 << "- WRITE TOTAL = " << m_cpt_write << std::endl 644 << "- WRITE MISS RATE = " << (double) m_cpt_write_miss/m_cpt_write << std::endl 645 << "- WRITE BURST LENGTH = " << (double) m_cpt_write_cells/m_cpt_write << std::endl 646 << "- WRITE BURST TOTAL = " << m_cpt_write_cells << std::endl 647 << "- REQUESTS TRT FULL = " << m_cpt_trt_full << std::endl 648 << "- READ TRT BLOKED HIT = " << m_cpt_trt_rb << std::endl 649 << "- UPDATE RATE = " << (double) m_cpt_update/m_cpt_cycles << std::endl 650 << "- UPDATE ARITY = " << (double) m_cpt_update_mult/m_cpt_update << std::endl 651 << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast) /m_cpt_cycles << std::endl 652 << "- INVAL MULTICAST ARITY= " << (double) m_cpt_inval_mult/ (m_cpt_inval-m_cpt_inval_brdcast) << std::endl 653 << "- INVAL BROADCAST RATE = " << (double) m_cpt_inval_brdcast/m_cpt_cycles << std::endl 654 << "- SAVE DIRTY RATE = " << (double) m_cpt_write_dirty/m_cpt_cycles << std::endl 655 << "- CLEANUP RATE = " << (double) m_cpt_cleanup/m_cpt_cycles << std::endl 656 << "- LL RATE = " << (double) m_cpt_ll/m_cpt_cycles << std::endl 657 << "- SC RATE = " << (double) m_cpt_sc/m_cpt_cycles << std::endl 658 << "- CAS RATE = " << (double) m_cpt_cas/m_cpt_cycles << std::endl; 710 << "- READ RATE = " << (double) m_cpt_read/m_cpt_cycles << std::endl 711 << "- READ TOTAL = " << m_cpt_read << std::endl 712 << "- READ MISS RATE = " << (double) m_cpt_read_miss/m_cpt_read << std::endl 713 << "- WRITE RATE = " << (double) m_cpt_write/m_cpt_cycles << std::endl 714 << "- WRITE TOTAL = " << m_cpt_write << std::endl 715 << "- WRITE MISS RATE = " << (double) m_cpt_write_miss/m_cpt_write << std::endl 716 << "- WRITE BURST LENGTH = " << (double) m_cpt_write_cells/m_cpt_write << std::endl 717 << "- WRITE BURST TOTAL = " << m_cpt_write_cells << std::endl 718 << "- REQUESTS TRT FULL = " << m_cpt_trt_full << std::endl 719 << "- READ TRT BLOKED HIT = " << m_cpt_trt_rb << std::endl 720 << "- UPDATE RATE = " << (double) m_cpt_update/m_cpt_cycles << std::endl 721 << "- UPDATE ARITY = " << (double) m_cpt_update_mult/m_cpt_update << std::endl 722 << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast) /m_cpt_cycles << std::endl 723 << "- INVAL MULTICAST ARITY = " << (double) m_cpt_inval_mult/ (m_cpt_inval-m_cpt_inval_brdcast) << std::endl 724 << "- INVAL BROADCAST RATE = " << (double) m_cpt_inval_brdcast/m_cpt_cycles << std::endl 725 << "- SAVE DIRTY RATE = " << (double) m_cpt_write_dirty/m_cpt_cycles << std::endl 726 << "- CLEANUP RATE = " << (double) m_cpt_cleanup/m_cpt_cycles << std::endl 727 << "- CLEANUP TOTAL = " << (double) m_cpt_cleanup << std::endl 728 << "- CLEANUP WITH DATA RATE = " << (double) m_cpt_cleanup_data/m_cpt_cycles << std::endl 729 << "- CLEANUP WITH DATA TOTAL = " << (double) m_cpt_cleanup_data << std::endl 730 << "- LL RATE = " << (double) m_cpt_ll/m_cpt_cycles << std::endl 731 << "- SC RATE = " << (double) m_cpt_sc/m_cpt_cycles << std::endl 732 << "- CAS RATE = " << (double) m_cpt_cas/m_cpt_cycles << std::endl << std::endl; 733 734 /* << "- WAIT DIR LOCK in READ_FSM = " << (double) m_cpt_read_fsm_dir_lock/m_cpt_read_fsm_n_dir_lock << std::endl 735 << "- NB CYCLES IN DIR LOCK in READ_FSM = " << (double) m_cpt_read_fsm_dir_used/m_cpt_read_fsm_n_dir_lock << std::endl 736 << "- WAIT DIR LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_dir_lock/m_cpt_write_fsm_n_dir_lock << std::endl 737 << "- NB CYCLES IN DIR LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_dir_used/m_cpt_write_fsm_n_dir_lock << std::endl 738 << "- WAIT DIR LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_dir_lock/m_cpt_xram_rsp_fsm_n_dir_lock << std::endl 739 << "- NB CYCLES IN DIR LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_dir_used/m_cpt_xram_rsp_fsm_n_dir_lock << std::endl 740 << "- WAIT DIR LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_dir_lock/m_cpt_cleanup_fsm_n_dir_lock << std::endl 741 << "- NB CYCLES IN DIR LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_dir_used/m_cpt_cleanup_fsm_n_dir_lock << std::endl 742 << "- WAIT DIR LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_dir_lock/m_cpt_cas_fsm_n_dir_lock << std::endl 743 << "- NB CYCLES IN LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_dir_used/m_cpt_cas_fsm_n_dir_lock << std::endl 744 << "- DIR UNUSED RATE = " << (double) m_cpt_dir_unused/m_cpt_cycles << std::endl << std::endl 745 746 << "- WAIT TRT LOCK in READ_FSM = " << (double) m_cpt_read_fsm_trt_lock/m_cpt_read_fsm_n_trt_lock << std::endl 747 << "- NB CYCLES IN TRT LOCK in READ_FSM = " << (double) m_cpt_read_fsm_trt_used/m_cpt_read_fsm_n_trt_lock << std::endl 748 << "- WAIT TRT LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_trt_lock/m_cpt_write_fsm_n_trt_lock << std::endl 749 << "- NB CYCLES IN TRT LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_trt_used/m_cpt_write_fsm_n_trt_lock << std::endl 750 << "- WAIT TRT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_trt_lock/m_cpt_cas_fsm_n_trt_lock << std::endl 751 << "- NB CYCLES IN TRT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_trt_used/m_cpt_cas_fsm_n_trt_lock << std::endl 752 << "- WAIT TRT LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_trt_lock/m_cpt_xram_rsp_fsm_n_trt_lock << std::endl 753 << "- NB CYCLES IN TRT LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_trt_used/m_cpt_xram_rsp_fsm_n_trt_lock << std::endl 754 << "- WAIT TRT LOCK in IXR_FSM = " << (double) m_cpt_ixr_fsm_trt_lock/m_cpt_ixr_fsm_n_trt_lock << std::endl 755 << "- NB CYCLES IN TRT LOCK in IXR_FSM = " << (double) m_cpt_ixr_fsm_trt_used/m_cpt_ixr_fsm_n_trt_lock << std::endl 756 << "- TRT UNUSED RATE = " << (double) m_cpt_trt_unused/m_cpt_cycles << std::endl << std::endl 757 758 << "- WAIT UPT LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_upt_lock/m_cpt_write_fsm_n_upt_lock << std::endl 759 << "- NB CYCLES IN UPT LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_upt_used/m_cpt_write_fsm_n_upt_lock << std::endl 760 << "- WAIT UPT LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_upt_lock/m_cpt_xram_rsp_fsm_n_upt_lock << std::endl 761 << "- NB CYCLES IN UPT LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_upt_used/m_cpt_xram_rsp_fsm_n_upt_lock << std::endl 762 << "- WAIT UPT LOCK in MULTIACK_FSM = " << (double) m_cpt_multi_ack_fsm_upt_lock/m_cpt_multi_ack_fsm_n_upt_lock << std::endl 763 << "- NB CYCLES IN UPT LOCK in MULTIACK_FSM = " << (double) m_cpt_multi_ack_fsm_upt_used/m_cpt_multi_ack_fsm_n_upt_lock << std::endl 764 << "- WAIT UPT LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_upt_lock/m_cpt_cleanup_fsm_n_upt_lock << std::endl 765 << "- NB CYCLES IN UPT LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_upt_used/m_cpt_cleanup_fsm_n_upt_lock << std::endl 766 << "- WAIT UPT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_upt_lock/m_cpt_cas_fsm_n_upt_lock << std::endl 767 << "- NB CYCLES IN UPT LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_upt_used/m_cpt_cas_fsm_n_upt_lock << std::endl 768 << "- UPT UNUSED RATE = " << (double) m_cpt_upt_unused/m_cpt_cycles << std::endl << std::endl 769 770 << "- WAIT HEAP LOCK in READ_FSM = " << (double) m_cpt_read_fsm_heap_lock/m_cpt_read_fsm_n_heap_lock << std::endl 771 << "- NB CYCLES IN HEAP LOCK in READ_FSM = " << (double) m_cpt_read_fsm_heap_used/m_cpt_read_fsm_n_heap_lock << std::endl 772 << "- WAIT HEAP LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_heap_lock/m_cpt_write_fsm_n_heap_lock << std::endl 773 << "- NB CYCLES IN HEAP LOCK in WRITE_FSM = " << (double) m_cpt_write_fsm_heap_used/m_cpt_write_fsm_n_heap_lock << std::endl 774 << "- WAIT HEAP LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_heap_lock/m_cpt_xram_rsp_fsm_n_heap_lock << std::endl 775 << "- NB CYCLES IN HEAP LOCK in XRAM_FSM = " << (double) m_cpt_xram_rsp_fsm_heap_used/m_cpt_xram_rsp_fsm_n_heap_lock << std::endl 776 << "- WAIT HEAP LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_heap_lock/m_cpt_cleanup_fsm_n_heap_lock << std::endl 777 << "- NB CYCLES IN HEAP LOCK in CLEANUP_FSM = " << (double) m_cpt_cleanup_fsm_heap_used/m_cpt_cleanup_fsm_n_heap_lock << std::endl 778 << "- WAIT HEAP LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_heap_lock/m_cpt_cas_fsm_n_heap_lock << std::endl 779 << "- NB CYCLES IN HEAP LOCK in CAS_FSM = " << (double) m_cpt_cas_fsm_heap_used/m_cpt_cas_fsm_n_heap_lock << std::endl 780 << "- HEAP UNUSED RATE = " << (double) m_cpt_heap_unused/m_cpt_cycles << std::endl;*/ 659 781 } 660 782 … … 664 786 { 665 787 delete [] r_ixr_rsp_to_xram_rsp_rok; 788 //delete [] r_ixr_rsp_to_xram_rsp_no_coherent; 666 789 667 790 delete [] r_xram_rsp_victim_data; … … 675 798 delete [] r_write_be; 676 799 delete [] r_write_to_cc_send_data; 800 801 delete [] r_cleanup_data; 802 delete [] r_cleanup_to_ixr_cmd_data; 677 803 } 678 804 … … 788 914 { 789 915 r_ixr_rsp_to_xram_rsp_rok[i] = false; 916 //r_ixr_rsp_to_xram_rsp_no_coherent[i] = false; 790 917 } 791 918 … … 808 935 r_tgt_rsp_key_sent = false; 809 936 937 // ODCCP 938 r_cleanup_data_index = 0; 939 r_cleanup_trdid = 0; 940 r_cleanup_pktid = 0; 941 r_cleanup_contains_data = false; 942 r_cleanup_to_ixr_cmd_req = false; 943 r_cleanup_to_ixr_cmd_l1_dirty_ncc = false; 944 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; 945 r_cleanup_to_ixr_cmd_srcid = 0; 946 r_cleanup_to_ixr_cmd_trdid = 0; 947 r_cleanup_to_ixr_cmd_pktid = 0; 948 r_cleanup_to_ixr_cmd_nline = 0; 949 for (size_t word = 0; word < m_words; word ++) 950 { 951 r_cleanup_to_ixr_cmd_data[word] = 0; 952 r_cleanup_data[word] = 0; 953 } 954 955 810 956 // Activity counters 811 m_cpt_cycles = 0; 812 m_cpt_read = 0; 813 m_cpt_read_miss = 0; 814 m_cpt_write = 0; 815 m_cpt_write_miss = 0; 816 m_cpt_write_cells = 0; 817 m_cpt_write_dirty = 0; 818 m_cpt_update = 0; 819 m_cpt_update_mult = 0; 820 m_cpt_inval_brdcast = 0; 821 m_cpt_inval = 0; 822 m_cpt_inval_mult = 0; 823 m_cpt_cleanup = 0; 824 m_cpt_ll = 0; 825 m_cpt_sc = 0; 826 m_cpt_cas = 0; 827 m_cpt_trt_full = 0; 828 m_cpt_trt_rb = 0; 957 m_cpt_cycles = 0; 958 m_cpt_read = 0; 959 m_cpt_read_miss = 0; 960 m_cpt_write = 0; 961 m_cpt_write_miss = 0; 962 m_cpt_write_cells = 0; 963 m_cpt_write_dirty = 0; 964 m_cpt_update = 0; 965 m_cpt_update_mult = 0; 966 m_cpt_inval_brdcast = 0; 967 m_cpt_inval = 0; 968 m_cpt_inval_mult = 0; 969 m_cpt_cleanup = 0; 970 m_cpt_cleanup_data = 0; 971 m_cpt_ll = 0; 972 m_cpt_sc = 0; 973 m_cpt_cas = 0; 974 m_cpt_trt_full = 0; 975 m_cpt_trt_rb = 0; 976 m_cpt_dir_unused = 0; 977 m_cpt_upt_unused = 0; 978 m_cpt_heap_unused = 0; 979 m_cpt_trt_unused = 0; 980 m_cpt_read_fsm_n_dir_lock = 0; 981 m_cpt_read_fsm_dir_lock = 0; 982 m_cpt_read_fsm_dir_used = 0; 983 m_cpt_read_fsm_trt_lock = 0; 984 m_cpt_read_fsm_heap_lock = 0; 985 m_cpt_write_fsm_dir_lock = 0; 986 m_cpt_write_fsm_n_dir_lock = 0; 987 m_cpt_write_fsm_upt_lock = 0; 988 m_cpt_write_fsm_heap_lock = 0; 989 m_cpt_write_fsm_dir_used = 0; 990 m_cpt_write_fsm_trt_lock = 0; 991 m_cpt_cas_fsm_n_dir_lock = 0; 992 m_cpt_cas_fsm_dir_lock = 0; 993 m_cpt_cas_fsm_upt_lock = 0; 994 m_cpt_cas_fsm_heap_lock = 0; 995 m_cpt_cas_fsm_trt_lock = 0; 996 m_cpt_cas_fsm_dir_used = 0; 997 m_cpt_xram_rsp_fsm_n_dir_lock = 0; 998 m_cpt_xram_rsp_fsm_dir_lock = 0; 999 m_cpt_xram_rsp_fsm_trt_lock = 0; 1000 m_cpt_xram_rsp_fsm_upt_lock = 0; 1001 m_cpt_xram_rsp_fsm_heap_lock = 0; 1002 m_cpt_xram_rsp_fsm_dir_used = 0; 1003 m_cpt_cleanup_fsm_dir_lock = 0; 1004 m_cpt_cleanup_fsm_n_dir_lock = 0; 1005 m_cpt_cleanup_fsm_heap_lock = 0; 1006 m_cpt_cleanup_fsm_upt_lock = 0; 1007 m_cpt_cleanup_fsm_dir_used = 0; 1008 m_cpt_ixr_fsm_trt_lock = 0; 1009 m_cpt_multi_ack_fsm_upt_lock = 0; 829 1010 830 1011 return; … … 1319 1500 case MULTI_ACK_UPT_LOCK: 1320 1501 { 1502 m_cpt_multi_ack_fsm_upt_lock++; 1321 1503 // get lock to the UPDATE table 1322 if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break;1504 if(r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break; 1323 1505 1324 1506 // decrement the number of expected responses 1325 1507 size_t count = 0; 1326 1508 bool valid = m_upt.decrement(r_multi_ack_upt_index.read(), count); 1509 1327 1510 1328 1511 if(not valid) … … 1349 1532 << " entry = " << r_multi_ack_upt_index.read() 1350 1533 << " / rsp_count = " << std::dec << count << std::endl; 1534 m_cpt_multi_ack_fsm_n_upt_lock++; 1351 1535 #endif 1352 1536 break; … … 1874 2058 { 1875 2059 r_read_fsm = READ_DIR_LOCK; 2060 m_cpt_read_fsm_n_dir_lock++; 1876 2061 } 1877 2062 … … 1880 2065 std::cout << " <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl; 1881 2066 #endif 2067 2068 m_cpt_read_fsm_dir_lock++; 2069 1882 2070 break; 1883 2071 } … … 1981 2169 if(m_monitor_ok) check_monitor( m_cmd_read_addr_fifo.read(), r_read_data[0], true); 1982 2170 1983 // update the cache directory 1984 DirectoryEntry entry; 1985 entry.valid = true; 1986 entry.is_cnt = is_cnt; 1987 entry.dirty = r_read_dirty.read(); 1988 entry.tag = r_read_tag.read(); 1989 entry.lock = r_read_lock.read(); 1990 entry.ptr = r_read_ptr.read(); 1991 1992 if(cached_read) // Cached read => we must update the copies 1993 { 1994 if(!is_cnt) // Not counter mode 1995 { 1996 entry.owner.srcid = m_cmd_read_srcid_fifo.read(); 2171 // update the cache directory 2172 DirectoryEntry entry; 2173 entry.valid = true; 2174 entry.is_cnt = is_cnt; 2175 entry.dirty = r_read_dirty.read(); 2176 entry.tag = r_read_tag.read(); 2177 entry.lock = r_read_lock.read(); 2178 entry.ptr = r_read_ptr.read(); 2179 2180 /*ODCCP*/ // if pktid = 0x9 that means read on no coherent line 2181 if(m_cmd_read_pktid_fifo.read() == 0x9){ 2182 entry.coherent = false; 2183 } 2184 else{ 2185 entry.coherent = true; 2186 } 2187 2188 if(cached_read) // Cached read => we must update the copies 2189 { 2190 if(!is_cnt) // Not counter mode 2191 { 2192 entry.owner.srcid = m_cmd_read_srcid_fifo.read(); 1997 2193 #if L1_MULTI_CACHE 1998 1999 #endif 2000 2001 2002 2003 2004 2005 2194 entry.owner.cache_id = m_cmd_read_pktid_fifo.read(); 2195 #endif 2196 entry.owner.inst = inst_read; 2197 entry.count = r_read_count.read() + 1; 2198 } 2199 else // Counter mode 2200 { 2201 entry.owner.srcid = 0; 2006 2202 #if L1_MULTI_CACHE 2007 2008 #endif 2009 2010 2011 2012 2013 2014 2015 2203 entry.owner.cache_id = 0; 2204 #endif 2205 entry.owner.inst = false; 2206 entry.count = r_read_count.read() + 1; 2207 } 2208 } 2209 else // Uncached read 2210 { 2211 entry.owner.srcid = r_read_copy.read(); 2016 2212 #if L1_MULTI_CACHE 2017 2018 #endif 2019 2020 2021 2213 entry.owner.cache_id = r_read_copy_cache.read(); 2214 #endif 2215 entry.owner.inst = r_read_copy_inst.read(); 2216 entry.count = r_read_count.read(); 2217 } 2022 2218 2023 2219 #if DEBUG_MEMC_READ … … 2033 2229 #endif 2034 2230 2035 m_cache_directory.write(set, way, entry); 2036 r_read_fsm = READ_RSP; 2037 } 2038 break; 2231 if(m_monitor_ok) 2232 { 2233 char buf[80]; 2234 snprintf(buf, 80, "READ_DIR_HIT srcid %d, ins %d", 2235 (int)m_cmd_read_srcid_fifo.read(), 2236 (int)((m_cmd_read_pktid_fifo.read()&0x2)!=0)); 2237 check_monitor(m_cmd_read_addr_fifo.read(), r_read_data[0], true); 2238 } 2239 m_cache_directory.write(set, way, entry); 2240 r_read_fsm = READ_RSP; 2241 } 2242 break; 2039 2243 } 2040 2244 /////////////////// … … 2044 2248 { 2045 2249 r_read_fsm = READ_HEAP_LOCK; 2250 m_cpt_read_fsm_n_heap_lock++; 2046 2251 } 2047 2252 … … 2051 2256 << " Requesting HEAP lock " << std::endl; 2052 2257 #endif 2258 2259 m_cpt_read_fsm_heap_lock++; 2260 2053 2261 break; 2054 2262 } … … 2283 2491 { 2284 2492 size_t index = 0; 2493 size_t index_write = 0; 2285 2494 addr_t addr = (addr_t) m_cmd_read_addr_fifo.read(); 2286 2495 bool hit_read = m_trt.hit_read(m_nline[addr], index); 2287 bool hit_write = m_trt.hit_write(m_nline[addr] );2496 bool hit_write = m_trt.hit_write(m_nline[addr], &index_write); 2288 2497 bool wok = !m_trt.full(index); 2289 2498 … … 2306 2515 << " hit_read = " << hit_read 2307 2516 << " / hit_write = " << hit_write 2517 << " / Index = " << index_write 2308 2518 << " / full = " << !wok << std::endl; 2309 #endif 2310 } 2519 m_cpt_read_fsm_n_trt_lock++; 2520 #endif 2521 } 2522 2523 m_cpt_read_fsm_trt_lock++; 2524 2311 2525 break; 2312 2526 } … … 2533 2747 2534 2748 r_write_fsm = WRITE_DIR_LOCK; 2749 m_cpt_write_fsm_n_dir_lock++; 2535 2750 } 2536 2751 … … 2540 2755 << std::endl; 2541 2756 #endif 2757 2758 m_cpt_write_fsm_dir_lock++; 2542 2759 2543 2760 break; … … 2792 3009 if(wok) r_write_fsm = WRITE_UPT_HEAP_LOCK; 2793 3010 else r_write_fsm = WRITE_WAIT; 2794 } 3011 m_cpt_write_fsm_n_upt_lock++; 3012 } 3013 3014 m_cpt_write_fsm_upt_lock++; 3015 2795 3016 break; 2796 3017 } … … 2808 3029 #endif 2809 3030 r_write_fsm = WRITE_UPT_REQ; 2810 } 3031 m_cpt_write_fsm_n_heap_lock++; 3032 } 3033 3034 m_cpt_write_fsm_heap_lock++; 3035 2811 3036 break; 2812 3037 } … … 3093 3318 m_cpt_trt_full++; 3094 3319 } 3095 } 3320 m_cpt_write_fsm_n_trt_lock++; 3321 } 3322 3323 m_cpt_write_fsm_trt_lock++; 3324 3096 3325 break; 3097 3326 } … … 3212 3441 << " : wok = " << wok << " / index = " << wok_index << std::endl; 3213 3442 #endif 3214 } 3443 m_cpt_write_fsm_n_trt_lock++; 3444 } 3445 3446 m_cpt_write_fsm_trt_lock++; 3447 3215 3448 break; 3216 3449 } … … 3239 3472 nb_copies, 3240 3473 index); 3241 3242 3474 #if DEBUG_MEMC_WRITE 3243 3475 if( m_debug and wok ) … … 3249 3481 if(wok) r_write_fsm = WRITE_BC_DIR_INVAL; 3250 3482 else r_write_fsm = WRITE_WAIT; 3251 } 3483 m_cpt_write_fsm_n_upt_lock++; 3484 } 3485 3486 m_cpt_write_fsm_upt_lock++; 3487 3252 3488 break; 3253 3489 } … … 3382 3618 //////////////////////// 3383 3619 case IXR_CMD_READ_IDLE: 3384 {3385 3620 if (r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 3386 3621 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3387 3622 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3623 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3388 3624 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3389 3625 break; 3390 }3391 3626 //////////////////////// 3392 3627 case IXR_CMD_WRITE_IDLE: 3393 { 3394 if (r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3628 if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3395 3629 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3630 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3396 3631 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3397 3632 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 3398 3633 break; 3399 }3400 3634 //////////////////////// 3401 3635 case IXR_CMD_CAS_IDLE: 3402 {3403 if (r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM;3636 if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3637 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3404 3638 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3405 3639 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 3406 3640 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3407 3641 break; 3408 }3409 3642 //////////////////////// 3410 3643 case IXR_CMD_XRAM_IDLE: 3411 {3412 if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ;3413 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE;3644 if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3645 else if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3646 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 3414 3647 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3415 3648 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3416 3649 break; 3417 } 3650 //////////////////////// 3651 case IXR_CMD_CLEANUP_IDLE: 3652 if(r_read_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_READ; 3653 else if(r_write_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_WRITE; 3654 else if(r_cas_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CAS; 3655 else if(r_xram_rsp_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_XRAM; 3656 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_DATA; 3657 break; 3418 3658 ////////////////// // send a get from READ FSM 3419 3659 case IXR_CMD_READ: … … 3541 3781 break; 3542 3782 } 3783 3784 //////////////////////// 3785 case IXR_CMD_CLEANUP_DATA: // send a put command to XRAM 3786 if(p_vci_ixr.cmdack) 3787 { 3788 if(r_ixr_cmd_cpt.read() == (m_words - 2)) 3789 { 3790 r_ixr_cmd_cpt = 0; 3791 r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE; 3792 r_cleanup_to_ixr_cmd_req = false; 3793 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = false; 3794 } 3795 else 3796 { 3797 r_ixr_cmd_cpt = r_ixr_cmd_cpt.read() + 2; 3798 } 3799 3800 #if DEBUG_MEMC_IXR_CMD 3801 if(m_debug) 3802 { 3803 std::cout << " <MEMC " << name() << ".IXR_CMD_CLEANUP_DATA> Send a put request to xram" << std::endl; 3804 } 3805 #endif 3806 } 3807 break; 3543 3808 3544 3809 } // end switch r_ixr_cmd_fsm … … 3619 3884 << r_ixr_rsp_trt_index.read() << std::endl; 3620 3885 #endif 3621 } 3886 m_cpt_ixr_fsm_n_trt_lock++; 3887 } 3888 3889 m_cpt_ixr_fsm_trt_lock++; 3890 3622 3891 break; 3623 3892 } … … 3645 3914 { 3646 3915 r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true; 3916 /*if(p_vci_ixr.rpktid.read()&0xF == 0x9) 3917 r_ixr_rsp_to_xram_rsp_no_coherent[r_ixr_rsp_trt_index.read()] = true; 3918 else 3919 r_ixr_rsp_to_xram_rsp_no_coherent[r_ixr_rsp_trt_index.read()] = false;*/ 3647 3920 r_ixr_rsp_fsm = IXR_RSP_IDLE; 3648 3921 } … … 3655 3928 << " / data = " << std::hex << data << std::endl; 3656 3929 #endif 3657 } 3930 m_cpt_ixr_fsm_n_trt_lock++; 3931 } 3932 m_cpt_ixr_fsm_trt_lock++; 3658 3933 break; 3659 3934 } … … 3728 4003 << " Get access to DIR and TRT" << std::endl; 3729 4004 #endif 3730 } 4005 m_cpt_xram_rsp_fsm_n_dir_lock++; 4006 m_cpt_xram_rsp_fsm_n_trt_lock++; 4007 } 4008 m_cpt_xram_rsp_fsm_dir_lock++; 4009 m_cpt_xram_rsp_fsm_trt_lock++; 3731 4010 break; 3732 4011 } … … 3754 4033 r_xram_rsp_victim_copy_cache= victim.owner.cache_id; 3755 4034 #endif 4035 4036 r_xram_rsp_victim_coherent = victim.coherent; 3756 4037 r_xram_rsp_victim_copy_inst = victim.owner.inst; 3757 4038 r_xram_rsp_victim_count = victim.count; … … 3764 4045 r_xram_rsp_victim_dirty = victim.dirty; 3765 4046 4047 3766 4048 if(!r_xram_rsp_trt_buf.rerror) 3767 4049 { 3768 r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; 4050 /*ODCCP*/ //if victim is no coherent and there is an inval no coherent pending we wait 4051 if(!victim.coherent and r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read()) 4052 { 4053 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 4054 } 4055 else 4056 { 4057 r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK; 4058 } 3769 4059 } 3770 4060 else … … 3829 4119 #endif 3830 4120 } 3831 } 4121 m_cpt_xram_rsp_fsm_n_upt_lock++; 4122 } 4123 4124 m_cpt_xram_rsp_fsm_upt_lock++; 4125 3832 4126 break; 3833 4127 } … … 3892 4186 entry.owner.inst = inst_read; 3893 4187 entry.count = 1; 4188 3894 4189 } 3895 4190 else … … 3902 4197 entry.count = 0; 3903 4198 } 4199 4200 /*ODCCP*/ //if pktid = 0x9 that means line no coherent 4201 if(r_xram_rsp_trt_buf.pktid == 0x9){ 4202 entry.coherent = false; 4203 } 4204 else{ 4205 entry.coherent = true; 4206 } 4207 3904 4208 m_cache_directory.write(set, way, entry); 3905 4209 … … 3950 4254 #endif 3951 4255 3952 // If the victim is not dirty , we don't need another XRAM put transaction,4256 // If the victim is not dirty and coherent or victim's count egal 0 , we don't need another XRAM put transaction, 3953 4257 // and we can erase the TRT entry 3954 if(!r_xram_rsp_victim_dirty.read() ) m_trt.erase(r_xram_rsp_trt_index.read());4258 if(!r_xram_rsp_victim_dirty.read() and (r_xram_rsp_victim_coherent.read() or (r_xram_rsp_victim_count.read() == 0))) m_trt.erase(r_xram_rsp_trt_index.read()); 3955 4259 3956 4260 // Next state 3957 if(r_xram_rsp_victim_dirty.read() ) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;4261 if(r_xram_rsp_victim_dirty.read() or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; 3958 4262 else if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; 3959 4263 else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; … … 3987 4291 else if(r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 3988 4292 else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 3989 } 4293 m_cpt_xram_rsp_fsm_n_trt_lock++; 4294 } 4295 4296 m_cpt_xram_rsp_fsm_trt_lock++; 4297 3990 4298 break; 3991 4299 } … … 4009 4317 4010 4318 if(r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL; 4011 else if(r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;4319 else if(r_xram_rsp_victim_dirty or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 4012 4320 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 4013 4321 … … 4045 4353 r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); 4046 4354 4047 if(r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;4355 if(r_xram_rsp_victim_dirty or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1))) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 4048 4356 else if(not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; 4049 4357 else r_xram_rsp_fsm = XRAM_RSP_IDLE; … … 4061 4369 case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM 4062 4370 { 4063 if(!r_xram_rsp_to_ixr_cmd_req.read()) 4064 { 4371 if((!r_xram_rsp_to_ixr_cmd_req.read()) and (!r_xram_rsp_to_ixr_cmd_inval_ncc_pending.read())) 4372 { 4373 4065 4374 r_xram_rsp_to_ixr_cmd_req = true; 4066 4375 r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read(); … … 4071 4380 } 4072 4381 m_cpt_write_dirty++; 4382 4383 // if victim is no coherent, we dont request a ixr command 4384 if( (!r_xram_rsp_victim_coherent.read()) and (r_xram_rsp_victim_count.read() == 1) ) 4385 { 4386 r_xram_rsp_to_ixr_cmd_inval_ncc_pending = true; // inval no coherent pending 4387 r_xram_rsp_to_ixr_cmd_req = false; 4388 r_xram_rsp_fsm = XRAM_RSP_IDLE; 4389 break; 4390 } 4073 4391 4074 4392 bool multi_req = !r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read(); … … 4093 4411 { 4094 4412 r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; 4413 m_cpt_xram_rsp_fsm_n_heap_lock++; 4095 4414 } 4096 4415 … … 4100 4419 << " Requesting HEAP lock" << std::endl; 4101 4420 #endif 4421 4422 m_cpt_xram_rsp_fsm_heap_lock++; 4423 4102 4424 break; 4103 4425 } … … 4243 4565 4244 4566 uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); 4245 4246 4567 uint32_t srcid = 4247 4568 DspinDhccpParam::dspin_get( … … 4264 4585 DspinDhccpParam::CLEANUP_NLINE_MSB) << 32; 4265 4586 4587 /*ODCCP*/ // Cleanup on no coherent line if 1 4588 r_cleanup_ncc = 4589 DspinDhccpParam::dspin_get( 4590 flit, 4591 DspinDhccpParam::CLEANUP_NCC); 4592 4266 4593 r_cleanup_inst = (type == DspinDhccpParam::TYPE_CLEANUP_INST); 4267 4594 r_cleanup_srcid = srcid; … … 4295 4622 { 4296 4623 if(not m_cc_receive_to_cleanup_fifo.rok()) break; 4624 4297 4625 4298 4626 uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); … … 4300 4628 addr_t nline = r_cleanup_nline.read() | 4301 4629 DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB); 4630 4631 bool eop = DspinDhccpParam::dspin_get(flit, DspinDhccpParam::FROM_L1_EOP); 4632 4633 /*ODCCP*/ // if not eop (more than 2 flits) there is a cleanup no coherent with data 4634 if (!eop) 4635 { 4636 r_cleanup_contains_data = true; // this cleanup contains data 4637 r_cleanup_fsm = CLEANUP_GET_DATA; 4638 r_cleanup_data_index = 0; 4639 } 4640 else 4641 { 4642 r_cleanup_contains_data = false; 4643 r_cleanup_fsm = CLEANUP_DIR_REQ; 4644 } 4302 4645 4303 4646 cc_receive_to_cleanup_fifo_get = true; 4304 r_cleanup_nline = nline; 4305 r_cleanup_fsm = CLEANUP_DIR_REQ; 4647 r_cleanup_nline = nline; 4306 4648 4307 4649 #if DEBUG_MEMC_CLEANUP … … 4314 4656 } 4315 4657 4658 /*ODCCP*/ // We save the cleanup's data into a buffer 4659 case CLEANUP_GET_DATA : 4660 { 4661 if(not m_cc_receive_to_cleanup_fifo.rok()) break; 4662 4663 assert (r_cleanup_data_index.read() < m_words and "MEM_CACHE in CLEANUP_GET_DATA : too much flits in cleanup data updt"); 4664 4665 uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); 4666 4667 uint32_t data = 4668 DspinDhccpParam::dspin_get (flit, DspinDhccpParam::CLEANUP_DATA_UPDT); 4669 4670 r_cleanup_data[r_cleanup_data_index.read()] = data; 4671 r_cleanup_data_index = r_cleanup_data_index.read() + 1; 4672 cc_receive_to_cleanup_fifo_get = true; 4673 m_cpt_cleanup_data++; 4674 4675 if (r_cleanup_data_index.read() == m_words - 1) // last flit 4676 { 4677 r_cleanup_fsm = CLEANUP_DIR_REQ; 4678 } 4679 break; 4680 } 4316 4681 ///////////////////// 4317 4682 case CLEANUP_DIR_REQ: // Get the lock to the directory 4318 4683 { 4684 m_cpt_cleanup_fsm_dir_lock++; 4685 // Get the lock to the directory 4319 4686 if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; 4320 4687 … … 4325 4692 std::cout << " <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock" << std::endl; 4326 4693 #endif 4694 4695 m_cpt_cleanup_fsm_n_dir_lock++; 4696 4327 4697 break; 4328 4698 } … … 4341 4711 exit(0); 4342 4712 } 4343 4344 4713 // Read the directory 4345 4714 size_t way = 0; … … 4362 4731 if(entry.valid) // hit : the copy must be cleared 4363 4732 { 4733 if(entry.count < 1) 4734 { 4735 std::cout << "assert on line " << std::hex <<r_cleanup_nline.read() << " | at cycle " << std::dec <<m_cpt_cycles << std::endl; 4736 std::cout << "cleanup with data ? " << r_cleanup_contains_data.read() << " | at cycle " << m_cpt_cycles << std::endl; 4737 std::cout << "cleanup_address = " << std::hex << (r_cleanup_nline.read()*m_words*4) << std::dec << std::endl; 4738 std::cout << "srcid = " << r_cleanup_srcid.read() << std::endl; 4739 std::cout << "inst = " << r_cleanup_inst.read() << std::endl; 4740 std::cout << "inst = " << r_cleanup_inst.read() << std::endl; 4741 } 4364 4742 assert( 4365 4743 (entry.count > 0) and … … 4445 4823 entry.valid = true; 4446 4824 entry.is_cnt = r_cleanup_is_cnt.read(); 4447 entry.dirty = r_cleanup_dirty.read() ;4825 entry.dirty = r_cleanup_dirty.read() or r_cleanup_contains_data.read(); 4448 4826 entry.tag = r_cleanup_tag.read(); 4449 4827 entry.lock = r_cleanup_lock.read(); … … 4456 4834 entry.owner.cache_id = 0; 4457 4835 #endif 4836 /*ODCCP*/ // if cleanup contains data we update the cache data 4837 if (r_cleanup_contains_data.read()) 4838 { 4839 for (size_t word = 0; word < m_words; word ++) 4840 { 4841 m_cache_data.write(way, set, word, r_cleanup_data[word].read(), 0xF); 4842 } 4843 } 4844 4458 4845 4459 4846 m_cache_directory.write(set, way, entry); … … 4484 4871 { 4485 4872 // get the lock to the HEAP directory 4873 m_cpt_cleanup_fsm_heap_lock++; 4486 4874 if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break; 4487 4875 … … 4497 4885 } 4498 4886 #endif 4887 m_cpt_cleanup_fsm_n_heap_lock++; 4499 4888 break; 4500 4889 } … … 4575 4964 << " / r_cleanup_copy_inst = " << r_cleanup_copy_inst.read() << std::endl 4576 4965 << "heap_entry.owner.srcid = " << heap_entry.owner.srcid 4577 << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl; 4966 << " / heap_entry.owner.inst = " << heap_entry.owner.inst << std::endl 4967 << " / addr = " << std::hex << (r_cleanup_nline.read() *m_words*4) << std::dec << std::endl; 4578 4968 /**/ 4579 4969 … … 4842 5232 // invalidate transaction matching the cleanup 4843 5233 { 5234 m_cpt_cleanup_fsm_upt_lock++; 4844 5235 if(r_alloc_upt_fsm.read() != ALLOC_UPT_CLEANUP) break; 4845 5236 … … 4851 5242 if ( not match_inval ) // no pending inval 4852 5243 { 5244 /*ODCCP*/ // If cleanup is on no coherent line we go to CLEANUP_IXR_REQ 5245 if (r_cleanup_ncc.read()) 5246 { 5247 r_cleanup_fsm = CLEANUP_IXR_REQ; 5248 } 5249 else 5250 { 4853 5251 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5252 } 4854 5253 4855 5254 #if DEBUG_MEMC_CLEANUP … … 4862 5261 << std::endl; 4863 5262 #endif 4864 break; 5263 m_cpt_cleanup_fsm_n_upt_lock++; 5264 break; 4865 5265 } 4866 5266 … … 4908 5308 else // multi inval transaction not completed 4909 5309 { 4910 r_cleanup_fsm = CLEANUP_SEND_CLACK ; 5310 /*ODCCP*/ // If cleanup is on no coherent line we go to CLEANUP_IXR_REQ 5311 if (r_cleanup_ncc.read()) 5312 { 5313 r_cleanup_fsm = CLEANUP_IXR_REQ; 5314 } 5315 else 5316 { 5317 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5318 } 4911 5319 } 4912 5320 … … 4938 5346 if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; 4939 5347 else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK; 5348 else if ( r_cleanup_ncc.read() ) r_cleanup_fsm = CLEANUP_IXR_REQ; 4940 5349 else r_cleanup_fsm = CLEANUP_SEND_CLACK; 4941 5350 … … 4960 5369 r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); 4961 5370 4962 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5371 /*ODCCP*/ // If cleanup is on no coherent line we go to CLEANUP_IXR_REQ 5372 if (r_cleanup_ncc.read()) 5373 { 5374 r_cleanup_fsm = CLEANUP_IXR_REQ; 5375 } 5376 else 5377 { 5378 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5379 } 4963 5380 4964 5381 #if DEBUG_MEMC_CLEANUP … … 4977 5394 { 4978 5395 if ( r_cleanup_to_config_ack.read() ) break; 4979 4980 5396 r_cleanup_to_config_ack = true; 4981 5397 r_cleanup_fsm = CLEANUP_SEND_CLACK; … … 4988 5404 break; 4989 5405 } 5406 5407 /*ODCCP*/ 5408 case CLEANUP_IXR_REQ: 5409 { 5410 5411 //Send a request to the ixr to write the data in the XRAM and set an entry in the TRT. 5412 if (r_alloc_trt_fsm.read() == ALLOC_TRT_CLEANUP) 5413 { 5414 if(!r_cleanup_to_ixr_cmd_req.read()) 5415 { 5416 size_t index = 0; 5417 bool hit = m_trt.hit_write(r_cleanup_nline.read(), &index); // we save the index of the matching entry in TRT 5418 if (!hit) 5419 { 5420 std::cout << "assert on line " << r_cleanup_nline.read() << " | at cycle " << std::dec <<m_cpt_cycles << std::endl; 5421 for (int i=0; i<4; i++) m_trt.print(i); 5422 } 5423 assert (hit and "CLEANUP_IXR_REQ found no matching entry in TRT"); 5424 5425 r_cleanup_to_ixr_cmd_req = true; 5426 5427 for(size_t i = 0; i < m_words; i++){ 5428 r_cleanup_to_ixr_cmd_data[i] = r_cleanup_data[i]; 5429 } 5430 5431 r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read(); 5432 r_cleanup_to_ixr_cmd_trdid = index; 5433 r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); 5434 r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); 5435 r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read(); 5436 r_cleanup_fsm = CLEANUP_SEND_CLACK; 5437 #if DEBUG_MEMC_CLEANUP 5438 if(m_debug) 5439 { 5440 std::cout 5441 << " <MEMC " << name() 5442 << " CLEANUP_IXR_REQ> Send a put request to the ixr:" 5443 << " contains data ? = " << std::dec << r_cleanup_contains_data.read() 5444 << " srcid = " << std::dec << r_cleanup_srcid.read() 5445 << " pktid = " << std::dec << r_cleanup_pktid.read() 5446 << " trdid = " << std::dec << index 5447 << " nline = " << std::hex << r_cleanup_nline.read() << std::dec 5448 << std::endl; 5449 } 5450 #endif 5451 } 5452 else 5453 { 5454 r_cleanup_fsm = CLEANUP_WAIT; 5455 } 5456 } 5457 break; 5458 } 5459 5460 case CLEANUP_WAIT : 5461 { 5462 r_cleanup_fsm = CLEANUP_IXR_REQ; 5463 break; 5464 } 5465 4990 5466 //////////////////////// 4991 5467 case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command … … 5094 5570 { 5095 5571 r_cas_fsm = CAS_DIR_LOCK; 5572 m_cpt_cas_fsm_n_dir_lock++; 5096 5573 } 5097 5574 … … 5104 5581 } 5105 5582 #endif 5583 5584 m_cpt_cas_fsm_dir_lock++; 5585 5106 5586 break; 5107 5587 } … … 5347 5827 << " / count = " << nb_copies << std::endl; 5348 5828 #endif 5349 } 5829 m_cpt_cas_fsm_n_upt_lock++; 5830 } 5831 5832 m_cpt_cas_fsm_upt_lock++; 5833 5350 5834 break; 5351 5835 } … … 5378 5862 #endif 5379 5863 r_cas_fsm = CAS_UPT_REQ; 5380 } 5864 m_cpt_cas_fsm_n_heap_lock++; 5865 } 5866 5867 m_cpt_cas_fsm_heap_lock++; 5868 5381 5869 break; 5382 5870 } … … 5518 6006 r_cas_fsm = CAS_WAIT; 5519 6007 } 5520 } 6008 m_cpt_cas_fsm_n_trt_lock++; 6009 } 6010 6011 m_cpt_cas_fsm_trt_lock++; 6012 5521 6013 break; 5522 6014 } … … 5583 6075 r_cas_fsm = CAS_WAIT; 5584 6076 } 5585 } 6077 m_cpt_cas_fsm_n_upt_lock++; 6078 } 6079 6080 m_cpt_cas_fsm_upt_lock++; 6081 5586 6082 break; 5587 6083 } … … 5761 6257 r_cas_fsm = CAS_MISS_TRT_SET; 5762 6258 } 5763 } 6259 m_cpt_cas_fsm_n_trt_lock++; 6260 } 6261 6262 m_cpt_cas_fsm_trt_lock++; 6263 5764 6264 break; 5765 6265 } … … 6531 7031 case CC_RECEIVE_CLEANUP_EOP: 6532 7032 { 6533 // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo 7033 // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo or more in case of cleanup data (ODCCP) 6534 7034 6535 7035 if(not p_dspin_in.write or not m_cc_receive_to_cleanup_fifo.wok()) 6536 7036 break; 6537 7037 6538 assert(p_dspin_in.eop.read() and7038 /*assert(p_dspin_in.eop.read() and 6539 7039 "VCI_MEM_CACHE ERROR in CC_RECEIVE : " 6540 "CLEANUP command must have two flits"); 7040 "CLEANUP command must have two flits");*/ 6541 7041 6542 7042 cc_receive_to_cleanup_fifo_put = true; 6543 r_cc_receive_fsm = CC_RECEIVE_IDLE; 7043 if(p_dspin_in.eop.read()) 7044 r_cc_receive_fsm = CC_RECEIVE_IDLE; 6544 7045 6545 7046 break; … … 7020 7521 (r_cas_fsm.read() == CAS_BC_UPT_LOCK)) 7021 7522 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7022 7023 7523 else if(r_config_fsm.read() == CONFIG_DIR_UPT_LOCK) 7024 7524 r_alloc_upt_fsm = ALLOC_UPT_CONFIG; 7025 } 7525 else 7526 m_cpt_upt_unused++; 7527 } 7528 else 7529 m_cpt_multi_ack_fsm_upt_used++; 7026 7530 break; 7027 7531 … … 7046 7550 else if(r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7047 7551 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7048 } 7552 7553 else 7554 m_cpt_upt_unused++; 7555 } 7556 else 7557 m_cpt_write_fsm_upt_used++; 7049 7558 break; 7050 7559 … … 7069 7578 (r_write_fsm.read() == WRITE_BC_UPT_LOCK)) 7070 7579 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7071 } 7580 7581 else 7582 m_cpt_upt_unused++; 7583 } 7584 else 7585 m_cpt_xram_rsp_fsm_upt_used++; 7072 7586 break; 7073 7587 … … 7093 7607 else if(r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7094 7608 r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP; 7095 } 7609 7610 else 7611 m_cpt_upt_unused++; 7612 } 7613 else 7614 m_cpt_cleanup_fsm_upt_used++; 7096 7615 break; 7097 7616 … … 7116 7635 else if(r_cleanup_fsm.read() == CLEANUP_UPT_LOCK) 7117 7636 r_alloc_upt_fsm = ALLOC_UPT_CLEANUP; 7118 } 7637 7638 else 7639 m_cpt_upt_unused++; 7640 } 7641 else 7642 m_cpt_cas_fsm_upt_used++; 7119 7643 break; 7120 7644 … … 7189 7713 else if(r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 7190 7714 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 7191 7715 7192 7716 else if(r_config_fsm.read() == CONFIG_DIR_REQ) 7193 7717 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 7194 } 7195 break; 7718 7719 else 7720 m_cpt_dir_unused++; 7721 } 7722 else 7723 m_cpt_read_fsm_dir_used++; 7724 break; 7196 7725 7197 7726 ///////////////////// … … 7227 7756 else if(r_read_fsm.read() == READ_DIR_REQ) 7228 7757 r_alloc_dir_fsm = ALLOC_DIR_READ; 7229 } 7230 break; 7758 7759 else 7760 m_cpt_dir_unused++; 7761 } 7762 else 7763 m_cpt_write_fsm_dir_used++; 7764 break; 7231 7765 7232 7766 /////////////////// … … 7263 7797 else if(r_write_fsm.read() == WRITE_DIR_REQ) 7264 7798 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 7265 } 7799 7800 else 7801 m_cpt_dir_unused++; 7802 } 7803 else 7804 m_cpt_cas_fsm_dir_used++; 7266 7805 break; 7267 7806 … … 7287 7826 else if(r_cas_fsm.read() == CAS_DIR_REQ) 7288 7827 r_alloc_dir_fsm = ALLOC_DIR_CAS; 7289 } 7290 break; 7828 7829 else 7830 m_cpt_dir_unused++; 7831 } 7832 else 7833 m_cpt_cleanup_fsm_dir_used++; 7834 break; 7291 7835 7292 7836 //////////////////////// … … 7310 7854 else if(r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 7311 7855 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 7312 } 7313 break; 7856 7857 else 7858 m_cpt_dir_unused++; 7859 } 7860 else 7861 m_cpt_xram_rsp_fsm_dir_used++; 7862 break; 7314 7863 7315 7864 } // end switch alloc_dir_fsm … … 7345 7894 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 7346 7895 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 7347 } 7896 7897 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 7898 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 7899 7900 else 7901 m_cpt_trt_unused++; 7902 } 7903 else 7904 m_cpt_read_fsm_trt_used++; 7348 7905 break; 7349 7906 … … 7365 7922 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 7366 7923 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 7924 7925 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 7926 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 7367 7927 7368 7928 else if(r_read_fsm.read() == READ_TRT_LOCK) 7369 7929 r_alloc_trt_fsm = ALLOC_TRT_READ; 7370 } 7930 7931 else 7932 m_cpt_trt_unused++; 7933 } 7934 else 7935 m_cpt_write_fsm_trt_used++; 7371 7936 break; 7372 7937 … … 7384 7949 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 7385 7950 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 7951 7952 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 7953 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 7386 7954 7387 7955 else if(r_read_fsm.read() == READ_TRT_LOCK) … … 7391 7959 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 7392 7960 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 7393 } 7961 7962 else 7963 m_cpt_trt_unused++; 7964 } 7965 else 7966 m_cpt_cas_fsm_trt_used++; 7394 7967 break; 7395 7968 … … 7405 7978 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 7406 7979 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 7980 7981 else if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 7982 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 7407 7983 7408 7984 else if(r_read_fsm.read() == READ_TRT_LOCK) … … 7416 7992 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 7417 7993 r_alloc_trt_fsm = ALLOC_TRT_CAS; 7418 } 7994 7995 else 7996 m_cpt_trt_unused++; 7997 } 7998 else 7999 m_cpt_xram_rsp_fsm_trt_used++; 7419 8000 break; 7420 8001 … … 7424 8005 (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) 7425 8006 { 8007 8008 if (r_cleanup_fsm.read() == CLEANUP_IXR_REQ) 8009 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 8010 8011 else if(r_read_fsm.read() == READ_TRT_LOCK) 8012 r_alloc_trt_fsm = ALLOC_TRT_READ; 8013 8014 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) || 8015 (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) 8016 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 8017 8018 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) || 8019 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 8020 r_alloc_trt_fsm = ALLOC_TRT_CAS; 8021 8022 else if((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) && 8023 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 8024 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 8025 8026 else 8027 m_cpt_trt_unused++; 8028 } 8029 else 8030 m_cpt_ixr_fsm_trt_used++; 8031 break; 8032 8033 //////////////////////// 8034 case ALLOC_TRT_CLEANUP: 8035 if(r_ixr_rsp_fsm.read() != CLEANUP_IXR_REQ) 8036 { 7426 8037 if(r_read_fsm.read() == READ_TRT_LOCK) 7427 8038 r_alloc_trt_fsm = ALLOC_TRT_READ; … … 7438 8049 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 7439 8050 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 8051 8052 else if((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || 8053 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 8054 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 7440 8055 } 7441 8056 break; … … 7488 8103 else if(r_config_fsm.read() == CONFIG_HEAP_REQ) 7489 8104 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 7490 } 8105 else 8106 m_cpt_heap_unused++; 8107 } 8108 else 8109 m_cpt_read_fsm_heap_used++; 7491 8110 break; 7492 8111 … … 7511 8130 else if(r_read_fsm.read() == READ_HEAP_REQ) 7512 8131 r_alloc_heap_fsm = ALLOC_HEAP_READ; 7513 } 8132 8133 else 8134 m_cpt_heap_unused++; 8135 } 8136 else 8137 m_cpt_write_fsm_heap_used++; 7514 8138 break; 7515 8139 … … 7534 8158 else if(r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) 7535 8159 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 7536 } 8160 8161 else 8162 m_cpt_heap_unused++; 8163 } 8164 else 8165 m_cpt_cas_fsm_heap_used++; 7537 8166 break; 7538 8167 … … 7558 8187 else if(r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) 7559 8188 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 7560 } 8189 8190 else 8191 m_cpt_heap_unused++; 8192 } 8193 else 8194 m_cpt_cleanup_fsm_heap_used++; 7561 8195 break; 7562 8196 … … 7603 8237 if(r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 7604 8238 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 7605 } 8239 else 8240 m_cpt_heap_unused++; 8241 } 8242 else 8243 m_cpt_xram_rsp_fsm_heap_used++; 7606 8244 break; 7607 8245 … … 7663 8301 //////////////////////////////////////////////////////////////////////////////////// 7664 8302 8303 /* 8304 if(cc_receive_to_cleanup_fifo_put) 8305 { 8306 if(cc_receive_to_cleanup_fifo_get) 8307 { 8308 m_cc_receive_to_cleanup_fifo.put_and_get( ( (uint64_t)(p_dspin_in.eop.read() & 0x1 ) << 32 ) | p_dspin_in.data.read()); 8309 } 8310 else // TODO PAS METTRE 32 en DUR !!!! 8311 { 8312 m_cc_receive_to_cleanup_fifo.simple_put( ( (uint64_t)(p_dspin_in.eop.read() & 0x1 ) << 32 ) | p_dspin_in.data.read()); 8313 //m_cc_receive_to_cleanup_fifo.simple_put(p_dspin_in.data.read()); 8314 } 8315 } 8316 else 8317 { 8318 if(cc_receive_to_cleanup_fifo_get) 8319 { 8320 m_cc_receive_to_cleanup_fifo.simple_get(); 8321 } 8322 } 8323 */ 7665 8324 m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get, 7666 8325 cc_receive_to_cleanup_fifo_put, 7667 p_dspin_in.data.read() ); 7668 8326 ( (uint64_t)(p_dspin_in.eop.read() & 0x1 ) << 32 ) | p_dspin_in.data.read() ); 7669 8327 //////////////////////////////////////////////////////////////////////////////////// 7670 8328 // CC_RECEIVE to MULTI_ACK FIFO … … 7814 8472 p_vci_ixr.trdid = r_xram_rsp_to_ixr_cmd_trdid.read(); 7815 8473 p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words-2)); 8474 } 8475 /*ODCCP*/ 8476 else if (r_ixr_cmd_fsm.read() == IXR_CMD_CLEANUP_DATA) 8477 { 8478 p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; 8479 p_vci_ixr.cmdval = true; 8480 p_vci_ixr.address = (addr_t)((r_cleanup_to_ixr_cmd_nline.read() * m_words + 8481 r_ixr_cmd_cpt.read()) * 4); 8482 8483 if(r_cleanup_to_ixr_cmd_l1_dirty_ncc.read()) // if cleanup data contains data, we use cleanup_data buffer (cleanup dirty) 8484 { 8485 p_vci_ixr.wdata = ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | 8486 ((wide_data_t)(r_cleanup_to_ixr_cmd_data[r_ixr_cmd_cpt.read() + 1].read()) << 32)); 8487 } 8488 else // if cleanup data doesnt contain data, we use xram_rsp_data buffer (cleanup not dirty) 8489 { 8490 p_vci_ixr.wdata = ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read()) | 8491 ((wide_data_t)(r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read() + 1].read()) << 32)); 8492 } 8493 8494 p_vci_ixr.trdid = r_cleanup_to_ixr_cmd_trdid.read(); 8495 p_vci_ixr.eop = (r_ixr_cmd_cpt == (m_words - 2)); 7816 8496 } 7817 8497 else
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