Changeset 477 for branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
- Timestamp:
- Jul 26, 2013, 5:03:12 PM (11 years ago)
- Location:
- branches/RWT
- Files:
-
- 2 added
- 1 edited
- 2 copied
Legend:
- Unmodified
- Added
- Removed
-
branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r473 r477 35 35 #define DEBUG_ICACHE 1 36 36 #define DEBUG_CMD 0 37 #define INSTRUMENTATION 1 37 38 38 39 namespace soclib { … … 87 88 "DCACHE_XTN_IT_INVAL", 88 89 "DCACHE_XTN_DC_FLUSH", 90 "DCACHE_XTN_DC_FLUSH_DATA", 89 91 "DCACHE_XTN_DC_FLUSH_GO", 90 92 "DCACHE_XTN_DC_INVAL_VA", … … 92 94 "DCACHE_XTN_DC_INVAL_END", 93 95 "DCACHE_XTN_DC_INVAL_GO", 96 "DCACHE_XTN_DC_INVAL_DATA", 94 97 "DCACHE_XTN_DT_INVAL", 95 98 … … 99 102 "DCACHE_MISS_SELECT", 100 103 "DCACHE_MISS_CLEAN", 104 "DCACHE_MISS_DATA", 101 105 "DCACHE_MISS_WAIT", 102 106 "DCACHE_MISS_DATA_UPDT", … … 110 114 "DCACHE_CC_UPDT", 111 115 "DCACHE_CC_INVAL", 116 "DCACHE_CC_INVAL_DATA", 112 117 113 118 "DCACHE_INVAL_TLB_SCAN", … … 174 179 "CC_SEND_CLEANUP_1", 175 180 "CC_SEND_CLEANUP_2", 181 "CC_SEND_CLEANUP_DATA_UPDT", 176 182 "CC_SEND_MULTI_ACK", 177 183 }; … … 367 373 r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth 368 374 r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth 375 r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth 376 r_cc_send_data_fifo("r_cc_send_data_fifo", 2), 369 377 370 378 r_cc_send_fsm("r_cc_send_fsm"), … … 424 432 r_mmu_release = (uint32_t)(1 << 16) | 0x1; 425 433 426 r_dcache_in_tlb = new bool[dcache_ways*dcache_sets]; 427 r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets]; 434 ////////////////////MODIFIED/////////////////////////////// 435 //r_dcache_in_tlb = new bool[dcache_ways*dcache_sets]; 436 //r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets]; 437 r_dcache_content_state = new int [dcache_ways*dcache_sets]; 438 r_dcache_dirty_word = new int [dcache_ways*dcache_sets*dcache_words]; 439 /////////////////////////////////////////////////////////// 440 428 441 429 442 SC_METHOD(transition); … … 450 463 ///////////////////////////////////// 451 464 { 452 delete [] r_dcache_in_tlb; 453 delete [] r_dcache_contains_ptd; 465 ////////////MODIFIED///////////// 466 //delete [] r_dcache_in_tlb; 467 //delete [] r_dcache_contains_ptd; 468 delete [] r_dcache_content_state; 469 delete [] r_dcache_dirty_word; 470 ///////////////////////////////// 454 471 } 455 472 … … 472 489 // b4 : dtlb trace 473 490 // b5 : itlb trace 474 475 491 std::cout << std::dec << "PROC " << name() << std::endl; 476 492 … … 479 495 std::cout << " " << m_dreq << std::endl; 480 496 std::cout << " " << m_drsp << std::endl; 497 498 /**/std::cout << r_iss << std::endl; 481 499 482 500 std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()] … … 562 580 } 563 581 564 /* 582 565 583 //////////////////////// 566 584 tmpl(void)::print_stats() … … 569 587 float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); 570 588 std::cout << name() << std::endl 571 << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl 572 << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl 573 << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl 574 << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl 575 << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 576 << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl 577 << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 578 << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl 579 << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl 580 << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 581 << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 582 << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl 583 << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl 584 << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl 585 << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl 586 << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl 587 << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl 588 << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl 589 << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl 590 << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl 591 << "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl 592 << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl 593 << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl 594 << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl 595 << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl 596 << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl 597 << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl 598 << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl 599 << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl 600 << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl 601 << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl 602 << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl 603 << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl 604 << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl 605 << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl 606 << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl 607 << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl 608 << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl 609 << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; 589 << "- CPI = " << std::dec <<(float)m_cpt_total_cycles/run_cycles << std::endl 590 << "- READ RATE = " << (float)m_cpt_data_read/run_cycles << std::endl 591 << "- WRITE RATE = " << (float)m_cpt_data_write/run_cycles << std::endl 592 << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl 593 << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl 594 << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl 595 << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 596 << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl 597 << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl 598 << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl 599 << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl 600 << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl 601 << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl 602 << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl 603 << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl 604 << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl 605 << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl 606 << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl 607 << "- ITLB HIT IN DCACHE RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl 608 << "- DTLB HIT IN DCACHE RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl 609 //<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl 610 << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl 611 << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl 612 << "- NB CC UPDATE DATA = " << m_cpt_cc_update_dcache << std::endl 613 << "- NB CC INVAL DATA = " << m_cpt_cc_inval_dcache << std::endl 614 << "- NB CC INVAL INS = " << m_cpt_cc_inval_icache << std::endl 615 << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl 616 << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_dcache << std::endl 617 << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_dcache << std::endl 618 << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_icache << std::endl 619 << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl 620 << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl 621 << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl 622 << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl 623 << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl 624 << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl 625 << "- NB WRITE TRANSACTION = " << m_cpt_write_transaction << std::endl 626 << "- NB WRITE WORDS VCI = " << m_length_write_transaction << std::endl 627 << "- NB WRITE PROC = " << m_cpt_data_write << std::endl 628 << "- NB WRITE BACK = " << m_cpt_data_write_back << std::endl 629 << "- NB WRITE BACK COHERENCE = " << m_cpt_data_cleanup << std::endl 630 << "- NB DATA SC = " << m_cpt_data_sc << std::endl 631 << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl 632 << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl 633 << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl 634 635 << "- DMISS TRANSACTION = " << m_cpt_dmiss_transaction << std::endl 636 << "- DUNC TRANSACTION = " << m_cpt_dunc_transaction << std::endl 637 << "- LL TRANSACTION = " << m_cpt_ll_transaction << std::endl 638 << "- CLEANUP DATA NOT DIRTY = " << m_cpt_cleanup_data_not_dirty << std::endl 639 << "- CLEANUP DATA DIRTY WORD = " << m_cpt_cleanup_data_dirty_word << std::endl; 610 640 } 611 641 … … 624 654 625 655 m_cpt_frz_cycles = 0; 626 m_cpt_dcache_frz_cycles = 0;656 // m_cpt_dcache_frz_cycles = 0; 627 657 m_cpt_total_cycles = 0; 628 658 629 m_cpt_read = 0;630 m_cpt_write = 0;659 // m_cpt_read = 0; 660 // m_cpt_write = 0; 631 661 m_cpt_data_miss = 0; 632 662 m_cpt_ins_miss = 0; … … 692 722 m_cost_dtlb_sc_dirty_transaction = 0; 693 723 694 m_cpt_cc_update_data = 0;695 m_cpt_cc_inval_ins = 0;696 m_cpt_cc_inval_data = 0;724 // m_cpt_cc_update_data = 0; 725 // m_cpt_cc_inval_ins = 0; 726 // m_cpt_cc_inval_data = 0; 697 727 m_cpt_cc_broadcast = 0; 698 728 … … 704 734 m_cpt_cc_cleanup_data = 0; 705 735 m_cpt_cc_cleanup_ins = 0; 736 737 m_cpt_cleanup_data_not_dirty = 0; 738 m_cpt_cleanup_data_dirty_word = 0; 739 706 740 } 707 741 708 */ 742 709 743 710 744 ///////////////////////// … … 734 768 for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++) 735 769 { 736 r_dcache_in_tlb[i] = false; 737 r_dcache_contains_ptd[i] = false; 770 // MODIFIED 771 //r_dcache_in_tlb[i] = false; 772 //r_dcache_contains_ptd[i] = false; 773 r_dcache_content_state[i] = LINE_CACHE_DATA_NOT_DIRTY; 774 r_dcache_dirty_word[i] = 0; 738 775 } 739 776 … … 741 778 r_vci_rsp_fifo_icache.init(); 742 779 r_vci_rsp_fifo_dcache.init(); 780 r_cc_send_data_fifo.init(); 743 781 744 782 // ICACHE & DCACHE activated … … 805 843 m_debug_previous_d_hit = false; 806 844 m_debug_activated = false; 845 846 // SPECIAL REGISTERS ODCCP 847 r_dcache_cc_cleanup_updt_data = false; 848 r_dcache_cc_cleanup_line_ncc = false; 849 r_dcache_miss_victim_no_coherence = false; 850 r_dcache_line_no_coherence = false; 851 r_cc_send_cpt_word = 0; 852 r_dcache_miss_data_cpt = 0; 853 r_dcache_miss_data_addr = 0; 807 854 808 855 // activity counters … … 821 868 822 869 m_cpt_data_miss = 0; 870 m_cpt_data_write = 0; 871 m_cpt_data_sc = 0; 872 m_cpt_data_write_back = 0; 873 m_cpt_data_cleanup = 0; 874 m_cpt_cleanup_data_not_dirty = 0; 823 875 m_cpt_ins_miss = 0; 824 876 m_cpt_unc_read = 0; … … 879 931 m_cpt_cc_cleanup_data = 0; 880 932 m_cpt_cc_cleanup_ins = 0; 933 934 m_cpt_cleanup_data_not_dirty = 0; 935 m_cpt_cleanup_data_dirty_word = 0; 881 936 882 937 m_cpt_itlbmiss_transaction = 0; … … 926 981 bool vci_rsp_fifo_dcache_put = false; 927 982 uint32_t vci_rsp_fifo_dcache_data = 0; 983 bool vci_rsp_fifo_rpktid_get = false; 984 bool vci_rsp_fifo_rpktid_put = false; 985 bool vci_rsp_fifo_rpktid = false; 986 987 // FIFO for cleanup data updt 988 bool cleanup_data_updt_fifo_dcache_get = false; 989 bool cleanup_data_updt_fifo_dcache_put = false; 990 uint32_t cleanup_data_updt_fifo_dcache_data = 0; 928 991 929 992 // updt fifo … … 935 998 936 999 #ifdef INSTRUMENTATION 937 m_cpt_fsm_dcache [r_dcache_fsm.read()] ++;938 m_cpt_fsm_icache [r_icache_fsm.read()] ++;939 m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;940 m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;941 m_cpt_fsm_ tgt [r_tgt_fsm.read()] ++;942 m_cpt_fsm_c leanup [r_cleanup_cmd_fsm.read()] ++;1000 m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++; 1001 m_cpt_fsm_icache [r_icache_fsm.read() ] ++; 1002 m_cpt_fsm_cmd [r_vci_cmd_fsm.read() ] ++; 1003 m_cpt_fsm_rsp [r_vci_rsp_fsm.read() ] ++; 1004 m_cpt_fsm_cc_send [r_cc_send_fsm.read() ] ++; 1005 m_cpt_fsm_cc_receive [r_cc_receive_fsm.read()] ++; 943 1006 #endif 944 1007 … … 1069 1132 else 1070 1133 { 1071 r_icache_vci_paddr = ( paddr_t)r_mmu_word_hi.read() << 32 |1134 r_icache_vci_paddr = (uint64_t)r_mmu_word_hi.read() << 32 | 1072 1135 (paddr_t)r_mmu_word_lo.read(); 1073 1136 } … … 1106 1169 1107 1170 #ifdef INSTRUMENTATION 1108 m_cpt_i tlb_read++;1171 m_cpt_ins_tlb_read++; 1109 1172 #endif 1110 1173 tlb_hit = r_itlb.translate( m_ireq.addr, … … 1181 1244 1182 1245 #ifdef INSTRUMENTATION 1183 m_cpt_i tlb_miss++;1246 m_cpt_ins_tlb_miss++; 1184 1247 #endif 1185 1248 r_icache_fsm = ICACHE_TLB_WAIT; … … 1199 1262 1200 1263 #ifdef INSTRUMENTATION 1201 m_cpt_i cache_miss++;1264 m_cpt_ins_miss++; 1202 1265 #endif 1203 1266 // we request a VCI transaction … … 1340 1403 &state ); 1341 1404 1342 if ( state == CACHE_SLOT_STATE_VALID ) // inval required1405 if ( state == CACHE_SLOT_STATE_VALID_CC ) // inval required 1343 1406 { 1344 1407 // request cleanup … … 1421 1484 1422 1485 #ifdef INSTRUMENTATION 1423 m_cpt_i tlb_read++;1486 m_cpt_ins_tlb_read++; 1424 1487 #endif 1425 1488 hit = r_itlb.translate(r_dcache_save_wdata.read(), … … 1441 1504 1442 1505 #ifdef INSTRUMENTATION 1443 m_cpt_i tlb_miss++;1506 m_cpt_ins_tlb_miss++; 1444 1507 #endif 1445 1508 r_icache_tlb_miss_req = true; … … 1468 1531 &word); 1469 1532 1470 if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done1533 if ( state == CACHE_SLOT_STATE_VALID_CC ) // inval to be done 1471 1534 { 1472 1535 r_icache_miss_way = way; … … 1751 1814 r_icache_miss_way.read(), 1752 1815 r_icache_miss_set.read(), 1753 CACHE_SLOT_STATE_VALID );1816 CACHE_SLOT_STATE_VALID_CC ); 1754 1817 #if DEBUG_ICACHE 1755 1818 if ( m_debug_activated ) … … 1924 1987 r_icache_cc_set = set; 1925 1988 1926 if ( state == CACHE_SLOT_STATE_VALID ) // hit1989 if ( state == CACHE_SLOT_STATE_VALID_CC) // hit 1927 1990 { 1928 1991 // need to update the cache state … … 2136 2199 m_drsp.error = false; 2137 2200 m_drsp.rdata = 0; 2201 //if(m_cpt_total_cycles % 1000000 == 0 ) r_dcache.printTrace(); 2138 2202 2139 2203 switch ( r_dcache_fsm.read() ) … … 2191 2255 bool wbuf_request = false; // request WBUF write in P1 stage 2192 2256 2257 2193 2258 // physical address computation : systematic DTLB access if activated) 2194 2259 if ( m_dreq.valid ) … … 2203 2268 &tlb_set ); 2204 2269 #ifdef INSTRUMENTATION 2205 m_cpt_d tlb_read++;2270 m_cpt_data_tlb_read++; 2206 2271 #endif 2207 2272 } … … 2211 2276 // we take into account the paddr extension 2212 2277 if (vci_param::N > 32) 2213 paddr = paddr | (( paddr_t)(r_dcache_paddr_ext.read()) << 32);2278 paddr = paddr | ((uint64_t)(r_dcache_paddr_ext.read()) << 32); 2214 2279 } 2215 2280 } // end physical address computation … … 2268 2333 size_t way = r_dcache_save_cache_way.read(); 2269 2334 size_t set = r_dcache_save_cache_set.read(); 2270 2271 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 2335 // MODIFIED 2336 //if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 2337 //{ 2338 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 2272 2339 { 2273 2340 tlb_inval_required = true; … … 2275 2342 r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>> 2276 2343 (uint32_log2(m_dcache_words<<2)); 2277 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 2278 } 2279 else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 2344 // MODIFIED RWT: DIRTY 2345 //r_dcache_in_tlb[way*m_dcache_sets+set] = false; 2346 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 2347 } 2348 // MODIFIED 2349 //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 2350 //{ 2351 else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 2280 2352 { 2281 2353 r_itlb.reset(); 2282 2354 r_dtlb.reset(); 2283 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 2355 // MODIFIED 2356 //r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 2357 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 2284 2358 } 2285 2359 … … 2312 2386 r_dcache_save_wdata.read(), 2313 2387 r_dcache_save_cacheable.read() ); 2314 #ifdef INSTRUMENTATION2388 /*#ifdef INSTRUMENTATION 2315 2389 m_cpt_wbuf_write++; 2316 #endif 2390 #endif*/ 2317 2391 if ( not wok ) // miss if write buffer full 2318 2392 { … … 2526 2600 else 2527 2601 { 2528 r_dcache_save_paddr = ( paddr_t)r_mmu_word_hi.read() << 32 |2602 r_dcache_save_paddr = (uint64_t)r_mmu_word_hi.read() << 32 | 2529 2603 (paddr_t)r_mmu_word_lo.read(); 2530 2604 } … … 2623 2697 if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; 2624 2698 else cacheable = tlb_flags.c; 2625 2626 2699 // access rights checking 2627 2700 if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) … … 2693 2766 { 2694 2767 #ifdef INSTRUMENTATION 2695 m_cpt_dcache_miss++; 2696 #endif 2768 m_cpt_data_miss++; 2769 #endif 2770 /*ODCCP*/ 2771 //std::cout << "\t\t\t\t\tCACHE MISS NEED READ for : " << name() << std::endl; 2697 2772 // request a VCI DMISS transaction 2698 2773 r_dcache_vci_paddr = paddr; … … 2723 2798 m_cpt_data_read++; 2724 2799 #endif 2800 /*if ((tlb_flags.s == 0) and (r_mmu_mode.read() & DATA_TLB_MASK) and (cache_state == CACHE_SLOT_STATE_VALID_CC)) 2801 { 2802 //ODCCP 2803 std::cout << "READ NO COHERENCE on " << name() << " | paddr = " << std::hex << paddr << std::dec << " | way = " << cache_way << " | set = " << cache_set << " | at cycle : "<< m_cpt_total_cycles << std::endl; 2804 r_dcache.write_dir(cache_way, 2805 cache_set, 2806 CACHE_SLOT_STATE_VALID_NCC); 2807 }*/ 2725 2808 // returns data to processor 2726 2809 m_drsp.valid = true; … … 2765 2848 r_dcache_ll_rsp_count = 0; 2766 2849 r_dcache_fsm = DCACHE_LL_WAIT; 2850 /*ODCCP*/ 2851 //std::cout << "LL on " << name() << " | paddr = " << std::hex << paddr << std::dec << " | at cycle : " << m_cpt_total_cycles << std::endl; 2767 2852 2768 2853 }// end LL … … 2806 2891 // response to processor 2807 2892 m_drsp.valid = true; 2808 2809 2893 // activating P1 stage 2810 wbuf_request = true; 2811 updt_request = (cache_state == CACHE_SLOT_STATE_VALID); 2894 if( (cache_state != CACHE_SLOT_STATE_ZOMBI )&&(cache_state != CACHE_SLOT_STATE_EMPTY )&&(cacheable) ) 2895 { 2896 wbuf_request = (cache_state == CACHE_SLOT_STATE_VALID_CC); //write to L2 only if CC 2897 updt_request = true; 2898 if (cache_state == CACHE_SLOT_STATE_VALID_NCC) 2899 { 2900 if (r_dcache_content_state[cache_way*m_dcache_sets+cache_set] == LINE_CACHE_DATA_NOT_DIRTY) 2901 { 2902 r_dcache_content_state[cache_way*m_dcache_sets+cache_set] = LINE_CACHE_DATA_DIRTY; 2903 } 2904 r_dcache_dirty_word[(cache_way*m_dcache_sets +cache_set)*m_dcache_words+cache_word] = 1;//dirty bit with word granularity (only for stats) 2905 m_cpt_data_write_back ++; 2906 } 2907 } 2908 else 2909 { 2910 wbuf_request = true; 2911 updt_request = false; 2912 } 2812 2913 } 2813 2914 } // end WRITE … … 2978 3079 m_cpt_dcache_dir_read++; 2979 3080 #endif 2980 if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache 3081 /*ODCCP*/ 3082 // assert((cache_state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_TLB_PTE1_GET : IMPOSSIBLE NCC HERE"); 3083 // if ( cache_state == CACHE_SLOT_STATE_VALID_CC ) // hit in dcache 3084 if (( cache_state == CACHE_SLOT_STATE_VALID_NCC ) or ( cache_state == CACHE_SLOT_STATE_VALID_CC )) 2981 3085 { 2982 3086 if ( not (entry & PTE_V_MASK) ) // unmapped … … 3015 3119 { 3016 3120 // mark the cache line ac containing a PTD 3017 r_dcache_contains_ptd[m_dcache_sets*way+set] = true; 3121 //MODIFIED 3122 //r_dcache_contains_ptd[m_dcache_sets*way+set] = true; 3123 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_CONTAINS_PTD; 3018 3124 3019 3125 // register bypass … … 3050 3156 else // PTE1 : we must update the TLB 3051 3157 { 3052 r_dcache_in_tlb[m_icache_sets*way+set] = true; 3158 // MODIFIED 3159 //r_dcache_in_tlb[m_icache_sets*way+set] = true; 3160 r_dcache_content_state[m_icache_sets*way+set] = LINE_CACHE_IN_TLB; 3053 3161 r_dcache_tlb_pte_flags = entry; 3054 3162 r_dcache_tlb_cache_way = way; … … 3108 3216 &set ); 3109 3217 #ifdef INSTRUMENTATION 3110 m_cpt_i tlb_read++;3218 m_cpt_ins_tlb_read++; 3111 3219 #endif 3112 3220 } … … 3118 3226 &set ); 3119 3227 #ifdef INSTRUMENTATION 3120 m_cpt_d tlb_read++;3228 m_cpt_data_tlb_read++; 3121 3229 #endif 3122 3230 } … … 3194 3302 nline ); 3195 3303 #ifdef INSTRUMENTATION 3196 m_cpt_i tlb_write++;3304 m_cpt_ins_tlb_update_acc++; 3197 3305 #endif 3198 3306 … … 3218 3326 nline ); 3219 3327 #ifdef INSTRUMENTATION 3220 m_cpt_d tlb_write++;3328 m_cpt_data_tlb_update_acc++; 3221 3329 #endif 3222 3330 … … 3268 3376 } 3269 3377 3270 uint32_t pte_flags ;3271 uint32_t pte_ppn ;3272 size_t way ;3273 size_t set ;3274 size_t word ;3275 int cache_state ;3378 uint32_t pte_flags = 0; 3379 uint32_t pte_ppn = 0; 3380 size_t way = 0; 3381 size_t set = 0; 3382 size_t word = 0; 3383 int cache_state = 0; 3276 3384 3277 3385 r_dcache.read( r_dcache_tlb_paddr.read(), … … 3286 3394 m_cpt_dcache_dir_read++; 3287 3395 #endif 3288 if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache 3396 /*ODCCP*/ 3397 // assert((cache_state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_TLB_PTE2_GET : IMPOSSIBLE NCC HERE"); 3398 // if (cache_state == CACHE_SLOT_STATE_VALID_CC) // hit in dcache 3399 if ((cache_state == CACHE_SLOT_STATE_VALID_CC) or (cache_state == CACHE_SLOT_STATE_VALID_NCC)) 3289 3400 { 3290 3401 if ( not (pte_flags & PTE_V_MASK) ) // unmapped … … 3318 3429 else // mapped : we must update the TLB 3319 3430 { 3320 r_dcache_in_tlb[m_dcache_sets*way+set] = true; 3431 // MODIFIED 3432 //r_dcache_in_tlb[m_dcache_sets*way+set] = true; 3433 r_dcache_content_state[m_dcache_sets*way+set] = LINE_CACHE_IN_TLB; 3321 3434 r_dcache_tlb_pte_flags = pte_flags; 3322 3435 r_dcache_tlb_pte_ppn = pte_ppn; … … 3383 3496 &set ); 3384 3497 #ifdef INSTRUMENTATION 3385 m_cpt_i tlb_read++;3498 m_cpt_ins_tlb_read++; 3386 3499 #endif 3387 3500 } … … 3393 3506 &set ); 3394 3507 #ifdef INSTRUMENTATION 3395 m_cpt_d tlb_read++;3508 m_cpt_data_tlb_read++; 3396 3509 #endif 3397 3510 } … … 3435 3548 // As long as this computation is not done, all access are local. 3436 3549 3550 int state; 3551 size_t way; 3552 size_t set; 3553 size_t word; 3554 r_dcache.read_dir(r_dcache_tlb_paddr.read(), 3555 &state, 3556 &way, 3557 &set, 3558 &word); 3559 r_cas_islocal = (state == CACHE_SLOT_STATE_VALID_NCC);//do not check L2 if NCC: the CAS is necessarily a success 3560 r_cas_local_way = way; 3561 r_cas_local_set = set; 3562 r_cas_local_word = word; 3563 3437 3564 if ( local ) // local access 3438 3565 { … … 3470 3597 nline ); 3471 3598 #ifdef INSTRUMENTATION 3472 m_cpt_i tlb_write++;3599 m_cpt_ins_tlb_update_acc++; 3473 3600 #endif 3474 3601 … … 3494 3621 nline ); 3495 3622 #ifdef INSTRUMENTATION 3496 m_cpt_d tlb_write++;3623 m_cpt_data_tlb_update_acc++; 3497 3624 #endif 3498 3625 … … 3528 3655 case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit 3529 3656 { 3657 uint32_t way = r_cas_local_way.read(); 3658 uint32_t set = r_cas_local_set.read(); 3659 uint32_t word = r_cas_local_word.read(); 3660 paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); 3530 3661 #if DEBUG_DCACHE 3531 3662 if ( m_debug_activated ) … … 3535 3666 } 3536 3667 #endif 3537 // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set 3538 r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); 3539 3540 // checking llsc reservation buffer 3541 if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() ) 3542 r_dcache_llsc_valid = false; 3543 3544 // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state 3545 r_dcache_vci_cas_req = true; 3546 r_dcache_fsm = DCACHE_TLB_LR_WAIT; 3668 3669 if (r_cas_islocal.read()) 3670 { 3671 r_dcache.write(way, 3672 set, 3673 word, 3674 r_dcache_vci_cas_new.read()); 3675 //compteur dirty 3676 r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 1; 3677 3678 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 3679 { 3680 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 3681 r_dcache_tlb_inval_line = nline; 3682 r_dcache_tlb_inval_set = 0; 3683 r_dcache_fsm_scan_save = DCACHE_TLB_RETURN; 3684 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 3685 break; 3686 } 3687 3688 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 3689 { 3690 r_itlb.reset(); 3691 r_dtlb.reset(); 3692 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 3693 3694 #if DEBUG_DCACHE 3695 if ( m_debug_activated ) 3696 { 3697 std::cout << " <PROC " << name() 3698 << " DCACHE_TLB_LR_UPDT> Flush DTLB & ITLB" << std::endl; 3699 } 3700 #endif 3701 } 3702 3703 r_dcache_fsm = DCACHE_TLB_RETURN; 3704 } 3705 else 3706 { 3707 // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set 3708 r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); 3709 3710 // checking llsc reservation buffer 3711 if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() ) 3712 r_dcache_llsc_valid = false; 3713 3714 // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state 3715 r_dcache_vci_cas_req = true; 3716 r_dcache_fsm = DCACHE_TLB_LR_WAIT; 3717 } 3547 3718 break; 3548 3719 } … … 3739 3910 &tag, 3740 3911 &state ); 3741 3742 if ( state == CACHE_SLOT_STATE_VALID ) // inval required 3912 /*ODCCP*/ 3913 3914 if ( state == CACHE_SLOT_STATE_VALID_CC ) // inval required 3743 3915 { 3744 3916 // request cleanup … … 3751 3923 r_dcache_miss_way = way; 3752 3924 r_dcache_miss_set = set; 3925 r_dcache_cc_cleanup_line_ncc = false; 3926 r_dcache_cc_cleanup_updt_data = false; 3753 3927 r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; 3928 } 3929 else if ( state == CACHE_SLOT_STATE_VALID_NCC) 3930 { 3931 // request cleanup 3932 r_dcache_cc_send_req = true; 3933 r_dcache_cc_send_nline = tag * m_dcache_sets + set; 3934 r_dcache_cc_send_way = way; 3935 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 3936 3937 // goes to DCACHE_XTN_DC_FLUSH_GO to inval directory 3938 r_dcache_miss_way = way; 3939 r_dcache_miss_set = set; 3940 r_dcache_cc_cleanup_line_ncc = true; 3941 //if (r_dcache_content_state[m_dcache_sets*way+set] != LINE_CACHE_DATA_NOT_DIRTY)//Must send data in the cleanup 3942 if (true)//Must send data in the cleanup 3943 { 3944 r_dcache_xtn_flush_addr_data = (tag * m_dcache_sets + set) * m_dcache_words * 4; 3945 r_dcache_xtn_flush_data_cpt = 0; 3946 r_dcache_cc_cleanup_updt_data = true; 3947 for (size_t w = 0; w< m_dcache_words; w++) 3948 { 3949 m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; 3950 } 3951 r_dcache_fsm = DCACHE_XTN_DC_FLUSH_DATA; 3952 } 3953 else 3954 { 3955 r_dcache_cc_cleanup_updt_data = false; 3956 r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; 3957 } 3754 3958 } 3755 3959 else if ( r_dcache_flush_count.read() == … … 3768 3972 break; 3769 3973 } 3974 3975 //////////////////////////// 3976 case DCACHE_XTN_DC_FLUSH_DATA: 3977 { 3978 uint32_t rdata; 3979 size_t way; 3980 size_t set; 3981 size_t word; 3982 r_dcache.read_neutral(r_dcache_xtn_flush_addr_data.read(), 3983 &rdata, 3984 &way, 3985 &set, 3986 &word); 3987 if(r_cc_send_data_fifo.wok()) 3988 { 3989 r_dcache_xtn_flush_addr_data = r_dcache_xtn_flush_addr_data.read() + 4; 3990 3991 cleanup_data_updt_fifo_dcache_put = true; 3992 cleanup_data_updt_fifo_dcache_data = rdata; 3993 3994 r_dcache_xtn_flush_data_cpt = r_dcache_xtn_flush_data_cpt + 1; 3995 if(r_dcache_xtn_flush_data_cpt.read() == (m_dcache_words - 1)) 3996 { 3997 r_dcache_xtn_flush_data_cpt = 0; 3998 r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; 3999 } 4000 } 4001 break; 4002 } 4003 3770 4004 //////////////////////////// 3771 4005 case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state … … 3776 4010 size_t set = r_dcache_miss_set.read(); 3777 4011 3778 r_dcache_in_tlb[m_dcache_sets*way+set] = false; 3779 r_dcache_contains_ptd[m_dcache_sets*way+set] = false; 4012 // MODIFIED 4013 //r_dcache_in_tlb[m_dcache_sets*way+set] = false; 4014 //r_dcache_contains_ptd[m_dcache_sets*way+set] = false; 4015 r_dcache_content_state[m_dcache_sets*way+set] = LINE_CACHE_DATA_DIRTY; 3780 4016 3781 4017 #ifdef INSTRUMENTATION … … 3820 4056 3821 4057 #ifdef INSTRUMENTATION 3822 m_cpt_d tlb_read++;4058 m_cpt_data_tlb_read++; 3823 4059 #endif 3824 4060 hit = r_dtlb.translate( r_dcache_save_wdata.read(), … … 3840 4076 3841 4077 #ifdef INSTRUMENTATION 3842 m_cpt_d tlb_miss++;4078 m_cpt_data_tlb_miss++; 3843 4079 #endif 3844 4080 r_dcache_tlb_ins = false; // dtlb … … 3877 4113 &set, 3878 4114 &word ); 3879 3880 if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done 3881 { 3882 r_dcache_xtn_way = way; 3883 r_dcache_xtn_set = set; 3884 r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; 4115 /*ODCCP*/ 4116 //assert((state != CACHE_SLOT_STATE_VALID_NCC) and "NOT YET DONE"); 4117 if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) // inval to be done 4118 { 4119 r_dcache_xtn_way = way; 4120 r_dcache_xtn_set = set; 4121 r_dcache_xtn_state = state; 4122 r_dcache_xtn_data_addr = r_dcache_save_paddr.read()&~0x3F; 4123 4124 if( (state == CACHE_SLOT_STATE_VALID_NCC) and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) ) 4125 { 4126 m_cpt_cleanup_data_not_dirty ++; 4127 } 4128 r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; 4129 3885 4130 } 3886 4131 else // miss : nothing to do … … 3896 4141 << " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex 3897 4142 << " / PADDR = " << r_dcache_save_paddr.read() << std::dec 3898 << " / HIT = " << ( state == CACHE_SLOT_STATE_VALID)4143 << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) 3899 4144 << " / SET = " << set 3900 4145 << " / WAY = " << way << std::endl; 4146 //r_dcache.printTrace(); 3901 4147 } 3902 4148 #endif … … 3910 4156 if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent 3911 4157 { 4158 int state = r_dcache_xtn_state.read(); 3912 4159 size_t way = r_dcache_xtn_way.read(); 3913 4160 size_t set = r_dcache_xtn_set.read(); … … 3917 4164 m_cpt_dcache_dir_write++; 3918 4165 #endif 3919 r_dcache.write_dir( way, 3920 set, 3921 CACHE_SLOT_STATE_ZOMBI ); 3922 3923 // request cleanup 3924 r_dcache_cc_send_req = true; 3925 r_dcache_cc_send_nline = nline; 3926 r_dcache_cc_send_way = way; 3927 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4166 // MODIFIER POUR DIRTY BIT // 4167 if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))// request cleanup 4168 { 4169 r_dcache_cc_send_req = true; 4170 r_dcache_cc_send_nline = nline; 4171 r_dcache_cc_send_way = way; 4172 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4173 if (state == CACHE_SLOT_STATE_VALID_CC) 4174 { 4175 r_dcache_cc_cleanup_line_ncc = false; 4176 r_dcache.write_dir( way, 4177 set, 4178 CACHE_SLOT_STATE_ZOMBI ); 4179 } 4180 else 4181 { 4182 r_dcache_cc_cleanup_line_ncc = true; 4183 //if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY)) //must send data 4184 if (true) //must send data 4185 { 4186 r_dcache_cc_cleanup_updt_data = true; 4187 for (size_t w = 0; w< m_dcache_words; w++) 4188 { 4189 m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; 4190 } 4191 r_dcache_fsm = DCACHE_XTN_DC_INVAL_DATA; 4192 break; 4193 } 4194 else 4195 { 4196 r_dcache_cc_cleanup_updt_data = false; 4197 r_dcache.write_dir( way, 4198 set, 4199 CACHE_SLOT_STATE_ZOMBI ); 4200 } 4201 if( (state == CACHE_SLOT_STATE_VALID_NCC) and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) ) 4202 m_cpt_cleanup_data_not_dirty ++; 4203 } 4204 } 4205 /*ODCCP*/ 3928 4206 3929 4207 // possible itlb & dtlb invalidate 3930 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 4208 // MODIFIED 4209 //if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 4210 //{ 4211 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 3931 4212 { 3932 4213 r_dcache_tlb_inval_line = nline; … … 3934 4215 r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END; 3935 4216 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 3936 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 3937 } 3938 else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 4217 // MODIFIED 4218 //r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4219 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 4220 } 4221 // MODIFIED 4222 //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 4223 //{ 4224 else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD) 3939 4225 { 3940 4226 r_itlb.reset(); 3941 4227 r_dtlb.reset(); 3942 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4228 // MODIFIED 4229 //r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4230 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 3943 4231 r_dcache_fsm = DCACHE_IDLE; 3944 4232 m_drsp.valid = true; … … 3961 4249 break; 3962 4250 } 4251 4252 /*ODCCP*/ 4253 ////////////////////////////// 4254 case DCACHE_XTN_DC_INVAL_DATA: //A verifier 4255 { 4256 4257 uint32_t rdata; 4258 size_t way; 4259 size_t set; 4260 size_t word; 4261 r_dcache.read_neutral(r_dcache_xtn_data_addr.read(), 4262 &rdata, 4263 &way, 4264 &set, 4265 &word); 4266 if(r_cc_send_data_fifo.wok()) 4267 { 4268 r_dcache_xtn_data_addr = r_dcache_xtn_data_addr.read() + 4; 4269 4270 cleanup_data_updt_fifo_dcache_put = true; 4271 cleanup_data_updt_fifo_dcache_data = rdata; 4272 4273 r_dcache_xtn_data_cpt = r_dcache_xtn_data_cpt.read() + 1; 4274 if(r_dcache_xtn_data_cpt.read() == (m_dcache_words - 1)) 4275 { 4276 r_dcache_xtn_state = CACHE_SLOT_STATE_ZOMBI; 4277 r_dcache_xtn_data_cpt = 0; 4278 r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; 4279 r_dcache.write_dir( way, 4280 set, 4281 CACHE_SLOT_STATE_ZOMBI ); 4282 } 4283 } 4284 break; 4285 } 4286 3963 4287 ////////////////////////////// 3964 4288 case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request … … 4001 4325 size_t set = 0; 4002 4326 paddr_t victim = 0; 4327 int state; 4003 4328 4004 4329 #ifdef INSTRUMENTATION … … 4011 4336 &found, 4012 4337 &cleanup ); 4338 state = r_dcache.get_cache_state(way,set); 4013 4339 4014 4340 if ( found ) … … 4026 4352 r_dcache_cc_send_way = way; 4027 4353 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4354 if( (state == CACHE_SLOT_STATE_VALID_NCC) )//and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) ) 4355 { 4356 //MODIFIER POUR DIRTY BIT // 4357 r_dcache_cc_cleanup_line_ncc = true; 4358 r_dcache_miss_data_addr = (victim*m_dcache_words)*4; 4359 //if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY))//must send data 4360 if (true)//must send data 4361 { 4362 r_dcache_cc_cleanup_updt_data = true; 4363 for (size_t w = 0; w< m_dcache_words; w++) 4364 { 4365 m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; 4366 } 4367 r_dcache_fsm = DCACHE_MISS_DATA; 4368 } 4369 else 4370 { 4371 r_dcache_cc_cleanup_updt_data = false; 4372 } 4373 4374 if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) 4375 m_cpt_cleanup_data_not_dirty ++; 4376 } 4377 4378 else 4379 { 4380 r_dcache_cc_cleanup_line_ncc = false; 4381 r_dcache_cc_cleanup_updt_data = false; 4382 } 4028 4383 } 4029 4384 else … … 4049 4404 } 4050 4405 /////////////////////// 4406 case DCACHE_MISS_DATA: 4407 { 4408 uint32_t rdata; 4409 size_t way; 4410 size_t set; 4411 size_t word; 4412 4413 r_dcache.read_neutral(r_dcache_miss_data_addr, 4414 &rdata, 4415 &way, 4416 &set, 4417 &word); 4418 if(r_cc_send_data_fifo.wok()) 4419 { 4420 r_dcache_miss_data_addr = r_dcache_miss_data_addr.read() + 4; 4421 4422 cleanup_data_updt_fifo_dcache_put = true; 4423 cleanup_data_updt_fifo_dcache_data = rdata; 4424 4425 r_dcache_miss_data_cpt = r_dcache_miss_data_cpt.read() + 1; 4426 if (r_dcache_miss_data_cpt.read() == m_dcache_words-1 ) 4427 { 4428 r_dcache_miss_data_cpt = 0; 4429 r_dcache_fsm = DCACHE_MISS_CLEAN; 4430 } 4431 } 4432 break; 4433 } 4434 /////////////////////// 4051 4435 case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state 4052 4436 // and possibly request itlb or dtlb invalidate … … 4074 4458 // if selective itlb & dtlb invalidate are required 4075 4459 // the miss response is not handled before invalidate completed 4076 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 4077 { 4078 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4460 // MODIFIED 4461 //if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 4462 //{ 4463 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 4464 { 4465 //MODIFIED 4466 //r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4467 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 4079 4468 r_dcache_tlb_inval_line = r_dcache_cc_send_nline; 4080 4469 r_dcache_tlb_inval_set = 0; … … 4082 4471 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4083 4472 } 4084 else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 4473 // MODIFIED 4474 //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 4475 //{ 4476 else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 4085 4477 { 4086 4478 r_itlb.reset(); 4087 4479 r_dtlb.reset(); 4088 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4480 // MODIFIED 4481 //r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4482 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 4089 4483 r_dcache_fsm = DCACHE_MISS_WAIT; 4090 4484 } … … 4101 4495 { 4102 4496 if ( m_dreq.valid) m_cost_data_miss_frz++; 4103 4104 4497 // coherence clack request (from DSPIN CLACK) 4105 4498 if ( r_dcache_clack_req.read() ) … … 4184 4577 if ( m_dreq.valid) m_cost_data_miss_frz++; 4185 4578 4186 if ( r_vci_rsp_fifo_dcache.rok() ) // one word available4579 if ( r_vci_rsp_fifo_dcache.rok() && r_vci_rsp_fifo_rpktid.rok()) // one word available 4187 4580 { 4188 4581 #ifdef INSTRUMENTATION … … 4205 4598 #endif 4206 4599 vci_rsp_fifo_dcache_get = true; 4600 4601 r_dcache_read_state = !r_vci_rsp_fifo_rpktid.read();//deduce the state (CC or NCC) from msb of pktid 4602 vci_rsp_fifo_rpktid_get = true; 4603 4604 4207 4605 r_dcache_miss_word = r_dcache_miss_word.read() + 1; 4208 4606 … … 4253 4651 r_dcache_cc_send_way = r_dcache_miss_way.read(); 4254 4652 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4653 r_dcache_cc_cleanup_updt_data = false; //the line is evicted at the very moment it arives, so it is not dirty 4654 r_dcache_cc_cleanup_line_ncc = !r_dcache_read_state.read(); 4255 4655 4256 4656 #ifdef INSTRUMENTATION … … 4279 4679 m_cpt_dcache_dir_write++; 4280 4680 #endif 4281 r_dcache.write_dir( r_dcache_save_paddr.read(), 4282 r_dcache_miss_way.read(), 4283 r_dcache_miss_set.read(), 4284 CACHE_SLOT_STATE_VALID ); 4681 4682 size_t way = r_dcache_miss_way.read(); 4683 size_t set = r_dcache_miss_set.read(); 4684 if (r_dcache_read_state.read()) 4685 { 4686 r_dcache.write_dir( r_dcache_save_paddr.read(), 4687 r_dcache_miss_way.read(), 4688 r_dcache_miss_set.read(), 4689 CACHE_SLOT_STATE_VALID_CC ); 4690 4691 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 4692 } 4693 else 4694 { 4695 r_dcache.write_dir( r_dcache_save_paddr.read(), 4696 r_dcache_miss_way.read(), 4697 r_dcache_miss_set.read(), 4698 CACHE_SLOT_STATE_VALID_NCC ); 4699 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 4700 for (size_t word =0; word < m_dcache_words ; word++) 4701 { 4702 r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 0; 4703 } 4704 } 4285 4705 4286 4706 #if DEBUG_DCACHE … … 4293 4713 #endif 4294 4714 // reset directory extension 4295 size_t way = r_dcache_miss_way.read(); 4296 size_t set = r_dcache_miss_set.read();4297 r_dcache_in_tlb[way*m_dcache_sets+set] = false;4298 r_dcache_contains_ptd[way*m_dcache_sets+set] = false;4715 4716 // MODIFIED 4717 //r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4718 //r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4299 4719 } 4300 4720 if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; … … 4467 4887 &state ); 4468 4888 4469 assert( (state == CACHE_SLOT_STATE_VALID ) and4889 assert( (state == CACHE_SLOT_STATE_VALID_CC or state == CACHE_SLOT_STATE_VALID_NCC) and 4470 4890 "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" ); 4471 4891 … … 4479 4899 4480 4900 // request a CAS CMD and go to DCACHE_DIRTY_WAIT state 4481 r_dcache_vci_cas_req = true; 4482 r_dcache_vci_paddr = r_dcache_dirty_paddr.read(); 4483 r_dcache_vci_cas_old = pte; 4484 r_dcache_vci_cas_new = pte | PTE_D_MASK; 4485 r_dcache_fsm = DCACHE_DIRTY_WAIT; 4901 if (state == CACHE_SLOT_STATE_VALID_CC) 4902 { 4903 r_dcache_vci_cas_req = true; 4904 r_dcache_vci_paddr = r_dcache_dirty_paddr.read(); 4905 r_dcache_vci_cas_old = pte; 4906 r_dcache_vci_cas_new = pte | PTE_D_MASK; 4907 r_cas_islocal = false; 4908 } 4909 else 4910 { 4911 r_cas_islocal = true; 4912 r_cas_local_way = way; 4913 r_cas_local_set = set; 4914 r_cas_local_word = word; 4915 r_dcache_vci_cas_new = pte | PTE_D_MASK; 4916 } 4917 4918 4919 r_dcache_fsm = DCACHE_DIRTY_WAIT; 4486 4920 4487 4921 #if DEBUG_DCACHE … … 4506 4940 // - if the CAS is a failure, we just retry the write. 4507 4941 { 4942 uint32_t way = r_cas_local_way.read(); 4943 uint32_t set = r_cas_local_set.read(); 4944 uint32_t word = r_cas_local_word.read(); 4945 paddr_t nline = r_dcache_dirty_paddr.read() / (m_dcache_words<<2); 4946 4508 4947 // coherence clack request (from DSPIN CLACK) 4509 4948 if ( r_dcache_clack_req.read() ) … … 4522 4961 } 4523 4962 4524 if ( r_vci_rsp_data_error.read() ) // bus error 4525 { 4526 std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; 4527 std::cout << "This should not happen in this state" << std::endl; 4528 exit(0); 4529 } 4530 else if ( r_vci_rsp_fifo_dcache.rok() ) // response available 4531 { 4532 vci_rsp_fifo_dcache_get = true; 4533 r_dcache_fsm = DCACHE_IDLE; 4534 4963 if (!r_cas_islocal.read()) 4964 { 4965 if ( r_vci_rsp_data_error.read() ) // bus error 4966 { 4967 std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; 4968 std::cout << "This should not happen in this state" << std::endl; 4969 exit(0); 4970 } 4971 else if ( r_vci_rsp_fifo_dcache.rok() ) // response available 4972 { 4973 vci_rsp_fifo_dcache_get = true; 4974 r_dcache_fsm = DCACHE_IDLE; 4535 4975 #if DEBUG_DCACHE 4536 4976 if ( m_debug_activated ) … … 4540 4980 } 4541 4981 #endif 4982 } 4983 } 4984 else 4985 { 4986 r_dcache.write(way, 4987 set, 4988 word, 4989 r_dcache_vci_cas_new.read()); 4990 //std::cout << "CAS local" << std::endl; 4991 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 4992 { 4993 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 4994 r_dcache_tlb_inval_line = nline; 4995 r_dcache_tlb_inval_set = 0; 4996 r_dcache_fsm_scan_save = DCACHE_IDLE; 4997 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4998 break; 4999 } 5000 5001 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 5002 { 5003 r_itlb.reset(); 5004 r_dtlb.reset(); 5005 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; 5006 5007 #if DEBUG_DCACHE 5008 if ( m_debug_activated ) 5009 { 5010 std::cout << " <PROC " << name() 5011 << " DCACHE_DIRTY_WAIT> Flush DTLB & ITLB" << std::endl; 5012 } 5013 #endif 5014 } 5015 r_dcache_fsm = DCACHE_IDLE; 4542 5016 } 4543 5017 break; … … 4674 5148 &word ); // unused 4675 5149 5150 r_dcache_cc_state = state; 4676 5151 r_dcache_cc_way = way; 4677 5152 r_dcache_cc_set = set; 4678 4679 if ( state == CACHE_SLOT_STATE_VALID) // hit 4680 { 4681 // need to update the cache state 4682 if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update 4683 { 4684 r_dcache_cc_need_write = true; 4685 r_dcache_fsm = DCACHE_CC_UPDT; 4686 r_dcache_cc_word = r_cc_receive_word_idx.read(); 4687 } 4688 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval 4689 { 4690 r_dcache_fsm = DCACHE_CC_INVAL; 5153 /*RWT / ODCCP*/ 5154 if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) // hit 5155 { 5156 // need to update the cache state 5157 r_dcache_cc_need_write = true; 5158 r_dcache_cc_cleanup_line_ncc = false; 5159 if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update 5160 { 5161 r_dcache_fsm = DCACHE_CC_UPDT; 5162 r_dcache_cc_word = r_cc_receive_word_idx.read(); 5163 } 5164 else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval 5165 { 5166 if (state == CACHE_SLOT_STATE_VALID_NCC) 5167 { 5168 r_dcache_cc_inval_addr = (paddr &~0x3F); 5169 r_dcache_cc_inval_data_cpt = 0; 5170 } 5171 r_dcache_fsm = DCACHE_CC_INVAL; 5172 r_dcache_dirty_save = false; 4691 5173 } 4692 5174 } … … 4716 5198 << " PADDR = " << std::hex << paddr 4717 5199 << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read() 4718 << " / HIT = " << ( state == CACHE_SLOT_STATE_VALID) << std::endl;5200 << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl; 4719 5201 } 4720 5202 #endif … … 4722 5204 break; 4723 5205 } 5206 4724 5207 ///////////////////// 4725 5208 case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a … … 4729 5212 size_t way = r_dcache_cc_way.read(); 4730 5213 size_t set = r_dcache_cc_set.read(); 4731 4732 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval 4733 { 4734 r_dcache_in_tlb[way*m_dcache_sets+set] = false; 4735 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 4736 r_dcache_tlb_inval_set = 0; 4737 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 4738 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 4739 break; 4740 } 4741 4742 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush 4743 { 4744 r_itlb.reset(); 4745 r_dtlb.reset(); 4746 r_dcache_contains_ptd[way*m_dcache_sets+set] = false; 4747 5214 int cache_state = r_dcache_cc_state.read(); 5215 bool dirty_save = false; 5216 5217 if (r_dcache_cc_need_write.read()) 5218 { 5219 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 5220 { 5221 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;//need to remember it was dirty for cleanup 5222 dirty_save = true; 5223 r_dcache_dirty_save = true; 5224 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 5225 r_dcache_tlb_inval_set = 0; 5226 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 5227 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 5228 break; 5229 } 5230 else 5231 { 5232 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 5233 { 5234 r_itlb.reset(); 5235 r_dtlb.reset(); 5236 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5237 dirty_save = true; 5238 r_dcache_dirty_save = true; 4748 5239 #if DEBUG_DCACHE 4749 5240 if ( m_debug_activated ) … … 4753 5244 } 4754 5245 #endif 4755 } 4756 4757 assert (not r_dcache_cc_send_req.read() && 4758 "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " 4759 "must not be set"); 4760 4761 // Switch slot state to ZOMBI and send CLEANUP command 4762 r_dcache.write_dir( 0, 4763 way, 4764 set, 4765 CACHE_SLOT_STATE_ZOMBI ); 4766 4767 // coherence request completed 4768 r_cc_receive_dcache_req = false; 4769 r_dcache_cc_send_req = true; 4770 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4771 r_dcache_cc_send_way = r_dcache_cc_way.read(); 4772 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4773 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 4774 4775 #if DEBUG_DCACHE 4776 if ( m_debug_activated ) 4777 { 4778 std::cout << " <PROC " << name() 4779 << " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec 4780 << " / WAY = " << way 4781 << " / SET = " << set << std::endl; 4782 } 4783 #endif 5246 } 5247 5248 if (cache_state == CACHE_SLOT_STATE_VALID_CC) 5249 { 5250 r_dcache.write_dir( way, 5251 set, 5252 CACHE_SLOT_STATE_ZOMBI ); 5253 } 5254 5255 r_dcache_cc_need_write = false; 5256 } 5257 } 5258 assert (not r_dcache_cc_send_req.read() && 5259 "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " 5260 "must not be set"); 5261 // coherence request completed 5262 r_cc_receive_dcache_req = false; 5263 // request multicast acknowledgement 5264 r_dcache_cc_send_req = true; 5265 r_dcache_cc_send_way = way; 5266 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 5267 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 5268 // MODIFIER POUR DIRTY BIT // 5269 if (cache_state == CACHE_SLOT_STATE_VALID_NCC) 5270 { 5271 r_dcache_cc_cleanup_line_ncc = true; 5272 //if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data 5273 if (true) //must send data 5274 { 5275 r_dcache_cc_cleanup_updt_data = true; 5276 for (size_t w = 0; w< m_dcache_words; w++) 5277 { 5278 m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; 5279 } 5280 r_dcache_fsm = DCACHE_CC_INVAL_DATA; 5281 } 5282 else 5283 { 5284 r_dcache_cc_cleanup_updt_data = false; 5285 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5286 } 5287 } 5288 else 5289 { 5290 r_dcache_cc_cleanup_updt_data = false; 5291 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5292 } 5293 5294 break; 5295 } 5296 5297 ///////////////////// 5298 case DCACHE_CC_INVAL_DATA: 5299 { 5300 5301 uint32_t rdata; 5302 size_t way; 5303 size_t set; 5304 size_t word; 5305 r_dcache.read_neutral(r_dcache_cc_inval_addr.read(), 5306 &rdata, 5307 &way, 5308 &set, 5309 &word); 5310 if(r_cc_send_data_fifo.wok()) 5311 { 5312 r_dcache_cc_inval_addr = r_dcache_cc_inval_addr.read() + 4; 5313 5314 cleanup_data_updt_fifo_dcache_put = true; 5315 cleanup_data_updt_fifo_dcache_data = rdata; 5316 5317 r_dcache_cc_inval_data_cpt = r_dcache_cc_inval_data_cpt.read() + 1; 5318 if(r_dcache_cc_inval_data_cpt.read() == (m_dcache_words - 1)) 5319 { 5320 r_dcache_cc_inval_data_cpt = 0; 5321 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5322 r_dcache.write_dir( way, 5323 set, 5324 CACHE_SLOT_STATE_ZOMBI ); 5325 } 5326 } 4784 5327 break; 4785 5328 } … … 4792 5335 size_t set = r_dcache_cc_set.read(); 4793 5336 4794 if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval4795 {4796 r_dcache_in_tlb[way*m_dcache_sets+set] = false;4797 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();4798 r_dcache_tlb_inval_set = 0;4799 r_dcache_fsm_scan_save = r_dcache_fsm.read();4800 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;4801 4802 break;4803 }4804 4805 if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush4806 {4807 r_itlb.reset();4808 r_dtlb.reset();4809 r_dcache_contains_ptd[way*m_dcache_sets+set] = false;5337 if (r_dcache_cc_need_write.read()) 5338 { 5339 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) 5340 { 5341 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 5342 r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); 5343 r_dcache_tlb_inval_set = 0; 5344 r_dcache_fsm_scan_save = r_dcache_fsm.read(); 5345 r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; 5346 break; 5347 } 5348 if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) 5349 { 5350 r_itlb.reset(); 5351 r_dtlb.reset(); 5352 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; 4810 5353 4811 5354 #if DEBUG_DCACHE … … 4816 5359 } 4817 5360 #endif 4818 }4819 4820 assert (not r_dcache_cc_send_req.read() &&4821 "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "4822 "must not be set");5361 } 5362 5363 assert (not r_dcache_cc_send_req.read() && 5364 "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " 5365 "must not be set"); 4823 5366 4824 if ( not r_cc_receive_updt_fifo_be.rok() ) break; 4825 4826 if (r_dcache_cc_need_write.read()) 4827 { 4828 5367 if ( not r_cc_receive_updt_fifo_be.rok() ) break; 5368 4829 5369 #ifdef INSTRUMENTATION 4830 5370 m_cpt_dcache_data_write++; … … 4855 5395 // no need to write in the cache anymore 4856 5396 r_dcache_cc_need_write = false; 4857 4858 5397 // coherence request completed 4859 5398 r_cc_receive_dcache_req = false; … … 5041 5580 r_dcache_vci_unc_req.read()) 5042 5581 or r_vci_cmd_imiss_prio.read() ); 5043 5044 5582 // 1 - Data Read Miss 5045 5583 if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) ) … … 5048 5586 r_dcache_vci_miss_req = false; 5049 5587 r_vci_cmd_imiss_prio = true; 5050 //m_cpt_dmiss_transaction++;5588 m_cpt_dmiss_transaction++; 5051 5589 } 5052 5590 // 2 - Data Read Uncachable … … 5055 5593 r_vci_cmd_fsm = CMD_DATA_UNC; 5056 5594 r_dcache_vci_unc_req = false; 5057 //m_cpt_dunc_transaction++;5595 m_cpt_dunc_transaction++; 5058 5596 } 5059 5597 // 3 - Data Linked Load … … 5062 5600 r_dcache_vci_ll_req = false; 5063 5601 r_vci_cmd_fsm = CMD_DATA_LL; 5064 //m_cpt_ll_transaction++;5602 m_cpt_ll_transaction++; 5065 5603 } 5066 5604 // 4 - Instruction Miss … … 5070 5608 r_icache_miss_req = false; 5071 5609 r_vci_cmd_imiss_prio = false; 5072 //m_cpt_imiss_transaction++;5610 m_cpt_imiss_transaction++; 5073 5611 } 5074 5612 // 5 - Instruction Uncachable … … 5077 5615 r_vci_cmd_fsm = CMD_INS_UNC; 5078 5616 r_icache_unc_req = false; 5079 //m_cpt_iunc_transaction++;5617 //m_cpt_iunc_transaction++; 5080 5618 } 5081 5619 // 6 - Data Write … … 5086 5624 r_vci_cmd_min = wbuf_min; 5087 5625 r_vci_cmd_max = wbuf_max; 5088 //m_cpt_write_transaction++;5089 //m_length_write_transaction += (wbuf_max-wbuf_min+1);5626 m_cpt_write_transaction++; 5627 m_length_write_transaction += (wbuf_max-wbuf_min+1); 5090 5628 } 5091 5629 // 7 - Data Store Conditionnal … … 5095 5633 r_vci_cmd_cpt = 0; 5096 5634 r_vci_cmd_fsm = CMD_DATA_SC; 5097 //m_cpt_sc_transaction++;5635 //m_cpt_sc_transaction++; 5098 5636 } 5099 5637 // 8 - Compare And Swap … … 5103 5641 r_dcache_vci_cas_req = false; 5104 5642 r_vci_cmd_cpt = 0; 5105 //m_cpt_cas_transaction++;5643 //m_cpt_cas_transaction++; 5106 5644 } 5107 5645 … … 5194 5732 { 5195 5733 r_vci_rsp_cpt = 0; 5196 5734 if (r_dcache_vci_paddr.read() == 0x1f624) std::cout << "Tansaction on barrier, pktid = " << p_vci.rpktid.read() << std::endl; 5197 5735 if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_UNC ) 5198 5736 { … … 5311 5849 else // no error reported 5312 5850 { 5313 if ( r_vci_rsp_fifo_dcache.wok() ) 5851 5852 5853 if ( r_vci_rsp_fifo_dcache.wok() && r_vci_rsp_fifo_rpktid.wok()) 5314 5854 { 5315 5855 assert( (r_vci_rsp_cpt.read() < m_dcache_words) and … … 5319 5859 vci_rsp_fifo_dcache_put = true, 5320 5860 vci_rsp_fifo_dcache_data = p_vci.rdata.read(); 5861 vci_rsp_fifo_rpktid = (p_vci.rpktid.read() == 0x9);//RWT: interpretation of pktid for state (NCC or CC) 5862 vci_rsp_fifo_rpktid_put = true;//RWT 5863 5321 5864 if ( p_vci.reop.read() ) 5322 5865 { 5866 if (r_vci_rsp_cpt.read() != m_dcache_words - 1) std::cout << "assert on proc " << name() << std::endl; 5323 5867 assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and 5324 5868 "The VCI response packet for data miss is too short"); … … 5480 6024 if (p_dspin_p2m.read.read()) 5481 6025 { 5482 if (r_cc_send_last_client.read() == 0) // dcache active request 5483 r_dcache_cc_send_req = false; // reset dcache request 5484 else // icache active request 5485 r_icache_cc_send_req = false; // reset icache request 5486 5487 // go back to idle state 5488 r_cc_send_fsm = CC_SEND_IDLE; 6026 //std::cout << "CLEANUP send on line " << r_dcache_cc_send_nline.read() << std::endl; 6027 if(r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0))//dcache request with data 6028 { 6029 r_cc_send_fsm = CC_SEND_CLEANUP_DATA_UPDT; 6030 } 6031 else 6032 { 6033 if (r_cc_send_last_client.read() == 0) // dcache active request 6034 { 6035 r_dcache_cc_send_req = false; // reset dcache request 6036 } 6037 else // icache active request 6038 { 6039 r_icache_cc_send_req = false; // reset icache request 6040 } 6041 // go back to idle state 6042 r_cc_send_fsm = CC_SEND_IDLE; 6043 } 6044 } 6045 break; 6046 } 6047 /////////////////////////// 6048 case CC_SEND_CLEANUP_DATA_UPDT: 6049 { 6050 if (p_dspin_p2m.read.read()) 6051 { 6052 if(r_cc_send_data_fifo.rok()) 6053 { 6054 /*ODCCP*///std::cout<<"CLEANUP_DATA_UPDT" << std::endl; 6055 m_cpt_data_cleanup++; 6056 cleanup_data_updt_fifo_dcache_get = true; 6057 r_cc_send_cpt_word = r_cc_send_cpt_word.read() + 1; 6058 if (r_cc_send_cpt_word.read() == m_dcache_words-1) 6059 { 6060 //std::cout << "L1 paddr CLEANUP DATA | paddr = " << std::hex << (r_dcache_cc_send_nline.read()*m_dcache_words)*4 << std::dec << std::endl; 6061 /*ODCCP*/ 6062 //std::cout << "CLEANUP with DATA finished by " << name() << std::endl; 6063 r_dcache_cc_send_req = false; 6064 r_dcache_cc_cleanup_updt_data = false; 6065 r_cc_send_cpt_word = 0; 6066 r_cc_send_fsm = CC_SEND_IDLE; 6067 } 6068 } 5489 6069 } 5490 6070 break; … … 5801 6381 vci_rsp_fifo_dcache_put, 5802 6382 vci_rsp_fifo_dcache_data); 6383 //BUG pktid 6384 r_vci_rsp_fifo_rpktid.update(vci_rsp_fifo_rpktid_get, 6385 vci_rsp_fifo_rpktid_put, 6386 vci_rsp_fifo_rpktid); 6387 6388 r_cc_send_data_fifo.update(cleanup_data_updt_fifo_dcache_get, 6389 cleanup_data_updt_fifo_dcache_put, 6390 cleanup_data_updt_fifo_dcache_data); 5803 6391 5804 6392 ///////////////// updt FIFO update ////////////////////// … … 6011 6599 >> (m_nline_width - m_x_width - m_y_width) 6012 6600 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 6013 6014 6601 DspinDhccpParam::dspin_set(dspin_send_data, 6015 6602 dest, … … 6027 6614 DspinDhccpParam::TYPE_CLEANUP_DATA, 6028 6615 DspinDhccpParam::P2M_TYPE); 6616 6617 DspinDhccpParam::dspin_set(dspin_send_data, 6618 (r_dcache_cc_cleanup_line_ncc.read() and (r_cc_send_last_client.read() == 0)), 6619 DspinDhccpParam::CLEANUP_NCC); 6029 6620 } 6030 6621 else // icache active request … … 6049 6640 DspinDhccpParam::TYPE_CLEANUP_INST, 6050 6641 DspinDhccpParam::P2M_TYPE); 6642 6643 DspinDhccpParam::dspin_set(dspin_send_data, 6644 0, 6645 DspinDhccpParam::CLEANUP_NCC); 6646 6647 6051 6648 } 6052 6649 // send flit … … 6060 6657 { 6061 6658 // initialize dspin send data 6062 // DspinDhccpParam::dspin_set(dspin_send_data,6063 // 1,6064 // DspinDhccpParam::P2M_EOP);6065 6066 6659 if(r_cc_send_last_client.read() == 0) // dcache active request 6067 6660 { … … 6079 6672 p_dspin_p2m.data = dspin_send_data; 6080 6673 p_dspin_p2m.write = true; 6081 p_dspin_p2m.eop = true; 6674 p_dspin_p2m.eop = ! (r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0)); 6675 break; 6676 } 6677 /////////////////////// 6678 case CC_SEND_CLEANUP_DATA_UPDT: 6679 { 6680 /*if (r_cc_send_cpt_word.read() == m_dcache_words-1) 6681 { 6682 DspinDhccpParam::dspin_set(dspin_send_data, 6683 1, 6684 DspinDhccpParam::FROM_L1_EOP); 6685 } 6686 else 6687 { 6688 DspinDhccpParam::dspin_set(dspin_send_data, 6689 0, 6690 DspinDhccpParam::FROM_L1_EOP); 6691 }*/ 6692 6693 DspinDhccpParam::dspin_set(dspin_send_data, 6694 r_cc_send_data_fifo.read(), 6695 DspinDhccpParam::CLEANUP_DATA_UPDT); 6696 6697 p_dspin_p2m.data = dspin_send_data; 6698 //std::cout << "genmoore CLEANUP DATA UPDT : dspin_send_data = " << std::hex << dspin_send_data << std::dec << std::endl; 6699 p_dspin_p2m.write = true; 6700 p_dspin_p2m.eop = (r_cc_send_cpt_word.read() == m_dcache_words-1); 6082 6701 break; 6083 6702 }
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