- Timestamp:
- Aug 2, 2013, 2:38:51 PM (11 years ago)
- Location:
- trunk/modules/vci_mem_cache/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r468 r481 104 104 TGT_RSP_XRAM, 105 105 TGT_RSP_MULTI_ACK, 106 TGT_RSP_CLEANUP 106 TGT_RSP_CLEANUP, 107 TGT_RSP_UPT_LOCK, 108 TGT_RSP_IVT_LOCK 107 109 }; 108 110 … … 333 335 ALLOC_UPT_WRITE, 334 336 ALLOC_UPT_CAS, 335 ALLOC_UPT_MULTI_ACK 337 ALLOC_UPT_MULTI_ACK, 338 ALLOC_UPT_TGT_RSP 336 339 }; 337 340 … … 343 346 ALLOC_IVT_CLEANUP, 344 347 ALLOC_IVT_CAS, 345 ALLOC_IVT_CONFIG 348 ALLOC_IVT_CONFIG, 349 ALLOC_IVT_TGT_RSP 346 350 }; 347 351 … … 492 496 void genMoore(); 493 497 void check_monitor(addr_t addr, data_t data, bool read); 498 bool hit_cleanup_req(size_t *index); 499 bool hit_multi_ack_req(size_t *index); 494 500 495 501 // Component attributes … … 510 516 TransactionTab m_trt; // xram transaction table 511 517 uint32_t m_upt_lines; 518 uint32_t m_ivt_lines; 512 519 UpdateTab m_upt; // pending update 513 520 UpdateTab m_ivt; // pending invalidate … … 736 743 737 744 // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) 738 sc_signal<bool> r_multi_ack_to_tgt_rsp_req;// valid request745 sc_signal<bool> *r_multi_ack_to_tgt_rsp_req; // valid request 739 746 sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid 740 747 sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid … … 784 791 785 792 // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) 786 sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request793 sc_signal<bool> *r_cleanup_to_tgt_rsp_req; // valid request 787 794 sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid 788 795 sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid … … 919 926 sc_signal<int> r_tgt_rsp_fsm; 920 927 sc_signal<size_t> r_tgt_rsp_cpt; 928 sc_signal<size_t> r_tgt_rsp_prio_multi_ack; 929 sc_signal<size_t> r_tgt_rsp_prio_cleanup; 921 930 sc_signal<bool> r_tgt_rsp_key_sent; 922 931 -
trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r468 r481 84 84 "TGT_RSP_XRAM", 85 85 "TGT_RSP_MULTI_ACK", 86 "TGT_RSP_CLEANUP" 86 "TGT_RSP_CLEANUP", 87 "TGT_RSP_UPT_LOCK", 88 "TGT_RSP_IVT_LOCK" 87 89 }; 88 90 const char *cc_receive_fsm_str[] = … … 285 287 "ALLOC_UPT_WRITE", 286 288 "ALLOC_UPT_CAS", 287 "ALLOC_UPT_MULTI_ACK" 289 "ALLOC_UPT_MULTI_ACK", 290 "ALLOC_UPT_TGT_RSP" 288 291 }; 289 292 const char *alloc_ivt_fsm_str[] = … … 293 296 "ALLOC_IVT_CLEANUP", 294 297 "ALLOC_IVT_CAS", 295 "ALLOC_IVT_CONFIG" 298 "ALLOC_IVT_CONFIG", 299 "ALLOC_IVT_TGT_RSP" 296 300 }; 297 301 const char *alloc_heap_fsm_str[] = … … 361 365 m_trt(this->name(), trt_lines, nwords), 362 366 m_upt_lines(upt_lines), 367 m_ivt_lines(ivt_lines), 363 368 m_upt(upt_lines), 364 369 m_ivt(ivt_lines), … … 502 507 i++; 503 508 } 509 // Allocation for MULTI_ACK FSM 510 r_multi_ack_to_tgt_rsp_req = new sc_signal<bool>[m_upt_lines]; 511 r_cleanup_to_tgt_rsp_req = new sc_signal<bool>[m_ivt_lines]; 504 512 505 513 // Allocation for IXR_RSP FSM … … 571 579 << " at cycle " << std::dec << m_cpt_cycles << std::endl; 572 580 } 581 } 582 // Index is the value of the current priority 583 /////////////////////////////////////////////////////////////////////// 584 tmpl(bool) ::hit_cleanup_req(size_t *index) 585 /////////////////////////////////////////////////////////////////////// 586 { 587 size_t i = *index; 588 do 589 { 590 if(r_cleanup_to_tgt_rsp_req[i].read()) 591 { 592 *index = i; 593 return true; 594 } 595 i = (i + 1) % m_ivt_lines; 596 } while (i != *index); 597 return false; 598 } 599 600 // Index is the value of the current priority 601 /////////////////////////////////////////////////////////////////////// 602 tmpl(bool) ::hit_multi_ack_req(size_t *index) 603 /////////////////////////////////////////////////////////////////////// 604 { 605 size_t i = *index; 606 do 607 { 608 if(r_multi_ack_to_tgt_rsp_req[i].read()) 609 { 610 *index = i; 611 return true; 612 } 613 i = (i + 1) % m_upt_lines; 614 } while (i != *index); 615 return false; 573 616 } 574 617 … … 674 717 { 675 718 delete [] r_ixr_rsp_to_xram_rsp_rok; 676 719 delete [] r_multi_ack_to_tgt_rsp_req; 720 delete [] r_cleanup_to_tgt_rsp_req; 677 721 delete [] r_xram_rsp_victim_data; 678 722 delete [] r_xram_rsp_to_tgt_rsp_data; … … 776 820 #endif 777 821 778 r_cleanup_to_tgt_rsp_req = false;779 780 822 m_cc_receive_to_cleanup_fifo.init(); 781 782 r_multi_ack_to_tgt_rsp_req = false; 823 for(size_t i = 0; i < m_upt_lines; i++) 824 { 825 r_multi_ack_to_tgt_rsp_req[i] = false; 826 } 827 for(size_t i = 0; i < m_ivt_lines; i++) 828 { 829 r_cleanup_to_tgt_rsp_req[i] = false; 830 } 783 831 784 832 m_cc_receive_to_multi_ack_fifo.init(); … … 818 866 r_alloc_heap_reset_cpt = 0; 819 867 820 r_tgt_rsp_key_sent = false; 868 r_tgt_rsp_key_sent = false; 869 r_tgt_rsp_prio_multi_ack = 0; 870 r_tgt_rsp_prio_cleanup = 0; 821 871 822 872 // Activity counters … … 1337 1387 size_t count = 0; 1338 1388 bool valid = m_upt.decrement(r_multi_ack_upt_index.read(), count); 1389 1390 bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read()); 1339 1391 1340 1392 if(not valid) … … 1346 1398 } 1347 1399 1348 if(count == 0) 1400 if(count == 0 and need_rsp) 1401 { 1402 r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; 1403 } 1404 else if(count == 0) 1349 1405 { 1350 1406 r_multi_ack_fsm = MULTI_ACK_UPT_CLEAR; … … 1380 1436 r_multi_ack_pktid = m_upt.pktid(r_multi_ack_upt_index.read()); 1381 1437 r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read()); 1382 bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read());1383 1438 bool need_ack = m_upt.need_ack(r_multi_ack_upt_index.read()); 1384 1439 … … 1386 1441 m_upt.clear(r_multi_ack_upt_index.read()); 1387 1442 1388 if ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; 1389 else if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK; 1443 if ( need_ack ) r_multi_ack_fsm = MULTI_ACK_CONFIG_ACK; 1390 1444 else r_multi_ack_fsm = MULTI_ACK_IDLE; 1391 1445 … … 1400 1454 ///////////////////////// 1401 1455 case MULTI_ACK_WRITE_RSP: // Post a response request to TGT_RSP FSM 1402 // Wait if pending request 1403 { 1404 if ( r_multi_ack_to_tgt_rsp_req.read() ) break; 1405 1406 r_multi_ack_to_tgt_rsp_req = true; 1407 r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read(); 1408 r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read(); 1409 r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read(); 1410 r_multi_ack_fsm = MULTI_ACK_IDLE; 1456 { 1457 r_multi_ack_to_tgt_rsp_req[r_multi_ack_upt_index.read()] = true; 1458 r_multi_ack_fsm = MULTI_ACK_IDLE; 1411 1459 1412 1460 #if DEBUG_MEMC_MULTI_ACK 1413 1461 if(m_debug) 1414 1462 std::cout << " <MEMC " << name() << " MULTI_ACK_WRITE_RSP>" 1415 << " Request TGT_RSP FSM to send a response to srcid "1416 << std::hex << r_multi_ack_srcid.read() << std::endl;1463 << " Request TGT_RSP FSM to send a response" 1464 << " / Request for upt index " << r_multi_ack_upt_index.read() << std::endl; 1417 1465 #endif 1418 1466 break; … … 4913 4961 size_t count = 0; 4914 4962 m_ivt.decrement(r_cleanup_index.read(), count); 4915 4916 if(count == 0) // multi inval transaction completed 4963 4964 if((count == 0) and r_cleanup_need_rsp.read()) // multi inval transaction completed 4965 { 4966 r_cleanup_fsm = CLEANUP_WRITE_RSP; 4967 } 4968 else if(count == 0) // multi inval transaction completed 4917 4969 { 4918 4970 r_cleanup_fsm = CLEANUP_IVT_CLEAR; … … 4948 5000 m_ivt.clear(r_cleanup_index.read()); 4949 5001 4950 if ( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP; 4951 else if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK; 5002 if ( r_cleanup_need_ack.read() ) r_cleanup_fsm = CLEANUP_CONFIG_ACK; 4952 5003 else r_cleanup_fsm = CLEANUP_SEND_CLACK; 4953 5004 … … 4964 5015 // wait if pending request to the TGT_RSP FSM 4965 5016 { 4966 if(r_cleanup_to_tgt_rsp_req.read()) break;4967 5017 4968 5018 // no pending request 4969 r_cleanup_to_tgt_rsp_req = true; 4970 r_cleanup_to_tgt_rsp_srcid = r_cleanup_write_srcid.read(); 4971 r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); 4972 r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); 5019 r_cleanup_to_tgt_rsp_req[r_cleanup_index.read()] = true; 4973 5020 4974 5021 r_cleanup_fsm = CLEANUP_SEND_CLACK; … … 4977 5024 if(m_debug) 4978 5025 std::cout << " <MEMC " << name() << " CLEANUP_WRITE_RSP>" 4979 << " Send a response to a previous write request: " 4980 << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() 4981 << " / rtrdid = " << r_cleanup_write_trdid.read() 4982 << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl; 5026 << " Send a response to a previous write request" 5027 << std::endl; 4983 5028 #endif 4984 5029 break; … … 6485 6530 case TGT_RSP_CONFIG_IDLE: // tgt_cmd requests have the highest priority 6486 6531 { 6532 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read(); 6533 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read(); 6487 6534 if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 6488 6535 else if(r_read_to_tgt_rsp_req) … … 6498 6545 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6499 6546 } 6500 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6501 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6547 else if(hit_multi_ack_req(&prio_multi_ack)) 6548 { 6549 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6550 // update rr priority 6551 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6552 } 6553 else if(hit_cleanup_req(&prio_cleanup)) 6554 { 6555 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6556 r_tgt_rsp_prio_cleanup = prio_cleanup; 6557 } 6502 6558 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6503 6559 break; … … 6506 6562 case TGT_RSP_TGT_CMD_IDLE: // read requests have the highest priority 6507 6563 { 6564 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read(); 6565 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read(); 6508 6566 if(r_read_to_tgt_rsp_req) 6509 6567 { … … 6518 6576 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6519 6577 } 6520 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6521 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6578 else if(hit_multi_ack_req(&prio_multi_ack)) 6579 { 6580 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6581 // update rr priority 6582 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6583 } 6584 else if(hit_cleanup_req(&prio_cleanup)) 6585 { 6586 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6587 r_tgt_rsp_prio_cleanup = prio_cleanup; 6588 } 6522 6589 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6523 6590 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6527 6594 case TGT_RSP_READ_IDLE: // write requests have the highest priority 6528 6595 { 6596 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read(); 6597 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read(); 6529 6598 if(r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; 6530 6599 else if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; … … 6534 6603 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6535 6604 } 6536 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6537 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6605 else if(hit_multi_ack_req(&prio_multi_ack)) 6606 { 6607 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6608 // update rr priority 6609 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6610 } 6611 else if(hit_cleanup_req(&prio_cleanup)) 6612 { 6613 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6614 r_tgt_rsp_prio_cleanup = prio_cleanup; 6615 } 6538 6616 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6539 6617 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6548 6626 case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority 6549 6627 { 6628 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read(); 6629 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read(); 6550 6630 if(r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; 6551 6631 else if(r_xram_rsp_to_tgt_rsp_req) … … 6554 6634 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6555 6635 } 6556 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6557 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6636 else if(hit_multi_ack_req(&prio_multi_ack)) 6637 { 6638 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6639 // update rr priority 6640 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6641 } 6642 else if(hit_cleanup_req(&prio_cleanup)) 6643 { 6644 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6645 r_tgt_rsp_prio_cleanup = prio_cleanup; 6646 } 6558 6647 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6559 6648 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6569 6658 case TGT_RSP_CAS_IDLE: // xram_rsp requests have the highest priority 6570 6659 { 6660 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read(); 6661 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read(); 6571 6662 if(r_xram_rsp_to_tgt_rsp_req) 6572 6663 { … … 6574 6665 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6575 6666 } 6576 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; 6577 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6667 else if(hit_multi_ack_req(&prio_multi_ack)) 6668 { 6669 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6670 // update rr priority 6671 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6672 } 6673 else if(hit_cleanup_req(&prio_cleanup)) 6674 { 6675 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6676 r_tgt_rsp_prio_cleanup = prio_cleanup; 6677 } 6578 6678 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6579 6679 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6590 6690 case TGT_RSP_XRAM_IDLE: // multi ack requests have the highest priority 6591 6691 { 6592 6593 if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; 6594 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6692 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read(); 6693 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read(); 6694 6695 if(hit_multi_ack_req(&prio_multi_ack)) 6696 { 6697 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6698 // update rr priority 6699 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6700 } 6701 else if(hit_cleanup_req(&prio_cleanup)) 6702 { 6703 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6704 r_tgt_rsp_prio_cleanup = prio_cleanup; 6705 } 6595 6706 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6596 6707 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6612 6723 case TGT_RSP_MULTI_ACK_IDLE: // cleanup requests have the highest priority 6613 6724 { 6614 if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6725 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read(); 6726 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read(); 6727 if(hit_cleanup_req(&prio_cleanup)) 6728 { 6729 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6730 r_tgt_rsp_prio_cleanup = prio_cleanup; 6731 } 6615 6732 else if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6616 6733 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6627 6744 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6628 6745 } 6629 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 6746 else if(hit_multi_ack_req(&prio_multi_ack)) 6747 { 6748 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6749 // update rr priority 6750 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6751 } 6630 6752 break; 6631 6753 } … … 6633 6755 case TGT_RSP_CLEANUP_IDLE: // tgt cmd requests have the highest priority 6634 6756 { 6757 size_t prio_multi_ack = r_tgt_rsp_prio_multi_ack.read(); 6758 size_t prio_cleanup = r_tgt_rsp_prio_cleanup.read(); 6635 6759 if(r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 6636 6760 else if(r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; … … 6647 6771 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 6648 6772 } 6649 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; 6650 else if(r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6773 else if(hit_multi_ack_req(&prio_multi_ack)) 6774 { 6775 r_tgt_rsp_fsm = TGT_RSP_UPT_LOCK; 6776 // update rr priority 6777 r_tgt_rsp_prio_multi_ack = prio_multi_ack; 6778 } 6779 else if(hit_cleanup_req(&prio_cleanup)) 6780 { 6781 r_tgt_rsp_fsm = TGT_RSP_IVT_LOCK; 6782 r_tgt_rsp_prio_cleanup = prio_cleanup; 6783 } 6651 6784 break; 6652 6785 } … … 6761 6894 break; 6762 6895 } 6896 6897 /////////////////////// 6898 case TGT_RSP_IVT_LOCK: // Clear IVT entry 6899 { 6900 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_TGT_RSP) break; 6901 6902 r_cleanup_to_tgt_rsp_srcid = m_ivt.srcid(r_tgt_rsp_prio_cleanup.read()); 6903 r_cleanup_to_tgt_rsp_trdid = m_ivt.trdid(r_tgt_rsp_prio_cleanup.read()); 6904 r_cleanup_to_tgt_rsp_pktid = m_ivt.pktid(r_tgt_rsp_prio_cleanup.read()); 6905 6906 m_ivt.clear(r_tgt_rsp_prio_cleanup.read()); 6907 6908 r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 6909 break; 6910 } 6911 6763 6912 ///////////////////// 6764 6913 case TGT_RSP_CLEANUP: // pas clair pour moi (AG) … … 6775 6924 #endif 6776 6925 r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE; 6777 r_cleanup_to_tgt_rsp_req = false; 6926 r_cleanup_to_tgt_rsp_req[r_tgt_rsp_prio_cleanup.read()] = false; 6927 r_tgt_rsp_prio_cleanup = (r_tgt_rsp_prio_cleanup.read() + 1) % m_ivt_lines; 6778 6928 } 6779 6929 break; … … 6841 6991 } 6842 6992 /////////////////////// 6993 case TGT_RSP_UPT_LOCK: // Clear UPT entry 6994 { 6995 if (r_alloc_upt_fsm.read() != ALLOC_UPT_TGT_RSP) break; 6996 6997 r_multi_ack_to_tgt_rsp_srcid = m_upt.srcid(r_tgt_rsp_prio_multi_ack.read()); 6998 r_multi_ack_to_tgt_rsp_trdid = m_upt.trdid(r_tgt_rsp_prio_multi_ack.read()); 6999 r_multi_ack_to_tgt_rsp_pktid = m_upt.pktid(r_tgt_rsp_prio_multi_ack.read()); 7000 7001 m_upt.clear(r_tgt_rsp_prio_multi_ack.read()); 7002 7003 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 7004 break; 7005 } 7006 7007 /////////////////////// 6843 7008 case TGT_RSP_MULTI_ACK: // send the write response after coherence transaction 6844 7009 { … … 6854 7019 #endif 6855 7020 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK_IDLE; 6856 r_multi_ack_to_tgt_rsp_req = false; 7021 r_multi_ack_to_tgt_rsp_req[r_tgt_rsp_prio_multi_ack.read()] = false; 7022 r_tgt_rsp_prio_multi_ack = (r_tgt_rsp_prio_multi_ack.read() + 1) % m_upt_lines; 6857 7023 } 6858 7024 break; … … 6882 7048 else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 6883 7049 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7050 7051 else if (r_tgt_rsp_fsm.read() == TGT_RSP_UPT_LOCK) 7052 r_alloc_upt_fsm = ALLOC_UPT_TGT_RSP; 6884 7053 } 6885 7054 break; … … 6891 7060 if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 6892 7061 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7062 7063 else if (r_tgt_rsp_fsm.read() == TGT_RSP_UPT_LOCK) 7064 r_alloc_upt_fsm = ALLOC_UPT_TGT_RSP; 6893 7065 6894 7066 else if (r_write_fsm.read() == WRITE_UPT_LOCK) … … 6902 7074 (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) 6903 7075 { 7076 if (r_tgt_rsp_fsm.read() == TGT_RSP_UPT_LOCK) 7077 r_alloc_upt_fsm = ALLOC_UPT_TGT_RSP; 7078 7079 else if (r_write_fsm.read() == WRITE_UPT_LOCK) 7080 r_alloc_upt_fsm = ALLOC_UPT_WRITE; 7081 7082 else if (r_cas_fsm.read() == CAS_UPT_LOCK) 7083 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7084 } 7085 break; 7086 7087 ///////////////////////// 7088 case ALLOC_UPT_TGT_RSP: // allocated to TGT_RSP FSM 7089 if (r_tgt_rsp_fsm.read() != TGT_RSP_UPT_LOCK ) 7090 { 6904 7091 if (r_write_fsm.read() == WRITE_UPT_LOCK) 6905 7092 r_alloc_upt_fsm = ALLOC_UPT_WRITE; … … 6907 7094 else if (r_cas_fsm.read() == CAS_UPT_LOCK) 6908 7095 r_alloc_upt_fsm = ALLOC_UPT_CAS; 7096 7097 else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) 7098 r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; 7099 6909 7100 } 6910 7101 break; … … 6943 7134 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 6944 7135 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7136 7137 else if (r_tgt_rsp_fsm.read() == TGT_RSP_IVT_LOCK) 7138 r_alloc_ivt_fsm = ALLOC_IVT_TGT_RSP; 6945 7139 } 6946 7140 break; … … 6958 7152 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 6959 7153 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7154 7155 else if (r_tgt_rsp_fsm.read() == TGT_RSP_IVT_LOCK) 7156 r_alloc_ivt_fsm = ALLOC_IVT_TGT_RSP; 6960 7157 6961 7158 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) … … 6974 7171 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 6975 7172 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7173 7174 else if (r_tgt_rsp_fsm.read() == TGT_RSP_IVT_LOCK) 7175 r_alloc_ivt_fsm = ALLOC_IVT_TGT_RSP; 6976 7176 6977 7177 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) … … 6989 7189 if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 6990 7190 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7191 7192 else if (r_tgt_rsp_fsm.read() == TGT_RSP_IVT_LOCK) 7193 r_alloc_ivt_fsm = ALLOC_IVT_TGT_RSP; 6991 7194 6992 7195 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) … … 7004 7207 case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM 7005 7208 if (r_config_fsm.read() != CONFIG_DIR_IVT_LOCK) 7006 { 7209 { 7210 if (r_tgt_rsp_fsm.read() == TGT_RSP_IVT_LOCK) 7211 r_alloc_ivt_fsm = ALLOC_IVT_TGT_RSP; 7212 7213 else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7214 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 7215 7216 else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK) 7217 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 7218 7219 else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) 7220 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 7221 7222 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7223 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7224 } 7225 break; 7226 7227 ////////////////////////// 7228 case ALLOC_IVT_TGT_RSP: // allocated to TGT RSP FSM 7229 if (r_tgt_rsp_fsm.read() != TGT_RSP_IVT_LOCK) 7230 { 7007 7231 if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) 7008 7232 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; … … 7016 7240 else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) 7017 7241 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 7242 7243 else if (r_config_fsm.read() == CONFIG_DIR_IVT_LOCK) 7244 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 7018 7245 } 7019 7246 break;
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