source: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 468

Last change on this file since 468 was 468, checked in by cfuguet, 11 years ago


Merging vci_mem_cache from branches/v5 to trunk [441-467]

=-----------------------------------------------------------------------
r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

  • Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p
  • Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

=-----------------------------------------------------------------------
r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

  • Introducing third port for the CLACK network.
  • CLEANUP FSM is no more a CC_SEND FSM client.
  • CLEANUP FSM controls directly the p_dspin_clack port

=-----------------------------------------------------------------------
r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

  • Adding missing "strings" for print_trace() function
  • Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

=-----------------------------------------------------------------------
r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface


Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

=-----------------------------------------------------------------------
r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

  • Renaming FROM_MC DSPIN flits fields in M2P
  • Renaming FROM_L1 DSPIN flits fields in P2M
  • Renaming CLEANUP_ACK DSPIN flits fields in CLACK

=-----------------------------------------------------------------------
r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

  • Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.
  • Adding third port for the clack coherence network.
  • Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

=-----------------------------------------------------------------------
r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

=-----------------------------------------------------------------------
r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

  • In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

=-----------------------------------------------------------------------
r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

=-----------------------------------------------------------------------
r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.


Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

=-----------------------------------------------------------------------
r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

  • This platform contains a third local crossbar interconnect for the CLACK network.
  • It works only in a monocluster topology

=-----------------------------------------------------------------------
r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

  • Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

=-----------------------------------------------------------------------
r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

  • Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

=-----------------------------------------------------------------------
r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

  • Adding preprocessor conditional statements for ALMOS support


Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

=-----------------------------------------------------------------------
r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

  • Renaming FROM_MC fields in M2P
  • Renaming FROM_L1 fields in P2M
  • Renaming CLEANUP_ACK fields in CLACK
File size: 41.0 KB
Line 
1/* -*- c++ -*-
2 * File         : vci_mem_cache.h
3 * Date         : 26/10/2008
4 * Copyright    : UPMC / LIP6
5 * Authors      : Alain Greiner / Eric Guthmuller
6 *
7 * SOCLIB_LGPL_HEADER_BEGIN
8 *
9 * This file is part of SoCLib, GNU LGPLv2.1.
10 *
11 * SoCLib is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU Lesser General Public License as published
13 * by the Free Software Foundation; version 2.1 of the License.
14 *
15 * SoCLib is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with SoCLib; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 * SOCLIB_LGPL_HEADER_END
26 *
27 * Maintainers: alain eric.guthmuller@polytechnique.edu
28 *              cesar.fuguet-tortolero@lip6.fr
29 *              alexandre.joannou@lip6.fr
30 */
31
32#ifndef SOCLIB_CABA_MEM_CACHE_H
33#define SOCLIB_CABA_MEM_CACHE_H
34
35#include <inttypes.h>
36#include <systemc>
37#include <list>
38#include <cassert>
39#include "arithmetics.h"
40#include "alloc_elems.h"
41#include "caba_base_module.h"
42#include "vci_target.h"
43#include "vci_initiator.h"
44#include "generic_fifo.h"
45#include "mapping_table.h"
46#include "int_tab.h"
47#include "generic_llsc_global_table.h"
48#include "mem_cache_directory.h"
49#include "xram_transaction.h"
50#include "update_tab.h"
51#include "dspin_interface.h"
52#include "dspin_dhccp_param.h"
53
54#define TRT_ENTRIES      4      // Number of entries in TRT
55#define UPT_ENTRIES      4      // Number of entries in UPT
56#define IVT_ENTRIES      4      // Number of entries in IVT
57#define HEAP_ENTRIES     1024   // Number of entries in HEAP
58
59namespace soclib {  namespace caba {
60
61  using namespace sc_core;
62
63  template<typename vci_param_int, 
64           typename vci_param_ext,
65           size_t   dspin_in_width,
66           size_t   dspin_out_width>
67    class VciMemCache
68    : public soclib::caba::BaseModule
69    {
70      typedef typename vci_param_int::fast_addr_t  addr_t;
71      typedef typename sc_dt::sc_uint<64>          wide_data_t;
72      typedef uint32_t                             data_t;
73      typedef uint32_t                             tag_t;
74      typedef uint32_t                             be_t;
75      typedef uint32_t                             copy_t;
76
77      /* States of the TGT_CMD fsm */
78      enum tgt_cmd_fsm_state_e
79      {
80        TGT_CMD_IDLE,
81        TGT_CMD_ERROR,
82        TGT_CMD_READ,
83        TGT_CMD_WRITE,
84        TGT_CMD_CAS,
85        TGT_CMD_CONFIG
86      };
87
88      /* States of the TGT_RSP fsm */
89      enum tgt_rsp_fsm_state_e
90      {
91        TGT_RSP_CONFIG_IDLE,
92        TGT_RSP_TGT_CMD_IDLE,
93        TGT_RSP_READ_IDLE,
94        TGT_RSP_WRITE_IDLE,
95        TGT_RSP_CAS_IDLE,
96        TGT_RSP_XRAM_IDLE,
97        TGT_RSP_MULTI_ACK_IDLE,
98        TGT_RSP_CLEANUP_IDLE,
99        TGT_RSP_CONFIG,
100        TGT_RSP_TGT_CMD,
101        TGT_RSP_READ,
102        TGT_RSP_WRITE,
103        TGT_RSP_CAS,
104        TGT_RSP_XRAM,
105        TGT_RSP_MULTI_ACK,
106        TGT_RSP_CLEANUP
107      };
108
109      /* States of the DSPIN_TGT fsm */
110      enum cc_receive_fsm_state_e
111      {
112        CC_RECEIVE_IDLE,
113        CC_RECEIVE_CLEANUP,
114        CC_RECEIVE_CLEANUP_EOP,
115        CC_RECEIVE_MULTI_ACK
116      };
117
118      /* States of the CC_SEND fsm */
119      enum cc_send_fsm_state_e
120      {
121        CC_SEND_CONFIG_IDLE,
122        CC_SEND_XRAM_RSP_IDLE,
123        CC_SEND_WRITE_IDLE,
124        CC_SEND_CAS_IDLE,
125        CC_SEND_CONFIG_INVAL_HEADER,
126        CC_SEND_CONFIG_INVAL_NLINE,
127        CC_SEND_CONFIG_BRDCAST_HEADER,
128        CC_SEND_CONFIG_BRDCAST_NLINE,
129        CC_SEND_XRAM_RSP_BRDCAST_HEADER,
130        CC_SEND_XRAM_RSP_BRDCAST_NLINE,
131        CC_SEND_XRAM_RSP_INVAL_HEADER,
132        CC_SEND_XRAM_RSP_INVAL_NLINE,
133        CC_SEND_WRITE_BRDCAST_HEADER,
134        CC_SEND_WRITE_BRDCAST_NLINE,
135        CC_SEND_WRITE_UPDT_HEADER,
136        CC_SEND_WRITE_UPDT_NLINE,
137        CC_SEND_WRITE_UPDT_DATA,
138        CC_SEND_CAS_BRDCAST_HEADER,
139        CC_SEND_CAS_BRDCAST_NLINE,
140        CC_SEND_CAS_UPDT_HEADER,
141        CC_SEND_CAS_UPDT_NLINE,
142        CC_SEND_CAS_UPDT_DATA,
143        CC_SEND_CAS_UPDT_DATA_HIGH
144      };
145
146      /* States of the MULTI_ACK fsm */
147      enum multi_ack_fsm_state_e
148      {
149        MULTI_ACK_IDLE,
150        MULTI_ACK_UPT_LOCK,
151        MULTI_ACK_UPT_CLEAR,
152        MULTI_ACK_WRITE_RSP,
153        MULTI_ACK_CONFIG_ACK
154      };
155
156      /* States of the CONFIG fsm */
157      enum config_fsm_state_e
158      {
159        CONFIG_IDLE,
160        CONFIG_LOOP,
161        CONFIG_RSP,
162        CONFIG_DIR_REQ,
163        CONFIG_DIR_ACCESS,
164        CONFIG_DIR_IVT_LOCK,
165        CONFIG_BC_SEND,
166        CONFIG_BC_WAIT,
167        CONFIG_INV_SEND,
168        CONFIG_HEAP_REQ,
169        CONFIG_HEAP_SCAN,
170        CONFIG_HEAP_LAST,
171        CONFIG_INV_WAIT
172      };
173
174      /* States of the READ fsm */
175      enum read_fsm_state_e
176      {
177        READ_IDLE,
178        READ_DIR_REQ,
179        READ_DIR_LOCK,
180        READ_DIR_HIT,
181        READ_HEAP_REQ,
182        READ_HEAP_LOCK,
183        READ_HEAP_WRITE,
184        READ_HEAP_ERASE,
185        READ_HEAP_LAST,
186        READ_RSP,
187        READ_TRT_LOCK,
188        READ_TRT_SET,
189        READ_TRT_REQ
190      };
191
192      /* States of the WRITE fsm */
193      enum write_fsm_state_e
194      {
195        WRITE_IDLE,
196        WRITE_NEXT,
197        WRITE_DIR_REQ,
198        WRITE_DIR_LOCK,
199        WRITE_DIR_READ,
200        WRITE_DIR_HIT,
201        WRITE_UPT_LOCK,
202        WRITE_UPT_HEAP_LOCK,
203        WRITE_UPT_REQ,
204        WRITE_UPT_NEXT,
205        WRITE_UPT_DEC,
206        WRITE_RSP,
207        WRITE_MISS_TRT_LOCK,
208        WRITE_MISS_TRT_DATA,
209        WRITE_MISS_TRT_SET,
210        WRITE_MISS_XRAM_REQ,
211        WRITE_BC_TRT_LOCK,
212        WRITE_BC_IVT_LOCK,
213        WRITE_BC_DIR_INVAL,
214        WRITE_BC_CC_SEND,
215        WRITE_BC_XRAM_REQ,
216        WRITE_WAIT
217      };
218
219      /* States of the IXR_RSP fsm */
220      enum ixr_rsp_fsm_state_e
221      {
222        IXR_RSP_IDLE,
223        IXR_RSP_ACK,
224        IXR_RSP_TRT_ERASE,
225        IXR_RSP_TRT_READ
226      };
227
228      /* States of the XRAM_RSP fsm */
229      enum xram_rsp_fsm_state_e
230      {
231        XRAM_RSP_IDLE,
232        XRAM_RSP_TRT_COPY,
233        XRAM_RSP_TRT_DIRTY,
234        XRAM_RSP_DIR_LOCK,
235        XRAM_RSP_DIR_UPDT,
236        XRAM_RSP_DIR_RSP,
237        XRAM_RSP_INVAL_LOCK,
238        XRAM_RSP_INVAL_WAIT,
239        XRAM_RSP_INVAL,
240        XRAM_RSP_WRITE_DIRTY,
241        XRAM_RSP_HEAP_REQ,
242        XRAM_RSP_HEAP_ERASE,
243        XRAM_RSP_HEAP_LAST,
244        XRAM_RSP_ERROR_ERASE,
245        XRAM_RSP_ERROR_RSP
246      };
247
248      /* States of the IXR_CMD fsm */
249      enum ixr_cmd_fsm_state_e
250      {
251        IXR_CMD_READ_IDLE,
252        IXR_CMD_WRITE_IDLE,
253        IXR_CMD_CAS_IDLE,
254        IXR_CMD_XRAM_IDLE,
255        IXR_CMD_READ,
256        IXR_CMD_WRITE,
257        IXR_CMD_CAS,
258        IXR_CMD_XRAM
259      };
260
261      /* States of the CAS fsm */
262      enum cas_fsm_state_e
263      {
264        CAS_IDLE,
265        CAS_DIR_REQ,
266        CAS_DIR_LOCK,
267        CAS_DIR_HIT_READ,
268        CAS_DIR_HIT_COMPARE,
269        CAS_DIR_HIT_WRITE,
270        CAS_UPT_LOCK,
271        CAS_UPT_HEAP_LOCK,
272        CAS_UPT_REQ,
273        CAS_UPT_NEXT,
274        CAS_BC_TRT_LOCK,
275        CAS_BC_IVT_LOCK,
276        CAS_BC_DIR_INVAL,
277        CAS_BC_CC_SEND,
278        CAS_BC_XRAM_REQ,
279        CAS_RSP_FAIL,
280        CAS_RSP_SUCCESS,
281        CAS_MISS_TRT_LOCK,
282        CAS_MISS_TRT_SET,
283        CAS_MISS_XRAM_REQ,
284        CAS_WAIT
285      };
286
287      /* States of the CLEANUP fsm */
288      enum cleanup_fsm_state_e
289      {
290        CLEANUP_IDLE,
291        CLEANUP_GET_NLINE,
292        CLEANUP_DIR_REQ,
293        CLEANUP_DIR_LOCK,
294        CLEANUP_DIR_WRITE,
295        CLEANUP_HEAP_REQ,
296        CLEANUP_HEAP_LOCK,
297        CLEANUP_HEAP_SEARCH,
298        CLEANUP_HEAP_CLEAN,
299        CLEANUP_HEAP_FREE,
300        CLEANUP_IVT_LOCK,
301        CLEANUP_IVT_DECREMENT,
302        CLEANUP_IVT_CLEAR,
303        CLEANUP_WRITE_RSP,
304        CLEANUP_CONFIG_ACK,
305        CLEANUP_SEND_CLACK
306      };
307
308      /* States of the ALLOC_DIR fsm */
309      enum alloc_dir_fsm_state_e
310      {
311        ALLOC_DIR_RESET,
312        ALLOC_DIR_CONFIG,
313        ALLOC_DIR_READ,
314        ALLOC_DIR_WRITE,
315        ALLOC_DIR_CAS,
316        ALLOC_DIR_CLEANUP,
317        ALLOC_DIR_XRAM_RSP
318      };
319
320      /* States of the ALLOC_TRT fsm */
321      enum alloc_trt_fsm_state_e
322      {
323        ALLOC_TRT_READ,
324        ALLOC_TRT_WRITE,
325        ALLOC_TRT_CAS,
326        ALLOC_TRT_XRAM_RSP,
327        ALLOC_TRT_IXR_RSP
328      };
329
330      /* States of the ALLOC_UPT fsm */
331      enum alloc_upt_fsm_state_e
332      {
333        ALLOC_UPT_WRITE,
334        ALLOC_UPT_CAS,
335        ALLOC_UPT_MULTI_ACK
336      };
337
338      /* States of the ALLOC_IVT fsm */
339      enum alloc_ivt_fsm_state_e
340      {
341        ALLOC_IVT_WRITE,
342        ALLOC_IVT_XRAM_RSP,
343        ALLOC_IVT_CLEANUP,
344        ALLOC_IVT_CAS,
345        ALLOC_IVT_CONFIG
346      };
347
348      /* States of the ALLOC_HEAP fsm */
349      enum alloc_heap_fsm_state_e
350      {
351        ALLOC_HEAP_RESET,
352        ALLOC_HEAP_READ,
353        ALLOC_HEAP_WRITE,
354        ALLOC_HEAP_CAS,
355        ALLOC_HEAP_CLEANUP,
356        ALLOC_HEAP_XRAM_RSP,
357        ALLOC_HEAP_CONFIG
358      };
359
360      /* transaction type, pktid field */
361      enum transaction_type_e
362      {
363          // b3 unused
364          // b2 READ / NOT READ
365          // Si READ
366          //  b1 DATA / INS
367          //  b0 UNC / MISS
368          // Si NOT READ
369          //  b1 accÚs table llsc type SW / other
370          //  b2 WRITE/CAS/LL/SC
371          TYPE_READ_DATA_UNC          = 0x0,
372          TYPE_READ_DATA_MISS         = 0x1,
373          TYPE_READ_INS_UNC           = 0x2,
374          TYPE_READ_INS_MISS          = 0x3,
375          TYPE_WRITE                  = 0x4,
376          TYPE_CAS                    = 0x5,
377          TYPE_LL                     = 0x6,
378          TYPE_SC                     = 0x7
379      };
380
381      /* SC return values */
382      enum sc_status_type_e
383      {
384          SC_SUCCESS  =   0x00000000,
385          SC_FAIL     =   0x00000001
386      };
387
388      /* Configuration commands */
389      enum cmd_config_type_e
390      {
391          CMD_CONFIG_INVAL = 0,
392          CMD_CONFIG_SYNC  = 1
393      };
394
395      // debug variables (for each FSM)
396      bool                 m_debug;
397      bool                 m_debug_previous_valid;
398      size_t               m_debug_previous_count;
399      bool                 m_debug_previous_dirty;
400      sc_signal<data_t>*   m_debug_previous_data;
401      sc_signal<data_t>*   m_debug_data;
402
403      bool         m_monitor_ok;
404      addr_t       m_monitor_base;
405      addr_t       m_monitor_length;
406
407      // instrumentation counters
408      uint32_t     m_cpt_cycles;        // Counter of cycles
409
410      uint32_t     m_cpt_read;          // Number of READ transactions
411      uint32_t     m_cpt_read_remote;   // number of remote READ transactions
412      uint32_t     m_cpt_read_flits;    // number of flits for READs
413      uint32_t     m_cpt_read_cost;     // Number of (flits * distance) for READs
414
415      uint32_t     m_cpt_read_miss;     // Number of MISS READ
416
417      uint32_t     m_cpt_write;         // Number of WRITE transactions
418      uint32_t     m_cpt_write_remote;  // number of remote WRITE transactions
419      uint32_t     m_cpt_write_flits;   // number of flits for WRITEs
420      uint32_t     m_cpt_write_cost;    // Number of (flits * distance) for WRITEs
421
422      uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
423      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
424      uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
425      uint32_t     m_cpt_update;        // Number of UPDATE transactions
426      uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
427      uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
428      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
429      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
430      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
431      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
432      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
433      uint32_t     m_cpt_ll;            // Number of LL transactions
434      uint32_t     m_cpt_sc;            // Number of SC transactions
435      uint32_t     m_cpt_cas;           // Number of CAS transactions
436
437      uint32_t     m_cpt_cleanup_cost;  // Number of (flits * distance) for CLEANUPs
438
439      uint32_t     m_cpt_update_flits;  // Number of flits for UPDATEs
440      uint32_t     m_cpt_update_cost;   // Number of (flits * distance) for UPDATEs
441
442      uint32_t     m_cpt_inval_cost;    // Number of (flits * distance) for INVALs
443
444      uint32_t     m_cpt_get;
445
446      uint32_t     m_cpt_put;
447
448      size_t       m_prev_count;
449
450      protected:
451
452      SC_HAS_PROCESS(VciMemCache);
453
454      public:
455      sc_in<bool>                                 p_clk;
456      sc_in<bool>                                 p_resetn;
457      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
458      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
459      soclib::caba::DspinInput<dspin_in_width>    p_dspin_p2m;
460      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_m2p;
461      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_clack;
462
463      VciMemCache(
464          sc_module_name name,                                // Instance Name
465          const soclib::common::MappingTable &mtp,            // Mapping table INT network
466          const soclib::common::MappingTable &mtx,            // Mapping table RAM network
467          const soclib::common::IntTab       &srcid_x,        // global index RAM network
468          const soclib::common::IntTab       &tgtid_d,        // global index INT network
469          const size_t                       cc_global_id,    // global index CC network
470          const size_t                       nways,           // Number of ways per set
471          const size_t                       nsets,           // Number of sets
472          const size_t                       nwords,          // Number of words per line
473          const size_t                       max_copies,      // max number of copies
474          const size_t                       heap_size=HEAP_ENTRIES,
475          const size_t                       trt_lines=TRT_ENTRIES, 
476          const size_t                       upt_lines=UPT_ENTRIES,     
477          const size_t                       ivt_lines=IVT_ENTRIES,     
478          const size_t                       debug_start_cycle=0,
479          const bool                         debug_ok=false );
480
481      ~VciMemCache();
482
483      void print_stats();
484      void print_trace();
485      void cache_monitor(addr_t addr);
486      void start_monitor(addr_t addr, addr_t length);
487      void stop_monitor();
488
489      private:
490
491      void transition();
492      void genMoore();
493      void check_monitor(addr_t addr, data_t data, bool read);
494
495      // Component attributes
496      std::list<soclib::common::Segment> m_seglist;          // segments allocated
497      size_t                             m_nseg;             // number of segments
498      soclib::common::Segment            **m_seg;            // array of segments pointers
499      size_t                             m_seg_config;       // config segment index
500      const size_t                       m_srcid_x;          // global index on RAM network
501      const size_t                       m_initiators;       // Number of initiators
502      const size_t                       m_heap_size;        // Size of the heap
503      const size_t                       m_ways;             // Number of ways in a set
504      const size_t                       m_sets;             // Number of cache sets
505      const size_t                       m_words;            // Number of words in a line
506      const size_t                       m_cc_global_id;     // global_index on cc network
507      size_t                             m_debug_start_cycle;
508      bool                               m_debug_ok;
509      uint32_t                           m_trt_lines;
510      TransactionTab                     m_trt;              // xram transaction table
511      uint32_t                           m_upt_lines;
512      UpdateTab                          m_upt;              // pending update
513      UpdateTab                          m_ivt;              // pending invalidate
514      CacheDirectory                     m_cache_directory;  // data cache directory
515      CacheData                          m_cache_data;       // data array[set][way][word]
516      HeapDirectory                      m_heap;             // heap for copies
517      size_t                             m_max_copies;       // max number of copies in heap
518      GenericLLSCGlobalTable
519      < 32  ,    // number of slots
520        4096,    // number of processors in the system
521        8000,    // registration life (# of LL operations)
522        addr_t >                         m_llsc_table;       // ll/sc registration table
523
524      // adress masks
525      const soclib::common::AddressMaskingTable<addr_t>   m_x;
526      const soclib::common::AddressMaskingTable<addr_t>   m_y;
527      const soclib::common::AddressMaskingTable<addr_t>   m_z;
528      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
529
530      // broadcast address
531      uint32_t                           m_broadcast_boundaries;
532
533      //////////////////////////////////////////////////
534      // Registers controlled by the TGT_CMD fsm
535      //////////////////////////////////////////////////
536
537      sc_signal<int>         r_tgt_cmd_fsm;
538
539      // Fifo between TGT_CMD fsm and READ fsm
540      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
541      GenericFifo<size_t>    m_cmd_read_length_fifo;
542      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
543      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
544      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
545
546      // Fifo between TGT_CMD fsm and WRITE fsm
547      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
548      GenericFifo<bool>      m_cmd_write_eop_fifo;
549      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
550      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
551      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
552      GenericFifo<data_t>    m_cmd_write_data_fifo;
553      GenericFifo<be_t>      m_cmd_write_be_fifo;
554
555      // Fifo between TGT_CMD fsm and CAS fsm
556      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
557      GenericFifo<bool>      m_cmd_cas_eop_fifo;
558      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
559      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
560      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
561      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
562
563      // Fifo between CC_RECEIVE fsm and CLEANUP fsm
564      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
565     
566      // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
567      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
568
569      // Buffer between TGT_CMD fsm and TGT_RSP fsm
570      // (segmentation violation response request)
571      sc_signal<bool>     r_tgt_cmd_to_tgt_rsp_req;
572
573      sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
574      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_error;
575      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_srcid;
576      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_trdid;
577      sc_signal<size_t>   r_tgt_cmd_to_tgt_rsp_pktid;
578
579      sc_signal<addr_t>   r_tgt_cmd_config_addr;
580      sc_signal<size_t>   r_tgt_cmd_config_cmd;
581
582      ///////////////////////////////////////////////////////
583      // Registers controlled by the CONFIG fsm
584      ///////////////////////////////////////////////////////
585
586      sc_signal<int>      r_config_fsm;            // FSM state
587      sc_signal<bool>     r_config_lock;           // lock protecting exclusive access
588      sc_signal<int>      r_config_cmd;            // config request status
589      sc_signal<addr_t>   r_config_address;        // target buffer physical address
590      sc_signal<size_t>   r_config_srcid;          // config request srcid
591      sc_signal<size_t>   r_config_trdid;          // config request trdid
592      sc_signal<size_t>   r_config_pktid;          // config request pktid
593      sc_signal<size_t>   r_config_nlines;         // number of lines covering the buffer
594      sc_signal<size_t>   r_config_dir_way;        // DIR: selected way
595      sc_signal<size_t>   r_config_dir_count;      // DIR: number of copies
596      sc_signal<bool>     r_config_dir_is_cnt;     // DIR: counter mode (broadcast required)
597      sc_signal<size_t>   r_config_dir_copy_srcid; // DIR: first copy SRCID
598      sc_signal<bool>     r_config_dir_copy_inst;  // DIR: first copy L1 type
599      sc_signal<size_t>   r_config_dir_next_ptr;   // DIR: index of next copy in HEAP
600      sc_signal<size_t>   r_config_heap_next;      // current pointer to scan HEAP
601
602      sc_signal<size_t>   r_config_ivt_index;      // IVT index
603
604      // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
605      sc_signal<bool>     r_config_to_tgt_rsp_req;    // valid request
606      sc_signal<bool>     r_config_to_tgt_rsp_error;  // error response
607      sc_signal<size_t>   r_config_to_tgt_rsp_srcid;  // Transaction srcid
608      sc_signal<size_t>   r_config_to_tgt_rsp_trdid;  // Transaction trdid
609      sc_signal<size_t>   r_config_to_tgt_rsp_pktid;  // Transaction pktid
610
611      // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
612      sc_signal<bool>     r_config_to_cc_send_multi_req;    // multi-inval request
613      sc_signal<bool>     r_config_to_cc_send_brdcast_req;  // broadcast-inval request
614      sc_signal<addr_t>   r_config_to_cc_send_nline;        // line index
615      sc_signal<size_t>   r_config_to_cc_send_trdid;        // UPT index
616      GenericFifo<bool>   m_config_to_cc_send_inst_fifo;    // fifo for the L1 type
617      GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;   // fifo for owners srcid
618
619#if L1_MULTI_CACHE
620      GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id
621#endif
622
623      ///////////////////////////////////////////////////////
624      // Registers controlled by the READ fsm
625      ///////////////////////////////////////////////////////
626
627      sc_signal<int>      r_read_fsm;          // FSM state
628      sc_signal<size_t>   r_read_copy;         // Srcid of the first copy
629      sc_signal<size_t>   r_read_copy_cache;   // Srcid of the first copy
630      sc_signal<bool>     r_read_copy_inst;    // Type of the first copy
631      sc_signal<tag_t>    r_read_tag;          // cache line tag (in directory)
632      sc_signal<bool>     r_read_is_cnt;       // is_cnt bit (in directory)
633      sc_signal<bool>     r_read_lock;         // lock bit (in directory)
634      sc_signal<bool>     r_read_dirty;        // dirty bit (in directory)
635      sc_signal<size_t>   r_read_count;        // number of copies
636      sc_signal<size_t>   r_read_ptr;          // pointer to the heap
637      sc_signal<data_t> * r_read_data;         // data (one cache line)
638      sc_signal<size_t>   r_read_way;          // associative way (in cache)
639      sc_signal<size_t>   r_read_trt_index;    // Transaction Table index
640      sc_signal<size_t>   r_read_next_ptr;     // Next entry to point to
641      sc_signal<bool>     r_read_last_free;    // Last free entry
642      sc_signal<addr_t>   r_read_ll_key;       // LL key from the llsc_global_table
643
644      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
645      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
646      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
647      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
648
649      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
650      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
651      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
652      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
653      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
654      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
655      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
656      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
657      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
658
659      ///////////////////////////////////////////////////////////////
660      // Registers controlled by the WRITE fsm
661      ///////////////////////////////////////////////////////////////
662
663      sc_signal<int>      r_write_fsm;        // FSM state
664      sc_signal<addr_t>   r_write_address;    // first word address
665      sc_signal<size_t>   r_write_word_index; // first word index in line
666      sc_signal<size_t>   r_write_word_count; // number of words in line
667      sc_signal<size_t>   r_write_srcid;      // transaction srcid
668      sc_signal<size_t>   r_write_trdid;      // transaction trdid
669      sc_signal<size_t>   r_write_pktid;      // transaction pktid
670      sc_signal<data_t> * r_write_data;       // data (one cache line)
671      sc_signal<be_t>   * r_write_be;         // one byte enable per word
672      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
673      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
674      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
675      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
676      sc_signal<size_t>   r_write_copy;       // first owner of the line
677      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
678      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
679      sc_signal<size_t>   r_write_count;      // number of copies
680      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
681      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
682      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
683      sc_signal<size_t>   r_write_way;        // way of the line
684      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
685      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
686      sc_signal<bool>     r_write_sc_fail;    // sc command failed
687      sc_signal<bool>     r_write_pending_sc; // sc command pending
688
689      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
690      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
691      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
692      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
693      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
694      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
695
696      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
697      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
698      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
699      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
700      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
701      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
702
703      // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
704      sc_signal<bool>     r_write_to_cc_send_multi_req;     // valid multicast request
705      sc_signal<bool>     r_write_to_cc_send_brdcast_req;   // valid brdcast request
706      sc_signal<addr_t>   r_write_to_cc_send_nline;         // cache line index
707      sc_signal<size_t>   r_write_to_cc_send_trdid;         // index in Update Table
708      sc_signal<data_t> * r_write_to_cc_send_data;          // data (one cache line)
709      sc_signal<be_t>   * r_write_to_cc_send_be;            // word enable
710      sc_signal<size_t>   r_write_to_cc_send_count;         // number of words in line
711      sc_signal<size_t>   r_write_to_cc_send_index;         // index of first word in line
712      GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
713      GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
714
715#if L1_MULTI_CACHE
716      GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
717#endif
718
719      // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
720      sc_signal<bool>     r_write_to_multi_ack_req;       // valid request
721      sc_signal<size_t>   r_write_to_multi_ack_upt_index; // index in update table
722
723      /////////////////////////////////////////////////////////
724      // Registers controlled by MULTI_ACK fsm
725      //////////////////////////////////////////////////////////
726
727      sc_signal<int>      r_multi_ack_fsm;       // FSM state
728      sc_signal<size_t>   r_multi_ack_upt_index; // index in the Update Table
729      sc_signal<size_t>   r_multi_ack_srcid;     // pending write srcid
730      sc_signal<size_t>   r_multi_ack_trdid;     // pending write trdid
731      sc_signal<size_t>   r_multi_ack_pktid;     // pending write pktid
732      sc_signal<addr_t>   r_multi_ack_nline;     // pending write nline
733
734      // signaling completion of multi-inval to CONFIG fsm
735      sc_signal<bool>     r_multi_ack_to_config_ack; 
736
737      // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
738      sc_signal<bool>     r_multi_ack_to_tgt_rsp_req;   // valid request
739      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
740      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
741      sc_signal<size_t>   r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
742
743      ///////////////////////////////////////////////////////
744      // Registers controlled by CLEANUP fsm
745      ///////////////////////////////////////////////////////
746
747      sc_signal<int>      r_cleanup_fsm;           // FSM state
748      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
749      sc_signal<bool>     r_cleanup_inst;          // Instruction or Data ?
750      sc_signal<size_t>   r_cleanup_way_index;     // L1 Cache Way index
751      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
752
753#if L1_MULTI_CACHE
754      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
755#endif
756
757      sc_signal<copy_t>   r_cleanup_copy;          // first copy
758      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
759      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
760      sc_signal<copy_t>   r_cleanup_count;         // number of copies
761      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
762      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
763      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
764      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
765      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
766      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
767      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
768      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
769      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
770      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
771      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
772
773      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write rsp
774      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
775      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
776
777      sc_signal<bool>     r_cleanup_need_rsp;      // write response required
778      sc_signal<bool>     r_cleanup_need_ack;      // config acknowledge required
779
780      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
781
782      // signaling completion of broadcast-inval to CONFIG fsm
783      sc_signal<bool>     r_cleanup_to_config_ack; 
784       
785      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
786      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
787      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
788      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
789      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
790
791      ///////////////////////////////////////////////////////
792      // Registers controlled by CAS fsm
793      ///////////////////////////////////////////////////////
794
795      sc_signal<int>      r_cas_fsm;        // FSM state
796      sc_signal<data_t>   r_cas_wdata;      // write data word
797      sc_signal<data_t> * r_cas_rdata;      // read data word
798      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
799      sc_signal<size_t>   r_cas_cpt;        // size of command
800      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
801      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
802      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
803      sc_signal<size_t>   r_cas_count;      // number of copies
804      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
805      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
806      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
807      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
808      sc_signal<size_t>   r_cas_way;        // way in directory
809      sc_signal<size_t>   r_cas_set;        // set in directory
810      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
811      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
812      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
813      sc_signal<data_t> * r_cas_data;       // cache line data
814
815      // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
816      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
817      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
818      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
819      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
820      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
821
822
823      // Buffer between CAS fsm and TGT_RSP fsm
824      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
825      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
826      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
827      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
828      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
829
830      // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
831      sc_signal<bool>     r_cas_to_cc_send_multi_req;     // valid request
832      sc_signal<bool>     r_cas_to_cc_send_brdcast_req;   // brdcast request
833      sc_signal<addr_t>   r_cas_to_cc_send_nline;         // cache line index
834      sc_signal<size_t>   r_cas_to_cc_send_trdid;         // index in Update Table
835      sc_signal<data_t>   r_cas_to_cc_send_wdata;         // data (one word)
836      sc_signal<bool>     r_cas_to_cc_send_is_long;       // it is a 64 bits CAS
837      sc_signal<data_t>   r_cas_to_cc_send_wdata_high;    // data high (one word)
838      sc_signal<size_t>   r_cas_to_cc_send_index;         // index of the word in line
839      GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
840      GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
841
842#if L1_MULTI_CACHE
843      GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
844#endif
845
846      ////////////////////////////////////////////////////
847      // Registers controlled by the IXR_RSP fsm
848      ////////////////////////////////////////////////////
849
850      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
851      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
852      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
853
854      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
855      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
856
857      ////////////////////////////////////////////////////
858      // Registers controlled by the XRAM_RSP fsm
859      ////////////////////////////////////////////////////
860
861      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
862      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
863      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
864      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
865      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
866      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
867      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
868      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
869      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
870      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
871      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
872      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
873      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
874      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
875      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
876      sc_signal<size_t>   r_xram_rsp_ivt_index;         // IVT entry index
877      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
878
879      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
880      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
881      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
882      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
883      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
884      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
885      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
886      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
887      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
888      sc_signal<addr_t>   r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
889
890      // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
891      sc_signal<bool>     r_xram_rsp_to_cc_send_multi_req;     // Valid request
892      sc_signal<bool>     r_xram_rsp_to_cc_send_brdcast_req;   // Broadcast request
893      sc_signal<addr_t>   r_xram_rsp_to_cc_send_nline;         // cache line index;
894      sc_signal<size_t>   r_xram_rsp_to_cc_send_trdid;         // index of UPT entry
895      GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
896      GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
897
898#if L1_MULTI_CACHE
899      GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
900#endif
901
902      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
903      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
904      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
905      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
906      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
907
908      ////////////////////////////////////////////////////
909      // Registers controlled by the IXR_CMD fsm
910      ////////////////////////////////////////////////////
911
912      sc_signal<int>      r_ixr_cmd_fsm;
913      sc_signal<size_t>   r_ixr_cmd_cpt;
914
915      ////////////////////////////////////////////////////
916      // Registers controlled by TGT_RSP fsm
917      ////////////////////////////////////////////////////
918
919      sc_signal<int>      r_tgt_rsp_fsm;
920      sc_signal<size_t>   r_tgt_rsp_cpt;
921      sc_signal<bool>     r_tgt_rsp_key_sent;
922
923      ////////////////////////////////////////////////////
924      // Registers controlled by CC_SEND fsm
925      ////////////////////////////////////////////////////
926
927      sc_signal<int>      r_cc_send_fsm;
928      sc_signal<size_t>   r_cc_send_cpt;
929      sc_signal<bool>     r_cc_send_inst;
930
931      ////////////////////////////////////////////////////
932      // Registers controlled by CC_RECEIVE fsm
933      ////////////////////////////////////////////////////
934
935      sc_signal<int>      r_cc_receive_fsm;
936
937      ////////////////////////////////////////////////////
938      // Registers controlled by ALLOC_DIR fsm
939      ////////////////////////////////////////////////////
940
941      sc_signal<int>      r_alloc_dir_fsm;
942      sc_signal<unsigned> r_alloc_dir_reset_cpt;
943
944      ////////////////////////////////////////////////////
945      // Registers controlled by ALLOC_TRT fsm
946      ////////////////////////////////////////////////////
947
948      sc_signal<int>      r_alloc_trt_fsm;
949
950      ////////////////////////////////////////////////////
951      // Registers controlled by ALLOC_UPT fsm
952      ////////////////////////////////////////////////////
953
954      sc_signal<int>      r_alloc_upt_fsm;
955
956      ////////////////////////////////////////////////////
957      // Registers controlled by ALLOC_IVT fsm
958      ////////////////////////////////////////////////////
959
960      sc_signal<int>      r_alloc_ivt_fsm;
961
962      ////////////////////////////////////////////////////
963      // Registers controlled by ALLOC_HEAP fsm
964      ////////////////////////////////////////////////////
965
966      sc_signal<int>      r_alloc_heap_fsm;
967      sc_signal<unsigned> r_alloc_heap_reset_cpt;
968    }; // end class VciMemCache
969
970}}
971
972#endif
973
974// Local Variables:
975// tab-width: 2
976// c-basic-offset: 2
977// c-file-offsets:((innamespace . 0)(inline-open . 0))
978// indent-tabs-mode: nil
979// End:
980
981// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
982
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