Changeset 499 for trunk/modules
- Timestamp:
- Aug 27, 2013, 6:21:19 PM (11 years ago)
- Location:
- trunk/modules/vci_mem_cache/caba/source
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
r489 r499 225 225 226 226 #define L2 soclib::common::uint32_log2 227 const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);228 const tag_t tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));227 const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1); 228 const tag_t tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2)); 229 229 #undef L2 230 230 231 bool hit = false; 232 for ( size_t i=0 ; i<m_ways ; i++ ) { 233 bool equal = ( m_dir_tab[set][i].tag == tag ); 234 bool valid = m_dir_tab[set][i].valid; 235 hit = equal && valid; 236 if ( hit ) { 237 way = i; 238 break; 231 bool hit = false; 232 for ( size_t i=0 ; i<m_ways ; i++ ) 233 { 234 bool equal = ( m_dir_tab[set][i].tag == tag ); 235 bool valid = m_dir_tab[set][i].valid; 236 hit = equal && valid; 237 if ( hit ) 238 { 239 way = i; 240 break; 241 } 242 } 243 if ( hit ) 244 { 245 m_lru_tab[set][way].recent = true; 246 return DirectoryEntry(m_dir_tab[set][way]); 239 247 } 240 } 241 if ( hit ) { 242 m_lru_tab[set][way].recent = true; 243 return DirectoryEntry(m_dir_tab[set][way]); 244 } else { 245 return DirectoryEntry(); 246 } 248 else 249 { 250 return DirectoryEntry(); 251 } 247 252 } // end read() 248 253 -
trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r489 r499 609 609 sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index 610 610 611 612 611 // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) 613 612 sc_signal<bool> r_config_to_tgt_rsp_req; // valid request -
trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r496 r499 926 926 bool config = false; 927 927 928 // register arguments for response (segmentation violation or config)929 r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read();930 r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read();931 r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read();932 933 928 for(size_t seg_id = 0 ; (seg_id < m_nseg) and not found ; seg_id++) 934 929 { … … 1014 1009 if ( p_vci_tgt.cmdval and p_vci_tgt.eop ) 1015 1010 { 1011 r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); 1012 r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read(); 1013 r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read(); 1016 1014 r_tgt_cmd_to_tgt_rsp_req = true; 1017 1015 r_tgt_cmd_to_tgt_rsp_error = 1; … … 1059 1057 } 1060 1058 else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock 1061 and (cell == MEMC_LOCK) 1062 and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) 1059 and (cell == MEMC_LOCK) ) 1063 1060 { 1064 1061 need_rsp = true; … … 1067 1064 } 1068 1065 else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo 1069 and (cell == MEMC_ADDR_LO) 1070 and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) 1066 and (cell == MEMC_ADDR_LO) ) 1071 1067 { 1072 1068 assert( ((wdata % (m_words*vci_param_int::B)) == 0) and … … 1076 1072 error = 0; 1077 1073 r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) | 1078 ( addr_t)p_vci_tgt.wdata.read();1074 ((addr_t)wdata); 1079 1075 } 1080 1076 else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi 1081 and (cell == MEMC_ADDR_HI) 1082 and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) 1077 and (cell == MEMC_ADDR_HI) ) 1083 1078 1084 1079 { … … 1086 1081 error = 0; 1087 1082 r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | 1088 (( addr_t)p_vci_tgt.wdata.read())<<32;1083 (((addr_t)wdata)<<32); 1089 1084 } 1090 1085 else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines 1091 and (cell == MEMC_BUF_LENGTH) 1092 and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) 1086 and (cell == MEMC_BUF_LENGTH) ) 1093 1087 { 1094 1088 need_rsp = true; 1095 1089 error = 0; 1096 size_t lines = (size_t)(p_vci_tgt.wdata.read()/(m_words<<2));1097 if ( r_config_address.read()%(m_words*4) ) lines++;1090 size_t lines = wdata/(m_words<<2); 1091 if ( wdata%(m_words<<2) ) lines++; 1098 1092 r_config_cmd_lines = lines; 1099 1093 r_config_rsp_lines = lines; 1100 1094 } 1101 1095 else if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type 1102 and (cell == MEMC_CMD_TYPE) 1103 and (p_vci_tgt.srcid.read() == r_tgt_cmd_srcid.read()) ) 1096 and (cell == MEMC_CMD_TYPE) ) 1104 1097 { 1105 1098 need_rsp = false; 1106 1099 error = 0; 1107 r_config_cmd = p_vci_tgt.wdata.read();1100 r_config_cmd = wdata; 1108 1101 1109 1102 // prepare delayed response from CONFIG FSM … … 1123 1116 if ( r_tgt_cmd_to_tgt_rsp_req.read() ) break; 1124 1117 1118 r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); 1119 r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read(); 1120 r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read(); 1125 1121 r_tgt_cmd_to_tgt_rsp_req = true; 1126 1122 r_tgt_cmd_to_tgt_rsp_error = error; … … 1560 1556 DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way); 1561 1557 1558 r_config_dir_way = way; 1559 r_config_dir_copy_inst = entry.owner.inst; 1560 r_config_dir_copy_srcid = entry.owner.srcid; 1561 r_config_dir_is_cnt = entry.is_cnt; 1562 r_config_dir_lock = entry.lock; 1563 r_config_dir_count = entry.count; 1564 r_config_dir_ptr = entry.ptr; 1565 1562 1566 if ( entry.valid and // hit & inval command 1563 1567 (r_config_cmd.read() == MEMC_CMD_INVAL) ) 1564 1568 { 1565 r_config_dir_way = way; 1566 r_config_dir_copy_inst = entry.owner.inst; 1567 r_config_dir_copy_srcid = entry.owner.srcid; 1568 r_config_dir_is_cnt = entry.is_cnt; 1569 r_config_dir_lock = entry.lock; 1570 r_config_dir_count = entry.count; 1571 r_config_dir_ptr = entry.ptr; 1572 1573 r_config_fsm = CONFIG_IVT_LOCK; 1569 r_config_fsm = CONFIG_IVT_LOCK; 1574 1570 } 1575 1571 else if ( entry.valid and // hit & sync command … … 1577 1573 (r_config_cmd.read() == MEMC_CMD_SYNC) ) 1578 1574 { 1579 r_config_fsm = CONFIG_TRT_LOCK;1575 r_config_fsm = CONFIG_TRT_LOCK; 1580 1576 } 1581 1577 else // miss : return to LOOP … … 1583 1579 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 1584 1580 r_config_rsp_lines = r_config_rsp_lines.read() - 1; 1585 r_config_cmd_lines = r_config_cmd_lines.read() - 1;1586 1581 r_config_address = r_config_address.read() + (m_words<<2); 1587 1582 r_config_fsm = CONFIG_LOOP; … … 1635 1630 entry.owner.inst = r_config_dir_copy_inst.read(); 1636 1631 entry.owner.srcid = r_config_dir_copy_srcid.read(); 1637 m_cache_directory.write( set, 1638 way, 1639 entry ); 1632 m_cache_directory.write( set, way, entry ); 1640 1633 1641 1634 r_config_trt_index = index; … … 1663 1656 1664 1657 // read data into cache 1665 size_t way = r_config_dir_way.read(); 1666 size_t set = m_y[r_config_address.read()]; 1667 1668 sc_signal<data_t> config_data[16]; 1669 m_cache_data.read_line( way, 1670 set, 1671 config_data ); 1672 1673 // post a PUT request in TRT 1658 size_t way = r_config_dir_way.read(); 1659 size_t set = m_y[r_config_address.read()]; 1674 1660 std::vector<data_t> data_vector; 1675 1661 data_vector.clear(); 1676 for(size_t i=0; i<m_words; i++) data_vector.push_back(config_data[i].read()); 1662 for(size_t word=0; word<m_words; word++) 1663 { 1664 uint32_t data = m_cache_data.read( way, set, word ); 1665 data_vector.push_back( data ); 1666 } 1667 1668 // post the PUT request in TRT 1677 1669 m_trt.set( r_config_trt_index.read(), 1678 false, // PUT 1679 m_nline[r_config_address.read()], // nline1680 0, // srcid: unused1681 0, // trdid: unused1682 0, // pktid: unused1670 false, // PUT transaction 1671 m_nline[r_config_address.read()], // line index 1672 0, // srcid: unused 1673 0, // trdid: unused 1674 0, // pktid: unused 1683 1675 false, // not proc_read 1684 0, // read_length: unused 1685 0, // word_index: unused 1686 std::vector<be_t>(m_words,0xF), 1687 data_vector); 1676 0, // read_length: unused 1677 0, // word_index: unused 1678 std::vector<be_t>(m_words,0xF), // byte-enable: unused 1679 data_vector, // data to be written 1680 0, // ll_key: unused 1681 true ); // requested by config FSM 1682 r_config_fsm = CONFIG_PUT_REQ; 1688 1683 1689 1684 #if DEBUG_MEMC_CONFIG … … 1696 1691 } 1697 1692 //////////////////// 1698 case CONFIG_PUT_REQ: // PUT request to IXR_CMD_FSM1693 case CONFIG_PUT_REQ: // post PUT request to IXR_CMD_FSM 1699 1694 { 1700 1695 if ( not r_config_to_ixr_cmd_req.read() ) … … 1710 1705 #if DEBUG_MEMC_CONFIG 1711 1706 if(m_debug) 1712 std::cout << " <MEMC " << name() << " CONFIG_PUT_REQ> PUT request to IXR_CMD_FSM"1707 std::cout << " <MEMC " << name() << " CONFIG_PUT_REQ> post PUT request to IXR_CMD_FSM" 1713 1708 << " / address = " << std::hex << r_config_address.read() << std::endl; 1714 1709 #endif
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