- Timestamp:
- Oct 3, 2013, 4:34:55 PM (11 years ago)
- File:
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- 1 edited
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branches/ODCCP/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r494 r541 36 36 #define DEBUG_CLEANUP 1 37 37 #define INSTRUMENTATION 1 38 #define FETCH_ON_WRITE_ENABLE 138 #define FETCH_ON_WRITE_ENABLE 0 39 39 #define DEBUG_CMD 0 40 40 … … 596 596 float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); 597 597 std::cout << name() << std::endl 598 << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl 599 << "- READ RATE = " << (float)m_cpt_data_read/run_cycles << std::endl598 << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl; 599 /*<< "- READ RATE = " << (float)m_cpt_data_read/run_cycles << std::endl 600 600 << "- WRITE RATE = " << (float)m_cpt_data_write/run_cycles << std::endl 601 601 << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl … … 643 643 << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl 644 644 << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl 645 << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; 645 << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;*/ 646 646 } 647 /* 647 648 648 //////////////////////// 649 649 tmpl(void)::clear_stats() … … 660 660 661 661 m_cpt_frz_cycles = 0; 662 m_cpt_dcache_frz_cycles = 0;662 //m_cpt_dcache_frz_cycles = 0; 663 663 m_cpt_total_cycles = 0; 664 664 665 m_cpt_read = 0;666 m_cpt_write = 0;665 //m_cpt_read = 0; 666 //m_cpt_write = 0; 667 667 m_cpt_data_miss = 0; 668 668 m_cpt_ins_miss = 0; … … 728 728 m_cost_dtlb_sc_dirty_transaction = 0; 729 729 730 m_cpt_cc_update_data = 0;731 m_cpt_cc_inval_ins = 0;732 m_cpt_cc_inval_data = 0;730 //m_cpt_cc_update_data = 0; 731 //m_cpt_cc_inval_ins = 0; 732 //m_cpt_cc_inval_data = 0; 733 733 m_cpt_cc_broadcast = 0; 734 734 … … 742 742 } 743 743 744 */ 744 745 745 746 746 ///////////////////////// … … 1171 1171 1172 1172 // We register processor request 1173 ///*ODCCP*/ std::cout << "DEBUG IREQ.ADDR = " << std::hex << m_ireq.addr << std::dec << " | on " << name() << std::endl;1174 1173 r_icache_vaddr_save = m_ireq.addr; 1175 1174 … … 1632 1631 r_icache_miss_way = way; 1633 1632 r_icache_miss_set = set; 1634 1633 1635 1634 if ( cleanup ) 1636 1635 { … … 1924 1923 paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4; 1925 1924 paddr_t mask = ~((m_icache_words<<2)-1); 1925 1926 #if DEBUG_DCACHE 1927 if ( m_debug_activated ) 1928 { 1929 std::cout << " <PROC " << name() 1930 << std::hex 1931 << " ICACHE_CC_CHECK> paddr = " << paddr 1932 << " r_icache_vci_paddr = " << r_icache_vci_paddr.read() 1933 << " mask = " << mask 1934 << " (r_icache_fsm_save == ICACHE_MISS_WAIT) = " 1935 << (r_icache_fsm_save == ICACHE_MISS_WAIT) 1936 << " (r_icache_fsm_save == ICACHE_MISS_DIR_UPDT) = " 1937 << (r_icache_fsm_save == ICACHE_MISS_DIR_UPDT) 1938 << " ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) = " 1939 << ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) 1940 << std::dec 1941 << std::endl; 1942 } 1943 #endif 1926 1944 1927 1945 // CLACK handler … … 2070 2088 2071 2089 // Switch slot state to ZOMBI and send CLEANUP command 2072 r_icache.write_dir( 0, 2073 r_icache_cc_way.read(), 2090 r_icache.write_dir( r_icache_cc_way.read(), 2074 2091 r_icache_cc_set.read(), 2075 2092 CACHE_SLOT_STATE_ZOMBI ); … … 4013 4030 &word); 4014 4031 4015 /*if (m_proc_id == 1) { std::cout << "rdata XTN_FLUSH_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }4016 if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/4017 4018 4032 if(r_cc_send_data_fifo.wok()) 4019 4033 { … … 4281 4295 &word); 4282 4296 4283 /*if (m_proc_id == 1) { std::cout << "rdata XTN_INVAL_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }4284 if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/4285 4286 4297 if(r_cc_send_data_fifo.wok()) 4287 4298 { … … 4472 4483 &set, 4473 4484 &word); 4474 4475 /*if (m_proc_id == 1) { std::cout << "rdata MISS_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }4476 if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/4477 4485 4478 4486 if(r_cc_send_data_fifo.wok()) … … 5355 5363 &word); 5356 5364 5357 /*if (m_proc_id == 1) { std::cout << "rdata CC_INVAL_DATA = " << std::hex << rdata << std::dec << " | at cycle = " << m_cpt_total_cycles << std::endl; }5358 if (m_proc_id == 1) { r_cc_send_data_fifo.print(); }*/5359 5360 5365 if(r_cc_send_data_fifo.wok()) 5361 5366 {
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