Changeset 544 for branches/ODCCP/modules/vci_mem_cache/caba/source/include
- Timestamp:
- Oct 4, 2013, 2:34:03 PM (11 years ago)
- Location:
- branches/ODCCP/modules/vci_mem_cache/caba/source/include
- Files:
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- 3 edited
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. (modified) (1 prop)
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mem_cache_directory.h (modified) (1 diff)
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vci_mem_cache.h (modified) (20 diffs)
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branches/ODCCP/modules/vci_mem_cache/caba/source/include
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/trunk/modules/vci_mem_cache/caba/source/include merged eligible /branches/v5/modules/vci_mem_cache/caba/source/include 441-467
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branches/ODCCP/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
r494 r544 235 235 236 236 bool hit = false; 237 for ( size_t i=0 ; i<m_ways ; i++ ) { 237 for ( size_t i=0 ; i<m_ways ; i++ ) 238 { 238 239 bool equal = ( m_dir_tab[set][i].tag == tag ); 239 240 bool valid = m_dir_tab[set][i].valid; 240 241 hit = equal && valid; 241 if ( hit ) { 242 if ( hit ) 243 { 242 244 way = i; 243 245 break; 244 246 } 245 247 } 246 if ( hit ) { 248 if ( hit ) 249 { 247 250 m_lru_tab[set][way].recent = true; 248 251 return DirectoryEntry(m_dir_tab[set][way]); 249 } else { 252 } 253 else 254 { 250 255 return DirectoryEntry(); 251 256 } -
branches/ODCCP/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r494 r544 80 80 { 81 81 TGT_CMD_IDLE, 82 TGT_CMD_ERROR,83 82 TGT_CMD_READ, 84 83 TGT_CMD_WRITE, 85 84 TGT_CMD_CAS, 85 TGT_CMD_ERROR, 86 86 TGT_CMD_CONFIG 87 87 }; … … 90 90 enum tgt_rsp_fsm_state_e 91 91 { 92 TGT_RSP_CONFIG_IDLE,93 TGT_RSP_TGT_CMD_IDLE,94 92 TGT_RSP_READ_IDLE, 95 93 TGT_RSP_WRITE_IDLE, … … 98 96 TGT_RSP_MULTI_ACK_IDLE, 99 97 TGT_RSP_CLEANUP_IDLE, 100 TGT_RSP_CONFIG ,101 TGT_RSP_TGT_CMD ,98 TGT_RSP_CONFIG_IDLE, 99 TGT_RSP_TGT_CMD_IDLE, 102 100 TGT_RSP_READ, 103 101 TGT_RSP_WRITE, … … 105 103 TGT_RSP_XRAM, 106 104 TGT_RSP_MULTI_ACK, 107 TGT_RSP_CLEANUP 105 TGT_RSP_CLEANUP, 106 TGT_RSP_CONFIG, 107 TGT_RSP_TGT_CMD 108 108 }; 109 109 … … 120 120 enum cc_send_fsm_state_e 121 121 { 122 CC_SEND_CONFIG_IDLE,123 122 CC_SEND_XRAM_RSP_IDLE, 124 123 CC_SEND_WRITE_IDLE, 125 124 CC_SEND_CAS_IDLE, 126 CC_SEND_CONFIG_INVAL_HEADER, 127 CC_SEND_CONFIG_INVAL_NLINE, 128 CC_SEND_CONFIG_BRDCAST_HEADER, 129 CC_SEND_CONFIG_BRDCAST_NLINE, 125 CC_SEND_CONFIG_IDLE, 130 126 CC_SEND_XRAM_RSP_BRDCAST_HEADER, 131 127 CC_SEND_XRAM_RSP_BRDCAST_NLINE, … … 142 138 CC_SEND_CAS_UPDT_NLINE, 143 139 CC_SEND_CAS_UPDT_DATA, 144 CC_SEND_CAS_UPDT_DATA_HIGH 140 CC_SEND_CAS_UPDT_DATA_HIGH, 141 CC_SEND_CONFIG_INVAL_HEADER, 142 CC_SEND_CONFIG_INVAL_NLINE, 143 CC_SEND_CONFIG_BRDCAST_HEADER, 144 CC_SEND_CONFIG_BRDCAST_NLINE 145 145 }; 146 146 … … 324 324 { 325 325 ALLOC_DIR_RESET, 326 ALLOC_DIR_CONFIG,327 326 ALLOC_DIR_READ, 328 327 ALLOC_DIR_WRITE, 329 328 ALLOC_DIR_CAS, 330 329 ALLOC_DIR_CLEANUP, 331 ALLOC_DIR_XRAM_RSP 330 ALLOC_DIR_XRAM_RSP, 331 ALLOC_DIR_CONFIG 332 332 }; 333 333 … … 414 414 uint32_t m_cpt_cycles; // Counter of cycles 415 415 416 uint32_t m_cpt_read; // Number of READ transactions 416 // Counters accessible in software (not yet but eventually) 417 uint32_t m_cpt_read_local; // Number of local READ transactions 417 418 uint32_t m_cpt_read_remote; // number of remote READ transactions 418 uint32_t m_cpt_read_flits; // number of flits for READs419 419 uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs 420 420 421 uint32_t m_cpt_read_miss; // Number of MISS READ 422 423 uint32_t m_cpt_write; // Number of WRITE transactions 421 uint32_t m_cpt_write_local; // Number of local WRITE transactions 424 422 uint32_t m_cpt_write_remote; // number of remote WRITE transactions 425 uint32_t m_cpt_write_flits; // number of flits for WRITEs 423 uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs 424 uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs 426 425 uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs 427 426 427 uint32_t m_cpt_ll_local; // Number of local LL transactions 428 uint32_t m_cpt_ll_remote; // number of remote LL transactions 429 uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs 430 431 uint32_t m_cpt_sc_local; // Number of local SC transactions 432 uint32_t m_cpt_sc_remote; // number of remote SC transactions 433 uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs 434 435 uint32_t m_cpt_cas_local; // Number of local SC transactions 436 uint32_t m_cpt_cas_remote; // number of remote SC transactions 437 uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs 438 439 uint32_t m_cpt_update; // Number of requests causing an UPDATE 440 uint32_t m_cpt_update_local; // Number of local UPDATE transactions 441 uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions 442 uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT 443 444 uint32_t m_cpt_m_inval; // Number of requests causing M_INV 445 uint32_t m_cpt_m_inval_local; // Number of local M_INV transactions 446 uint32_t m_cpt_m_inval_remote; // Number of remote M_INV transactions 447 uint32_t m_cpt_m_inval_cost; // Number of (flits * distance) for M_INV 448 449 uint32_t m_cpt_br_inval; // Number of BROADCAST INVAL 450 451 uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions 452 uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions 453 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs 454 455 // Counters not accessible by software 456 uint32_t m_cpt_read_miss; // Number of MISS READ 428 457 uint32_t m_cpt_write_miss; // Number of MISS WRITE 429 uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions430 458 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 431 uint32_t m_cpt_update; // Number of UPDATE transactions 459 uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write 460 432 461 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt 433 462 uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt … … 441 470 uint32_t m_cpt_sc; // Number of SC transactions 442 471 uint32_t m_cpt_cas; // Number of CAS transactions 443 444 472 uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK 445 473 uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK … … 520 548 uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused 521 549 522 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs523 524 550 uint32_t m_cpt_update_flits; // Number of flits for UPDATEs 525 uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDATEs526 527 551 uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs 528 552 529 553 uint32_t m_cpt_get; 530 531 554 uint32_t m_cpt_put; 532 555 … … 546 569 soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack; 547 570 571 #if MONITOR_MEMCACHE_FSM == 1 572 sc_out<int> p_read_fsm; 573 sc_out<int> p_write_fsm; 574 sc_out<int> p_xram_rsp_fsm; 575 sc_out<int> p_cas_fsm; 576 sc_out<int> p_cleanup_fsm; 577 sc_out<int> p_config_fsm; 578 sc_out<int> p_alloc_heap_fsm; 579 sc_out<int> p_alloc_dir_fsm; 580 sc_out<int> p_alloc_trt_fsm; 581 sc_out<int> p_alloc_upt_fsm; 582 sc_out<int> p_alloc_ivt_fsm; 583 sc_out<int> p_tgt_cmd_fsm; 584 sc_out<int> p_tgt_rsp_fsm; 585 sc_out<int> p_ixr_cmd_fsm; 586 sc_out<int> p_ixr_rsp_fsm; 587 sc_out<int> p_cc_send_fsm; 588 sc_out<int> p_cc_receive_fsm; 589 sc_out<int> p_multi_ack_fsm; 590 #endif 591 548 592 VciMemCache( 549 593 sc_module_name name, // Instance Name … … 553 597 const soclib::common::IntTab &tgtid_d, // global index INT network 554 598 const size_t cc_global_id, // global index CC network 599 const size_t x_width, // X width in platform 600 const size_t y_width, // Y width in platform 555 601 const size_t nways, // Number of ways per set 556 602 const size_t nsets, // Number of sets … … 566 612 ~VciMemCache(); 567 613 568 void clear_stats(); 569 void print_stats(); 614 void print_stats(bool activity_counters, bool stats); 570 615 void print_trace(); 571 616 void cache_monitor(addr_t addr); … … 578 623 void genMoore(); 579 624 void check_monitor(addr_t addr, data_t data, bool read); 625 uint32_t req_distance(uint32_t req_srcid); 626 bool is_local_req(uint32_t req_srcid); 580 627 581 628 // Component attributes … … 591 638 const size_t m_words; // Number of words in a line 592 639 const size_t m_cc_global_id; // global_index on cc network 640 const size_t m_xwidth; // number of x bits in platform 641 const size_t m_ywidth; // number of y bits in platform 593 642 size_t m_debug_start_cycle; 594 643 bool m_debug_ok; … … 665 714 666 715 sc_signal<int> r_tgt_cmd_fsm; 667 sc_signal<size_t> r_tgt_cmd_srcid; // srcid for response to config668 sc_signal<size_t> r_tgt_cmd_trdid; // trdid for response to config669 sc_signal<size_t> r_tgt_cmd_pktid; // pktid for response to config670 716 671 717 /////////////////////////////////////////////////////// … … 696 742 sc_signal<bool> r_config_to_ixr_cmd_req; // valid request 697 743 sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index 698 699 744 700 745 // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) … … 776 821 sc_signal<size_t> r_write_upt_index; // index in Update Table 777 822 sc_signal<bool> r_write_sc_fail; // sc command failed 778 sc_signal<bool> r_write_pending_sc; // sc command pending 823 sc_signal<data_t> r_write_sc_key; // sc command key 824 sc_signal<bool> r_write_bc_data_we; // Write enable for data buffer 779 825 780 826 // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) … … 787 833 // Buffer between WRITE fsm and IXR_CMD fsm 788 834 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 789 sc_signal<bool> r_write_to_ixr_cmd_put; // request type (GET/PUT)790 835 sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index 791 836 … … 891 936 // Buffer between CAS fsm and IXR_CMD fsm 892 937 sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request 893 sc_signal<bool> r_cas_to_ixr_cmd_put; // request type (GET/PUT)894 938 sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index 895 939
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