Changeset 550 for trunk/platforms/tsar_generic_iob/top.cpp
- Timestamp:
- Oct 17, 2013, 8:55:19 PM (11 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_iob/top.cpp
r533 r550 240 240 241 241 #define BDEV_BASE 0x00B3000000 242 #define BDEV_SIZE 0x000000 1000 // 4 Kbytes242 #define BDEV_SIZE 0x0000008000 // 4 Kbytes 243 243 244 244 #define MTTY_BASE 0x00B4000000 … … 291 291 //////////////////////////////////////////////////////////////////////// 292 292 293 #define PROC_LOCAL_SRCID 0 // from 0 to 7294 #define MDMA_LOCAL_SRCID 8295 #define IOBX_LOCAL_SRCID 9296 #define BDEV_LOCAL_SRCID 10297 #define CDMA_LOCAL_SRCID 11298 #define MEMC_LOCAL_SRCID 12299 300 //////////////////////////////////////////////////////////////////// 293 #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 294 #define MDMA_LOCAL_SRCID 0x8 295 #define IOBX_LOCAL_SRCID 0x9 296 #define MEMC_LOCAL_SRCID 0xA 297 #define CDMA_LOCAL_SRCID 0xE // hard-coded in dspin_tsar 298 #define BDEV_LOCAL_SRCID 0xF // hard-coded in dspin_tsar 299 300 /////////////////////////////////////////////////////////////////////// 301 301 // TGT_ID and INI_ID port indexing for INT local interconnect 302 //////////////////////////////////////////////////////////////////// 302 /////////////////////////////////////////////////////////////////////// 303 303 304 304 #define INT_MEMC_TGT_ID 0 … … 311 311 #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) 312 312 313 //////////////////////////////////////////////////////////////////// 313 /////////////////////////////////////////////////////////////////////// 314 314 // TGT_ID and INI_ID port indexing for RAM local interconnect 315 //////////////////////////////////////////////////////////////////// 315 /////////////////////////////////////////////////////////////////////// 316 316 317 317 #define RAM_XRAM_TGT_ID 0 … … 320 320 #define RAM_IOBX_INI_ID 1 321 321 322 //////////////////////////////////////////////////////////////////// 322 /////////////////////////////////////////////////////////////////////// 323 323 // TGT_ID and INI_ID port indexing for I0X local interconnect 324 //////////////////////////////////////////////////////////////////// 324 /////////////////////////////////////////////////////////////////////// 325 325 326 326 #define IOX_IOB0_TGT_ID 0 // don't change this value … … 338 338 #define IOX_CDMA_INI_ID 3 339 339 340 ///////////////////////////////////////////////////////////////////// 340 //////////////////////////////////////////////////////////////////////// 341 341 int _main(int argc, char *argv[]) 342 ///////////////////////////////////////////////////////////////////// 342 //////////////////////////////////////////////////////////////////////// 343 343 { 344 344 using namespace sc_core; … … 533 533 uint64_t offset = ((uint64_t)cluster(x,y)) 534 534 << (vci_address_width-x_width-y_width); 535 bool config = true; 535 bool config = true; 536 bool cacheable = true; 536 537 537 538 // the four following segments are defined in all clusters … … 540 541 smemc_conf << "int_seg_memc_conf_" << x << "_" << y; 541 542 maptab_int.add(Segment(smemc_conf.str(), MEMC_BASE+offset, MEMC_SIZE, 542 IntTab(cluster(x,y),INT_MEMC_TGT_ID), true, config ));543 IntTab(cluster(x,y),INT_MEMC_TGT_ID), cacheable, config )); 543 544 544 545 std::ostringstream smemc_xram; 545 546 smemc_xram << "int_seg_memc_xram_" << x << "_" << y; 546 547 maptab_int.add(Segment(smemc_xram.str(), XRAM_BASE+offset, XRAM_SIZE, 547 IntTab(cluster(x,y),INT_MEMC_TGT_ID), true));548 IntTab(cluster(x,y),INT_MEMC_TGT_ID), cacheable)); 548 549 549 550 std::ostringstream sxicu; 550 551 sxicu << "int_seg_xicu_" << x << "_" << y; 551 552 maptab_int.add(Segment(sxicu.str(), XICU_BASE+offset, XICU_SIZE, 552 IntTab(cluster(x,y),INT_XICU_TGT_ID), false));553 IntTab(cluster(x,y),INT_XICU_TGT_ID), not cacheable)); 553 554 554 555 std::ostringstream smdma; 555 556 smdma << "int_seg_mdma_" << x << "_" << y; 556 557 maptab_int.add(Segment(smdma.str(), MDMA_BASE+offset, MDMA_SIZE, 557 IntTab(cluster(x,y),INT_MDMA_TGT_ID), false));558 IntTab(cluster(x,y),INT_MDMA_TGT_ID), not cacheable)); 558 559 559 560 // the following segments are only defined in cluster_iob0 or in cluster_iob1 … … 564 565 siobx << "int_seg_iobx_" << x << "_" << y; 565 566 maptab_int.add(Segment(siobx.str(), IOBX_BASE+offset, IOBX_SIZE, 566 IntTab(cluster(x,y), INT_IOBX_TGT_ID), false, config ));567 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable, config )); 567 568 568 569 std::ostringstream stty; 569 570 stty << "int_seg_mtty_" << x << "_" << y; 570 571 maptab_int.add(Segment(stty.str(), MTTY_BASE+offset, MTTY_SIZE, 571 IntTab(cluster(x,y), INT_IOBX_TGT_ID), false));572 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 572 573 573 574 std::ostringstream sfbf; 574 575 sfbf << "int_seg_fbuf_" << x << "_" << y; 575 576 maptab_int.add(Segment(sfbf.str(), FBUF_BASE+offset, FBUF_SIZE, 576 IntTab(cluster(x,y), INT_IOBX_TGT_ID), false));577 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 577 578 578 579 std::ostringstream sbdv; 579 580 sbdv << "int_seg_bdev_" << x << "_" << y; 580 581 maptab_int.add(Segment(sbdv.str(), BDEV_BASE+offset, BDEV_SIZE, 581 IntTab(cluster(x,y), INT_IOBX_TGT_ID), false));582 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 582 583 583 584 std::ostringstream snic; 584 585 snic << "int_seg_mnic_" << x << "_" << y; 585 586 maptab_int.add(Segment(snic.str(), MNIC_BASE+offset, MNIC_SIZE, 586 IntTab(cluster(x,y), INT_IOBX_TGT_ID), false));587 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 587 588 588 589 std::ostringstream srom; 589 590 srom << "int_seg_brom_" << x << "_" << y; 590 591 maptab_int.add(Segment(srom.str(), BROM_BASE+offset, BROM_SIZE, 591 IntTab(cluster(x,y), INT_IOBX_TGT_ID), true));592 IntTab(cluster(x,y), INT_IOBX_TGT_ID), cacheable )); 592 593 593 594 std::ostringstream sdma; 594 595 sdma << "int_seg_cdma_" << x << "_" << y; 595 596 maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE, 596 IntTab(cluster(x,y), INT_IOBX_TGT_ID), false));597 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 597 598 } 598 599 … … 600 601 // and the port index on the local interconnect. 601 602 602 maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), INT_MDMA_INI_ID ); 603 604 maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), INT_IOBX_INI_ID ); 603 maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), 604 IntTab( cluster(x,y), INT_MDMA_INI_ID ) ); 605 606 maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), 607 IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); 605 608 606 609 for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) 607 maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), INT_PROC_INI_ID+p ); 610 maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), 611 IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); 608 612 } 609 613 } … … 637 641 } 638 642 639 // This define the mapping between the initiators (identified by their640 // global SRCID)and the port index on the RAM local interconnect.643 // This define the mapping between the initiators SRCID 644 // and the port index on the RAM local interconnect. 641 645 // External initiator have two alias SRCID (iob0 / iob1) 642 646 643 maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), RAM_IOBX_INI_ID ); 644 maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), RAM_IOBX_INI_ID ); 645 646 maptab_ram.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), RAM_IOBX_INI_ID ); 647 maptab_ram.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), RAM_IOBX_INI_ID ); 648 649 maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), RAM_MEMC_INI_ID ); 647 maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), 648 IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); 649 650 maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), 651 IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); 652 653 maptab_ram.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), 654 IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); 655 656 maptab_ram.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), 657 IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); 658 659 maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), 660 IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); 650 661 651 662 std::cout << "RAM network " << maptab_ram << std::endl; … … 735 746 // External initiator have two alias SRCID (iob0 / iob1 access) 736 747 737 maptab_iox.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), IOX_CDMA_INI_ID ); 738 maptab_iox.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), IOX_CDMA_INI_ID ); 739 740 maptab_iox.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), IOX_BDEV_INI_ID ); 741 maptab_iox.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), IOX_BDEV_INI_ID ); 748 maptab_iox.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), 749 IntTab( cluster_iob0, IOX_CDMA_INI_ID ) ); 750 751 maptab_iox.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), 752 IntTab( cluster_iob1, IOX_CDMA_INI_ID ) ); 753 754 maptab_iox.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), 755 IntTab( cluster_iob0, IOX_BDEV_INI_ID ) ); 756 757 maptab_iox.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), 758 IntTab( cluster_iob0, IOX_BDEV_INI_ID ) ); 742 759 743 760 for (size_t x = 0; x < XMAX; x++) … … 745 762 for (size_t y = 0; y < YMAX ; y++) 746 763 { 747 if ( x < (XMAX/2) ) // send response to proc or mdma through IOB0 748 { 749 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID ), IOX_IOB0_INI_ID ); 750 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+1 ), IOX_IOB0_INI_ID ); 751 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+2 ), IOX_IOB0_INI_ID ); 752 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+3 ), IOX_IOB0_INI_ID ); 753 maptab_iox.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), IOX_IOB0_INI_ID ); 754 } 755 else // send response to proc or mdma through IOB1 756 { 757 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID ), IOX_IOB1_INI_ID ); 758 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+1 ), IOX_IOB1_INI_ID ); 759 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+2 ), IOX_IOB1_INI_ID ); 760 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+3 ), IOX_IOB1_INI_ID ); 761 maptab_iox.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), IOX_IOB1_INI_ID ); 762 } 764 size_t iob = ( x < (XMAX/2) ) ? IOX_IOB0_INI_ID : IOX_IOB1_INI_ID; 765 766 for (size_t p = 0 ; p < NB_PROCS_MAX ; p++) 767 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID + p ), 768 IntTab( cluster(x,y), iob ) ); 769 770 maptab_iox.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), 771 IntTab( cluster(x,y), IOX_IOB0_INI_ID ) ); 763 772 } 764 773 } … … 770 779 /////////////////// 771 780 772 sc_clock signal_clk("clk"); 773 sc_signal<bool> signal_resetn("resetn"); 774 775 sc_signal<bool> signal_unused_irq[32]; 776 sc_signal<bool> signal_irq_bdev; 777 sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; 778 sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; 779 sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS]; 780 sc_signal<bool> signal_irq_cdma[NB_NIC_CHANNELS*2]; 781 sc_clock signal_clk("clk"); 782 sc_signal<bool> signal_resetn("resetn"); 783 784 sc_signal<bool> signal_unused_irq[32]; 785 sc_signal<bool> signal_irq_bdev; 786 sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; 787 sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; 788 sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS]; 789 sc_signal<bool> signal_irq_cdma[NB_NIC_CHANNELS*2]; 790 791 // DSPIN signals for loopback in cluster_iob0 & cluster_iob1 792 DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob0_loopback; 793 DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob0_loopback; 794 DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob1_loopback; 795 DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob1_loopback; 781 796 782 797 // VCI signals for IOX network 783 VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0");784 VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1");785 VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev");786 VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma");787 788 VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0");789 VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1");790 VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty");791 VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");792 VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic");793 VciSignals<vci_param_ext> signal_vci_tgt_brom("signal_vci_tgt_brom");794 VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev");795 VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma");798 VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); 799 VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); 800 VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev"); 801 VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); 802 803 VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); 804 VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); 805 VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); 806 VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); 807 VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); 808 VciSignals<vci_param_ext> signal_vci_tgt_brom("signal_vci_tgt_brom"); 809 VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); 810 VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); 796 811 797 812 // Horizontal inter-clusters INT network DSPIN … … 881 896 iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", 882 897 maptab_iox, 883 0, // cluster_id884 898 8, // number of targets 885 899 4 ); // number of initiators 886 900 // boot ROM 887 VciSimpleRom<vci_param_ext>* iox_brom;888 iox_brom = new VciSimpleRom<vci_param_ext>( "iox_brom",889 890 891 901 VciSimpleRom<vci_param_ext>* brom; 902 brom = new VciSimpleRom<vci_param_ext>( "brom", 903 IntTab(0, IOX_BROM_TGT_ID), 904 maptab_iox, 905 loader ); 892 906 // Network Controller 893 VciMultiNic<vci_param_ext>* iox_mnic;894 iox_mnic = new VciMultiNic<vci_param_ext>( "iox_mnic",895 896 897 898 899 900 901 907 VciMultiNic<vci_param_ext>* mnic; 908 mnic = new VciMultiNic<vci_param_ext>( "mnic", 909 IntTab(0, IOX_MNIC_TGT_ID), 910 maptab_iox, 911 NB_NIC_CHANNELS, 912 nic_rx_name, 913 nic_tx_name, 914 0, // mac_4 address 915 0 ); // mac_2 address 902 916 903 917 // Frame Buffer 904 VciFrameBuffer<vci_param_ext>* iox_fbuf;905 iox_fbuf = new VciFrameBuffer<vci_param_ext>( "iox_fbuf",906 907 908 918 VciFrameBuffer<vci_param_ext>* fbuf; 919 fbuf = new VciFrameBuffer<vci_param_ext>( "fbuf", 920 IntTab(0, IOX_FBUF_TGT_ID), 921 maptab_iox, 922 FBUF_X_SIZE, FBUF_Y_SIZE ); 909 923 910 924 // Block Device 911 VciBlockDeviceTsar<vci_param_ext>* iox_bdev; 912 iox_bdev = new VciBlockDeviceTsar<vci_param_ext>( "iox_bdev", 913 maptab_iox, 914 IntTab(0, BDEV_LOCAL_SRCID), 915 IntTab(0, IOX_BDEV_TGT_ID), 916 disk_name, 917 block_size, 918 64); // burst size (bytes) 925 // for AHCI 926 // std::vector<std::string> filenames; 927 // filenames.push_back(disk_name); // one single disk 928 VciBlockDeviceTsar<vci_param_ext>* bdev; 929 bdev = new VciBlockDeviceTsar<vci_param_ext>( "bdev", 930 maptab_iox, 931 IntTab(0, BDEV_LOCAL_SRCID), 932 IntTab(0, IOX_BDEV_TGT_ID), 933 disk_name, 934 block_size, 935 64, // burst size (bytes) 936 0 ); // disk latency 919 937 920 938 // Chained Buffer DMA controller 921 VciChbufDma<vci_param_ext>* iox_cdma;922 iox_cdma = new VciChbufDma<vci_param_ext>( "iox_cdma",923 924 925 926 927 939 VciChbufDma<vci_param_ext>* cdma; 940 cdma = new VciChbufDma<vci_param_ext>( "cdma", 941 maptab_iox, 942 IntTab(0, CDMA_LOCAL_SRCID), 943 IntTab(0, IOX_CDMA_TGT_ID), 944 64, // burst size (bytes) 945 2*NB_NIC_CHANNELS ); 928 946 // Multi-TTY controller 929 947 std::vector<std::string> vect_names; … … 934 952 vect_names.push_back(term_name.str().c_str()); 935 953 } 936 VciMultiTty<vci_param_ext>* iox_mtty;937 iox_mtty = new VciMultiTty<vci_param_ext>( "iox_mtty",938 939 940 954 VciMultiTty<vci_param_ext>* mtty; 955 mtty = new VciMultiTty<vci_param_ext>( "mtty", 956 IntTab(0, IOX_MTTY_TGT_ID), 957 maptab_iox, 958 vect_names); 941 959 // Clusters 942 960 TsarIobCluster<vci_param_int, … … 1002 1020 1003 1021 RAM_MEMC_INI_ID, 1004 RAM_ MEMC_INI_ID,1022 RAM_IOBX_INI_ID, 1005 1023 1006 1024 MEMC_WAYS, … … 1052 1070 1053 1071 // BDEV connexion 1054 iox_bdev->p_clk (signal_clk); 1055 iox_bdev->p_resetn (signal_resetn); 1056 iox_bdev->p_irq (signal_irq_bdev); 1057 iox_bdev->p_vci_target (signal_vci_tgt_bdev); 1058 iox_bdev->p_vci_initiator (signal_vci_ini_bdev); 1072 bdev->p_clk (signal_clk); 1073 bdev->p_resetn (signal_resetn); 1074 bdev->p_irq (signal_irq_bdev); 1075 // For AHCI 1076 // bdev->p_channel_irq[0] (signal_irq_bdev); 1077 bdev->p_vci_target (signal_vci_tgt_bdev); 1078 bdev->p_vci_initiator (signal_vci_ini_bdev); 1059 1079 1060 1080 std::cout << " - BDEV connected" << std::endl; 1061 1081 1062 1082 // FBUF connexion 1063 iox_fbuf->p_clk (signal_clk);1064 iox_fbuf->p_resetn (signal_resetn);1065 iox_fbuf->p_vci (signal_vci_tgt_fbuf);1083 fbuf->p_clk (signal_clk); 1084 fbuf->p_resetn (signal_resetn); 1085 fbuf->p_vci (signal_vci_tgt_fbuf); 1066 1086 1067 1087 std::cout << " - FBUF connected" << std::endl; 1068 1088 1069 1089 // MNIC connexion 1070 iox_mnic->p_clk (signal_clk);1071 iox_mnic->p_resetn (signal_resetn);1072 iox_mnic->p_vci (signal_vci_tgt_mnic);1090 mnic->p_clk (signal_clk); 1091 mnic->p_resetn (signal_resetn); 1092 mnic->p_vci (signal_vci_tgt_mnic); 1073 1093 for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) 1074 1094 { 1075 iox_mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);1076 iox_mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);1095 mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); 1096 mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); 1077 1097 } 1078 1098 … … 1080 1100 1081 1101 // BROM connexion 1082 iox_brom->p_clk (signal_clk);1083 iox_brom->p_resetn (signal_resetn);1084 iox_brom->p_vci (signal_vci_tgt_brom);1102 brom->p_clk (signal_clk); 1103 brom->p_resetn (signal_resetn); 1104 brom->p_vci (signal_vci_tgt_brom); 1085 1105 1086 1106 std::cout << " - BROM connected" << std::endl; 1087 1107 1088 1108 // MTTY connexion 1089 iox_mtty->p_clk (signal_clk);1090 iox_mtty->p_resetn (signal_resetn);1091 iox_mtty->p_vci (signal_vci_tgt_mtty);1109 mtty->p_clk (signal_clk); 1110 mtty->p_resetn (signal_resetn); 1111 mtty->p_vci (signal_vci_tgt_mtty); 1092 1112 for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) 1093 1113 { 1094 iox_mtty->p_irq[i] (signal_irq_mtty[i]);1114 mtty->p_irq[i] (signal_irq_mtty[i]); 1095 1115 } 1096 1116 … … 1098 1118 1099 1119 // CDMA connexion 1100 iox_cdma->p_clk (signal_clk);1101 iox_cdma->p_resetn (signal_resetn);1102 iox_cdma->p_vci_target (signal_vci_tgt_cdma);1103 iox_cdma->p_vci_initiator (signal_vci_ini_cdma);1120 cdma->p_clk (signal_clk); 1121 cdma->p_resetn (signal_resetn); 1122 cdma->p_vci_target (signal_vci_tgt_cdma); 1123 cdma->p_vci_initiator (signal_vci_ini_cdma); 1104 1124 for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) 1105 1125 { 1106 iox_cdma->p_irq[i] (signal_irq_cdma[i]);1126 cdma->p_irq[i] (signal_irq_cdma[i]); 1107 1127 } 1108 1128 … … 1129 1149 1130 1150 // IOB0 cluster connexion to IOX network 1131 (*clusters[0][0]->p_vci_io x_ini)(signal_vci_ini_iob0);1132 (*clusters[0][0]->p_vci_io x_tgt)(signal_vci_tgt_iob0);1151 (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); 1152 (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); 1133 1153 1134 1154 // IOB1 cluster connexion to IOX network 1135 (*clusters[XMAX-1][YMAX-1]->p_vci_io x_ini)(signal_vci_ini_iob1);1136 (*clusters[XMAX-1][YMAX-1]->p_vci_io x_tgt)(signal_vci_tgt_iob1);1155 (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); 1156 (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); 1137 1157 1138 1158 // All clusters Clock & RESET connexions … … 1239 1259 } 1240 1260 1241 clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); 1242 clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); 1243 clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); 1244 clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); 1245 1246 clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); 1247 clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); 1248 clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); 1249 clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); 1261 if( y == 0 ) // handling IOB to RAM network connection in cluster_iob0 1262 { 1263 (*clusters[0][0]->p_dspin_iob_cmd_out) (signal_dspin_cmd_iob0_loopback); 1264 clusters[0][0]->p_dspin_ram_cmd_in[WEST] (signal_dspin_cmd_iob0_loopback); 1265 1266 clusters[0][0]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][0][WEST]); 1267 clusters[0][0]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][0][WEST]); 1268 1269 clusters[0][0]->p_dspin_ram_rsp_out[WEST] (signal_dspin_rsp_iob0_loopback); 1270 (*clusters[0][0]->p_dspin_iob_rsp_in) (signal_dspin_rsp_iob0_loopback); 1271 1272 } 1273 else 1274 { 1275 clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); 1276 clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); 1277 clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); 1278 clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); 1279 } 1280 1281 if( y == YMAX-1 ) // handling IOB to RAM network connection in cluster_iob1 1282 { 1283 (*clusters[XMAX-1][YMAX-1]->p_dspin_iob_cmd_out) (signal_dspin_cmd_iob1_loopback); 1284 clusters[XMAX-1][YMAX-1]->p_dspin_ram_cmd_in[EAST] (signal_dspin_cmd_iob1_loopback); 1285 1286 clusters[XMAX-1][YMAX-1]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][YMAX-1][EAST]); 1287 clusters[XMAX-1][YMAX-1]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][YMAX-1][EAST]); 1288 1289 clusters[XMAX-1][YMAX-1]->p_dspin_ram_rsp_out[EAST] (signal_dspin_rsp_iob1_loopback); 1290 (*clusters[XMAX-1][YMAX-1]->p_dspin_iob_rsp_in) (signal_dspin_rsp_iob1_loopback); 1291 } 1292 else 1293 { 1294 clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); 1295 clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); 1296 clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); 1297 clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); 1298 } 1250 1299 } 1251 1300 … … 1282 1331 } 1283 1332 1284 std::cout << "North & South boundaries established" << std::endl ;1333 std::cout << "North & South boundaries established" << std::endl << std::endl; 1285 1334 1286 1335 //////////////////////////////////////////////////////// … … 1327 1376 } 1328 1377 1329 sc_start(sc_core::sc_time(1, SC_NS)); 1330 signal_resetn = true; 1331 1332 for (size_t n = 1; n < ncycles; n++) 1333 { 1334 // Monitor a specific address for L1 & L2 caches 1335 // clusters[1][1]->proc[0]->cache_monitor(0x8ba4ULL); 1336 // clusters[0][0]->memc->cache_monitor( 0x12180ULL); 1337 1338 if (debug_ok and (n > debug_from) and (n % debug_period == 0)) 1339 { 1340 std::cout << "****************** cycle " << std::dec << n ; 1341 std::cout << " ************************************************" << std::endl; 1342 1343 // trace proc[debug_proc_id] 1344 if ( debug_proc_id < XMAX*YMAX*NB_PROCS_MAX ) 1378 sc_start(sc_core::sc_time(1, SC_NS)); 1379 signal_resetn = true; 1380 1381 for (size_t n = 1; n < ncycles; n++) 1382 { 1383 // Monitor a specific address for L1 & L2 caches 1384 // clusters[1][1]->proc[0]->cache_monitor(0x8ba4ULL); 1385 // clusters[0][0]->memc->cache_monitor( 0x12180ULL); 1386 1387 if (debug_ok and (n > debug_from) and (n % debug_period == 0)) 1345 1388 { 1346 1347 size_t l = debug_proc_id % NB_PROCS_MAX ; 1348 size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ; 1349 size_t x = debug_proc_id / (YMAX * NB_PROCS_MAX) ; 1350 1351 clusters[x][y]->proc[l]->print_trace(1); 1352 1353 std::ostringstream proc_signame; 1354 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 1355 clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); 1356 1357 std::ostringstream p2m_signame; 1358 p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; 1359 clusters[x][y]->signal_int_dspin_p2m_proc[l].print_trace(p2m_signame.str()); 1360 1361 std::ostringstream m2p_signame; 1362 m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; 1363 clusters[x][y]->signal_int_dspin_m2p_proc[l].print_trace(m2p_signame.str()); 1364 1365 // std::ostringstream p_cmd_signame; 1366 // p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ; 1367 // clusters[x][y]->signal_int_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str()); 1368 1369 // std::ostringstream p_rsp_signame; 1370 // p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ; 1371 // clusters[x][y]->signal_int_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str()); 1372 1373 // trace INT routers and xbar in a given cluster 1374 // clusters[x][y]->int_xbar_m2p_c->print_trace(); 1375 // clusters[x][y]->int_router_cmd->print_trace(1); 1376 // clusters[x][y]->int_xbar_rsp_d->print_trace(); 1377 // clusters[x][y]->int_xbar_cmd_d->print_trace(); 1378 // clusters[x][y]->signal_int_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); 1379 // clusters[x][y]->signal_int_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); 1380 // clusters[x][y]->signal_int_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); 1381 // clusters[x][y]->signal_int_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); 1389 std::cout << "****************** cycle " << std::dec << n ; 1390 std::cout << " ************************************************" << std::endl; 1391 1392 // trace proc[debug_proc_id] 1393 if ( debug_proc_id < XMAX*YMAX*NB_PROCS_MAX ) 1394 { 1395 1396 size_t l = debug_proc_id % NB_PROCS_MAX ; 1397 size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ; 1398 size_t x = debug_proc_id / (YMAX * NB_PROCS_MAX) ; 1399 1400 clusters[x][y]->proc[l]->print_trace(0); 1401 1402 std::ostringstream proc_signame; 1403 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 1404 clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); 1405 1406 // std::ostringstream p2m_signame; 1407 // p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; 1408 // clusters[x][y]->signal_int_dspin_p2m_proc[l].print_trace(p2m_signame.str()); 1409 1410 // std::ostringstream m2p_signame; 1411 // m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; 1412 // clusters[x][y]->signal_int_dspin_m2p_proc[l].print_trace(m2p_signame.str()); 1413 1414 // std::ostringstream p_cmd_signame; 1415 // p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ; 1416 // clusters[x][y]->signal_int_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str()); 1417 1418 // std::ostringstream p_rsp_signame; 1419 // p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ; 1420 // clusters[x][y]->signal_int_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str()); 1421 } 1422 1423 // trace INT_CMD_D xbar and router in 1_0 1424 // clusters[1][0]->int_xbar_cmd_d->print_trace(); 1425 // clusters[1][0]->int_xbar_rsp_d->print_trace(); 1426 1427 // clusters[1][0]->signal_int_dspin_cmd_l2g_d.print_trace("[SIG] INT_CMD_L2G_D_1_0"); 1428 // clusters[1][0]->signal_int_dspin_rsp_g2l_d.print_trace("[SIG] INT_RSP_G2L_D_1_0"); 1429 1430 // clusters[1][0]->int_router_cmd->print_trace(0); 1431 // clusters[1][0]->int_router_rsp->print_trace(0); 1432 1433 // trace INT_CMD_D xbar and router in 0_0 1434 // clusters[0][0]->int_xbar_cmd_d->print_trace(); 1435 // clusters[0][0]->int_xbar_rsp_d->print_trace(); 1436 1437 // clusters[0][0]->signal_int_dspin_cmd_g2l_d.print_trace("[SIG] INT_CMD_G2L_D_0_0"); 1438 // clusters[0][0]->signal_int_dspin_rsp_l2g_d.print_trace("[SIG] INT_RSP_L2G_D_0_0"); 1439 1440 // clusters[0][0]->int_router_cmd->print_trace(0); 1441 // clusters[0][0]->int_router_rsp->print_trace(0); 1442 1443 // trace memc[debug_memc_id] and xram[debug_memc_id] 1444 if ( debug_memc_id < XMAX*YMAX ) 1445 { 1446 size_t x = debug_memc_id / YMAX; 1447 size_t y = debug_memc_id % YMAX; 1448 clusters[x][y]->memc->print_trace(0); 1449 std::ostringstream smemc_tgt; 1450 smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; 1451 clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); 1452 std::ostringstream smemc_ini; 1453 smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; 1454 clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); 1455 clusters[x][y]->xram->print_trace(); 1456 std::ostringstream sxram_tgt; 1457 sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; 1458 clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); 1459 } 1460 1461 // trace RAM network 1462 for( size_t cluster = 0 ; cluster < XMAX*YMAX ; cluster++ ) 1463 { 1464 size_t x = cluster / YMAX; 1465 size_t y = cluster % YMAX; 1466 clusters[x][y]->ram_router_cmd->print_trace(); 1467 clusters[x][y]->ram_router_rsp->print_trace(); 1468 } 1469 1470 // trace iob, iox and external peripherals 1471 if ( debug_iob ) 1472 { 1473 clusters[0][0]->iob->print_trace(); 1474 clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); 1475 clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); 1476 clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); 1477 1478 signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); 1479 signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); 1480 1481 signal_dspin_cmd_iob0_loopback.print_trace("[SIG]IOB0_CMD_LOOPBACK"); 1482 signal_dspin_rsp_iob0_loopback.print_trace("[SIG]IOB0_RSP_LOOPBACK"); 1483 1484 // cdma->print_trace(); 1485 // signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT"); 1486 // signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI"); 1487 1488 // brom->print_trace(); 1489 // signal_vci_tgt_brom.print_trace("[SIG]IOX_BROM_TGT"); 1490 1491 // mtty->print_trace(); 1492 // signal_vci_tgt_mtty.print_trace("[SIG]IOX_MTTY_TGT"); 1493 1494 bdev->print_trace(); 1495 signal_vci_tgt_bdev.print_trace("[SIG]IOX_BDEV_TGT"); 1496 signal_vci_ini_bdev.print_trace("[SIG]IOX_BDEV_INI"); 1497 1498 // fbuf->print_trace(); 1499 // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); 1500 1501 iox_network->print_trace(); 1502 1503 // interrupts 1504 if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED" << std::endl; 1505 } 1382 1506 } 1383 1507 1384 // trace memc[debug_memc_id] 1385 if ( debug_memc_id < XMAX*YMAX ) 1386 { 1387 1388 size_t x = debug_memc_id / YMAX; 1389 size_t y = debug_memc_id % YMAX; 1390 1391 clusters[x][y]->memc->print_trace(); 1392 1393 std::ostringstream smemc_tgt; 1394 smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; 1395 clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); 1396 1397 std::ostringstream smemc_ini; 1398 smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; 1399 clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); 1400 1401 // clusters[x][y]->ram_router_cmd->print_trace(); 1402 // clusters[x][y]->ram_xbar_cmd->print_trace(); 1403 1404 // std::ostringstream sg2l; 1405 // sg2l << "[SIG]G2L_" << x << "_" << y; 1406 // clusters[x][y]->signal_ram_dspin_cmd_g2l.print_trace(sg2l.str()); 1407 1408 clusters[x][y]->xram->print_trace(); 1409 1410 std::ostringstream sxram_tgt; 1411 sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; 1412 clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); 1413 1414 std::ostringstream sm2p; 1415 sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; 1416 clusters[x][y]->signal_int_dspin_m2p_memc.print_trace(sm2p.str()); 1417 1418 std::ostringstream sp2m; 1419 sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; 1420 clusters[x][y]->signal_int_dspin_p2m_memc.print_trace(sp2m.str()); 1421 1422 // std::ostringstream m_cmd_signame; 1423 // m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ; 1424 // clusters[x][y]->signal_int_dspin_cmd_memc_t.print_trace(m_cmd_signame.str()); 1425 1426 // std::ostringstream m_rsp_signame; 1427 // m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ; 1428 // clusters[x][y]->signal_int_dspin_rsp_memc_t.print_trace(m_rsp_signame.str()); 1429 1430 std::ostringstream siob_ini; 1431 siob_ini << "[SIG]IOB_INI_" << x << "_" << y; 1432 clusters[x][y]->signal_ram_vci_ini_iobx.print_trace(siob_ini.str()); 1433 } 1434 1435 // trace components iob 1436 if ( debug_iob ) 1437 { 1438 clusters[0][0]->iob->print_trace(); 1439 clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0 INT TGT" ); 1440 // clusters[0][0]->signal_int_dspin_cmd_iobx_t.print_trace("[SIG]IOB0 INT CMD"); 1441 // clusters[0][0]->signal_int_dspin_rsp_iobx_t.print_trace("[SIG]IOB0 INT RSP"); 1442 1443 clusters[XMAX-1][YMAX-1]->iob->print_trace(); 1444 clusters[XMAX-1][YMAX-1]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB1 INT TGT" ); 1445 // clusters[XMAX-1][YMAX-1]->signal_int_dspin_cmd_iobx_t.print_trace("[SIG]IOB1 INT CMD"); 1446 // clusters[XMAX-1][YMAX-1]->signal_int_dspin_rsp_iobx_t.print_trace("[SIG]IOB1 INT RSP"); 1447 } 1448 1449 // trace external peripherals 1450 iox_network->print_trace(); 1451 1452 signal_vci_ini_iob0.print_trace("[SIG]IOB0 IOX INI"); 1453 signal_vci_tgt_iob0.print_trace("[SIG]IOB0 IOX TGT"); 1454 signal_vci_ini_iob1.print_trace("[SIG]IOB1 IOX INI"); 1455 signal_vci_tgt_iob1.print_trace("[SIG]IOB1 IOX TGT"); 1456 1457 iox_cdma->print_trace(); 1458 signal_vci_tgt_cdma.print_trace("[SIG]CDMA_TGT"); 1459 signal_vci_ini_cdma.print_trace("[SIG]CDMA_INI"); 1460 1461 // iox_brom->print_trace(); 1462 // signal_vci_tgt_brom.print_trace("[SIG]BROM"); 1463 1464 iox_mtty->print_trace(); 1465 signal_vci_tgt_mtty.print_trace("[SIG]MTTY"); 1466 1467 iox_bdev->print_trace(); 1468 signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); 1469 signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 1470 1471 // iox_fbuf->print_trace(); 1472 // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); 1473 1474 } 1475 1476 sc_start(sc_core::sc_time(1, SC_NS)); 1477 } 1478 return EXIT_SUCCESS; 1508 sc_start(sc_core::sc_time(1, SC_NS)); 1509 } 1510 return EXIT_SUCCESS; 1479 1511 } 1480 1512
Note: See TracChangeset
for help on using the changeset viewer.