Changeset 550 for trunk/platforms/tsar_generic_iob/tsar_iob_cluster
- Timestamp:
- Oct 17, 2013, 8:55:19 PM (11 years ago)
- Location:
- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd
r468 r550 83 83 dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), 84 84 85 Uses('caba:dspin_ local_crossbar',85 Uses('caba:dspin_router_tsar', 86 86 flit_width = parameter.Reference('dspin_ram_cmd_width')), 87 87 88 Uses('caba:dspin_local_crossbar', 89 flit_width = parameter.Reference('dspin_ram_rsp_width')), 90 91 Uses('caba:dspin_router', 92 flit_width = parameter.Reference('dspin_ram_cmd_width')), 93 94 Uses('caba:dspin_router', 88 Uses('caba:dspin_router_tsar', 95 89 flit_width = parameter.Reference('dspin_ram_rsp_width')), 96 90 -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r468 r550 25 25 #include "vci_dspin_initiator_wrapper.h" 26 26 #include "vci_dspin_target_wrapper.h" 27 #include "dspin_router .h"27 #include "dspin_router_tsar.h" 28 28 #include "virtual_dspin_router.h" 29 29 #include "vci_multi_dma.h" … … 52 52 sc_in<bool> p_resetn; 53 53 54 soclib::caba::VciInitiator<vci_param_ext>* p_vci_iox_ini; 55 soclib::caba::VciTarget<vci_param_ext>* p_vci_iox_tgt; 56 57 sc_in<bool>* p_irq[32]; // not always used 58 54 // Thes two ports are used to connect IOB to IOX nework in top cell 55 soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini; 56 soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; 57 58 // These ports are used to connect IOB to RAM network in top cell 59 soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out; 60 soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_iob_rsp_in; 61 62 // These ports are used to connect hard IRQ from external peripherals to IOB0 63 sc_in<bool>* p_irq[32]; 64 65 // These arrays of ports are used to connect the INT & RAM networks in top cell 59 66 soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out; 60 67 soclib::caba::DspinInput<dspin_int_cmd_width>** p_dspin_int_cmd_in; … … 124 131 VciSignals<vci_param_ext> signal_ram_vci_tgt_xram; 125 132 126 // RAM network DSPIN signals between VCI/DSPIN wrappers and crossbars orrouters133 // RAM network DSPIN signals between VCI/DSPIN wrappers and routers 127 134 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; 128 135 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; 129 136 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i; 130 137 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i; 131 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_iobx_i;132 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_iobx_i;133 138 134 // RAM network DSPIN signals between DSPIN routers and DSPIN local crossbars135 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_l2g;136 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_g2l;137 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_l2g;138 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_g2l;139 140 139 ////////////////////////////////////// 141 140 // Hardwate Components (pointers) … … 194 193 dspin_ram_rsp_width>* xram_ram_wt; 195 194 196 DspinRouter <dspin_ram_cmd_width>*ram_router_cmd;197 DspinRouter <dspin_ram_rsp_width>*ram_router_rsp;195 DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd; 196 DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp; 198 197 199 198 // IO Network Components (not instanciated in all clusters) … … 214 213 dspin_ram_rsp_width>* iob_ram_wi; 215 214 216 DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd;217 DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp;218 219 215 // cluster constructor 220 216 TsarIobCluster( sc_module_name insname, -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r533 r550 49 49 size_t l_width, 50 50 51 size_t memc_int_tgtid, 52 size_t xicu_int_tgtid, 53 size_t mdma_int_tgtid, 54 size_t iobx_int_tgtid, 55 56 size_t proc_int_srcid, 57 size_t mdma_int_srcid, 58 size_t iobx_int_srcid, 59 60 size_t xram_ram_tgtid, 61 62 size_t memc_ram_srcid, 63 size_t iobx_ram_srcid, 51 size_t memc_int_tgtid, // local index 52 size_t xicu_int_tgtid, // local index 53 size_t mdma_int_tgtid, // local index 54 size_t iobx_int_tgtid, // local index 55 56 size_t proc_int_srcid, // local index 57 size_t mdma_int_srcid, // local index 58 size_t iobx_int_srcid, // local index 59 60 size_t xram_ram_tgtid, // local index 61 62 size_t memc_ram_srcid, // local index 63 size_t iobx_ram_srcid, // local index 64 64 65 65 size_t memc_ways, … … 85 85 86 86 size_t cluster_id = x_id * ymax + y_id; 87 size_t cluster_iob0 = 0; 88 size_t cluster_iob1 = xmax*ymax-1; 87 88 size_t cluster_iob0 = 0; // South-West cluster 89 size_t cluster_iob1 = xmax*ymax-1; // North-East cluster 89 90 90 91 // Vectors of DSPIN ports for inter-cluster communications … … 99 100 p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); 100 101 101 // VCI ports to IOB0 and IOB1 in cluster_iob0 and cluster_iob1102 // ports in cluster_iob0 and cluster_iob1 only 102 103 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 103 104 { 104 p_vci_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; 105 p_vci_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 105 // VCI ports from IOB to IOX network 106 p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; 107 p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 108 109 // DSPIN ports from IOB to RAM network 110 p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>; 111 p_dspin_iob_rsp_in = new soclib::caba::DspinInput<dspin_ram_rsp_width>; 106 112 } 107 113 … … 166 172 IntTab(cluster_id, memc_int_tgtid), // TGTID INT network 167 173 (cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID 168 x_width, // Number of x bits in platform169 y_width, // Number of y bits in platform174 x_width, // number of bits for x coordinate 175 y_width, // number of bits for y coordinate 170 176 memc_ways, memc_sets, 16, // CACHE SIZE 171 177 3, // MAX NUMBER OF COPIES … … 334 340 int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( 335 341 s_int_router_rsp.str().c_str(), 336 x_id,y_id, // coordinates in mesh342 x_id,y_id, // router coordinates in mesh 337 343 x_width, y_width, // x & y fields width 338 344 2, // nb virtual channels … … 360 366 std::ostringstream s_ram_router_cmd; 361 367 s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; 362 ram_router_cmd = new DspinRouter <dspin_ram_cmd_width>(368 ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>( 363 369 s_ram_router_cmd.str().c_str(), 364 x_id,y_id, // coordinate in the mesh 365 x_width, y_width, // x & y fields width 366 4,4); // input & output fifo depths 370 x_id, y_id, // router coordinates in mesh 371 x_width, // x field width in first flit 372 x_width, // y field width in first flit 373 4, 4, // input & output fifo depths 374 cluster_iob0, // cluster containing IOB0 375 cluster_iob1, // cluster containing IOB1 376 l_width, // local field width in first flit 377 iobx_ram_srcid ); // IOB local index 367 378 368 379 std::ostringstream s_ram_router_rsp; 369 380 s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; 370 ram_router_rsp = new DspinRouter <dspin_ram_rsp_width>(381 ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>( 371 382 s_ram_router_rsp.str().c_str(), 372 x_id,y_id, // coordinates in mesh 373 x_width, y_width, // x & y fields width 374 4,4); // input & output fifo depths 383 x_id, y_id, // coordinates in mesh 384 x_width, // x field width in first flit 385 y_width, // y field width in first flit 386 4, 4, // input & output fifo depths 387 cluster_iob0, // cluster containing IOB0 388 cluster_iob1, // cluster containing IOB1 389 l_width, // local field width in first flit 390 iobx_ram_srcid ); // IOB local index 391 375 392 376 393 ////////////////////// I/O CLUSTER ONLY /////////////////////// … … 435 452 s_iob_ram_wi.str().c_str(), 436 453 x_width + y_width + l_width); 437 438 ///////////// RAM LOCAL_XBAR(S) 439 std::ostringstream s_ram_xbar_cmd; 440 s_ram_xbar_cmd << "ram_xbar_cmd_" << x_id << "_" << y_id; 441 ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>( 442 s_ram_xbar_cmd.str().c_str(), 443 mt_ram, // mapping table 444 x_id, y_id, // cluster coordinates 445 x_width, y_width, 0, // one dest on ram_cmd network 446 2, // number of local sources 447 1, // number of local dests 448 2, 2, // fifo depths 449 true, // CMD crossbar 450 false, // no routing table (one dest) 451 false ); // no broadcast 452 453 std::ostringstream s_ram_xbar_rsp; 454 s_ram_xbar_rsp << "ram_xbar_rsp_" << x_id << "_" << y_id; 455 ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>( 456 s_ram_xbar_rsp.str().c_str(), 457 mt_ram, // mapping table 458 x_id, y_id, // cluster coordinates 459 x_width, y_width, l_width, // two sources on ram_rsp network 460 1, // number of local sources 461 2, // number of local dests 462 2, 2, // fifo depths 463 false, // RSP crossbar 464 true, // use routing table 465 false ); // no broadcast 466 } 454 } // end if IO 467 455 468 456 //////////////////////////////////// … … 682 670 mdma_int_wi->p_vci (signal_int_vci_ini_mdma); 683 671 684 // For the IO bridge and the RAM network components, the connexions 685 // depend on cluster type: The vci_io_bridge and dspin_local_crossbar 686 // components are only in cluster_iob0 & cluster_iob1 687 688 if ( (cluster_id != cluster_iob0) and (cluster_id != cluster_iob1) ) 689 { 690 // RAM network CMD & RSP routers 691 ram_router_cmd->p_clk (this->p_clk); 692 ram_router_cmd->p_resetn (this->p_resetn); 693 ram_router_rsp->p_clk (this->p_clk); 694 ram_router_rsp->p_resetn (this->p_resetn); 695 for( size_t n=0 ; n<4 ; n++) 696 { 697 ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); 698 ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); 699 ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); 700 ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); 701 } 702 ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); 703 ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); 704 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); 705 ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); 706 } 707 else // IO cluster 672 //////////////////////////// RAM network CMD & RSP routers 673 ram_router_cmd->p_clk (this->p_clk); 674 ram_router_cmd->p_resetn (this->p_resetn); 675 ram_router_rsp->p_clk (this->p_clk); 676 ram_router_rsp->p_resetn (this->p_resetn); 677 for( size_t n=0 ; n<4 ; n++) 678 { 679 ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); 680 ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); 681 ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); 682 ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); 683 } 684 ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); 685 ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); 686 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); 687 ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); 688 689 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 690 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 708 691 { 709 692 // IO bridge 710 693 iob->p_clk (this->p_clk); 711 694 iob->p_resetn (this->p_resetn); 712 iob->p_vci_ini_iox (*(this->p_vci_io x_ini));713 iob->p_vci_tgt_iox (*(this->p_vci_io x_tgt));695 iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); 696 iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); 714 697 iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); 715 698 iob->p_vci_ini_int (signal_int_vci_ini_iobx); 716 699 iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); 700 717 701 if ( cluster_id == cluster_iob0 ) 718 for ( size_t n=0 ; n<32 ; n++ )719 (*iob->p_irq[n]) (*(this->p_irq[n]));702 for ( size_t n=0 ; n<32 ; n++ ) 703 (*iob->p_irq[n]) (*(this->p_irq[n])); 720 704 721 705 // initiator wrapper to RAM network 722 706 iob_ram_wi->p_clk (this->p_clk); 723 707 iob_ram_wi->p_resetn (this->p_resetn); 724 iob_ram_wi->p_dspin_cmd ( signal_ram_dspin_cmd_iobx_i);725 iob_ram_wi->p_dspin_rsp ( signal_ram_dspin_rsp_iobx_i);708 iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out)); 709 iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in)); 726 710 iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); 727 711 … … 739 723 iob_int_wt->p_dspin_rsp (signal_int_dspin_rsp_iobx_t); 740 724 iob_int_wt->p_vci (signal_int_vci_tgt_iobx); 741 742 // RAM network CMD local crossbar 743 ram_xbar_cmd->p_clk (this->p_clk); 744 ram_xbar_cmd->p_resetn (this->p_resetn); 745 ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_l2g); 746 ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_g2l); 747 ram_xbar_cmd->p_local_in[0] (signal_ram_dspin_cmd_memc_i); 748 ram_xbar_cmd->p_local_in[1] (signal_ram_dspin_cmd_iobx_i); 749 ram_xbar_cmd->p_local_out[0] (signal_ram_dspin_cmd_xram_t); 750 751 // RAM network RSP local crossbar 752 ram_xbar_rsp->p_clk (this->p_clk); 753 ram_xbar_rsp->p_resetn (this->p_resetn); 754 ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_l2g); 755 ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_g2l); 756 ram_xbar_rsp->p_local_in[0] (signal_ram_dspin_rsp_xram_t); 757 ram_xbar_rsp->p_local_out[0] (signal_ram_dspin_rsp_memc_i); 758 ram_xbar_rsp->p_local_out[1] (signal_ram_dspin_rsp_iobx_i); 759 760 // RAM network CMD & RSP routers 761 ram_router_cmd->p_clk (this->p_clk); 762 ram_router_cmd->p_resetn (this->p_resetn); 763 ram_router_rsp->p_clk (this->p_clk); 764 ram_router_rsp->p_resetn (this->p_resetn); 765 for( size_t n=0 ; n<4 ; n++) 766 { 767 ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); 768 ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); 769 ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); 770 ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); 771 } 772 ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_g2l); 773 ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_l2g); 774 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_g2l); 775 ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_l2g); 776 } 777 725 } 726 778 727 } // end constructor 779 728
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