Changeset 568 for trunk/softs/tsar_boot/conf

Timestamp:

Oct 30, 2013, 11:19:23 AM (11 years ago)

Author:

cfuguet

Message:

Adding support for TSAR platforms using the vci_io_bridge component.

In this case (USE_IOB=1), when a block is read from the disk controller,
the buffer containing the read data must be invalidated in the Memory
Cache as the transfer is done between the disk controller and the RAM.

Location:

trunk/softs/tsar_boot/conf

Files:

• platform_fpga_de2-115/defs_platform.h (modified) (2 diffs)
• platform_tsarv4_mono_mmu_ioc/defs_platform.h (modified) (2 diffs)
• platform_vgsb_xicu_mmu/defs_platform.h (modified) (2 diffs)

trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h

@@ -4 +4 @@
 #define IRQ_PER_PROC    1
 
+#define USE_IOB         0
 #define CACHE_COHERENCE 1
 #define CACHE_LINE_SIZE 64//bytes
@@ -13 +14 @@
 #define TTY_BASE        0xFC000000
 #define ICU_BASE        0xFD000000
+#define MCC_BASE        0xFFFFFFFF // not used
 
 /* Mandatory argument only for FPGA platforms */ 

trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h

@@ -4 +4 @@
 #define IRQ_PER_PROC    1
 
+#define USE_IOB         0
 #define CACHE_COHERENCE 1
 #define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word)
@@ -13 +14 @@
 #define ICU_BASE        0x30000000
 #define IOC_BASE        0x40000000
+#define MCC_BASE        0xFFFFFFFF // not used

trunk/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h

@@ -4 +4 @@
 #define IRQ_PER_PROC    1
 
+#define USE_IOB         0
 #define CACHE_COHERENCE 0
 #define CACHE_LINE_SIZE 16//bytes
@@ -13 +14 @@
 #define IOC_BASE        0x00F10000
 #define TTY_BASE        0x00F20000
+#define MCC_BASE        0xFFFFFFFF //not used