Ignore:
Timestamp:
Oct 31, 2013, 5:47:51 PM (11 years ago)
Author:
meunier
Message:

Correction of the "double barrier" problem from the user point of view for the generated llsc tests (use of 2 distinct barriers)

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/softs/test_llsc/scripts/test_llsc.py

    r546 r571  
    1515cluster_x = int(sys.argv[1])
    1616cluster_y = int(sys.argv[2])
    17 memspace_size = int(sys.argv[3])
     17memspace_size = int(sys.argv[3]) * 4
    1818
    1919nb_procs = 4
     
    2727            'table':   MemspacePort(),
    2828            'barrier': BarrierPort(),
     29            'barrier2': BarrierPort(),
    2930        },
    3031        impls = [
     
    4445            'table':   MemspacePort(),
    4546            'barrier': BarrierPort(),
     47            'barrier2': BarrierPort(),
    4648            'id' : ConstPort(),
    4749        },
     
    5759
    5860barrier = Barrier('barrier')
     61barrier2 = Barrier('barrier2')
    5962memspace = Memspace('memspace', memspace_size)
    6063
     
    6669               'table'   : memspace,
    6770               'barrier' : barrier,
     71               'barrier2' : barrier2,
    6872            },
    6973            defines = {} ),
     
    7579               'table'   : memspace,
    7680               'barrier' : barrier,
     81               'barrier2' : barrier2,
    7782               'id' : i,
    7883            },
    7984            defines = {} ),
    8085
    81 
    82 
    83 
    8486tcg = dsx.Tcg('test_llsc', *tasks)
    8587
    86 mpr = Mapper(hd ,tcg)
     88mpr = Mapper(hd, tcg)
    8789
    8890mpr.map('task_llsc_main', cluster = 0, proc = 0, stack = "PSEG_RAM_0")
     
    9597   mpr.map(const, pseg = 'PSEG_RAM_0')
    9698
     99
    97100mpr.map('memspace', pseg = "PSEG_RAM_0")
    98101mpr.map('barrier', pseg = "PSEG_RAM_0")
     102mpr.map('barrier2', pseg = "PSEG_RAM_0")
    99103
    100104mpr.map(tcg, code = 'PSEG_RAM_0', data = 'PSEG_RAM_0', ptab = "PSEG_RAM_0")
    101105mpr.map('system', boot = 'PSEG_RAM_0', kernel = 'PSEG_RAM_0', scheduler = True)
    102106
    103 mpr.generate(dsx.Giet(outdir = '.', vaddr_replicated_peri_inc = 0x2000, debug = True))
     107mpr.generate(dsx.Giet(outdir = '.', vaddr_replicated_peri_inc = 0x2000, debug = False))
    104108
Note: See TracChangeset for help on using the changeset viewer.