Changeset 575

Timestamp:

Nov 17, 2013, 4:02:23 PM (11 years ago)

Author:

bouyer

Message:

Make sure MOSI data changes on SPI clock falling edge,
not one system clock cycle later. With a dividor of 0, this would
delay the MOSI change to the SPI clock rising edge.

File:

• trunk/modules/vci_spi/caba/source/src/vci_spi.cpp (modified) (1 diff)

trunk/modules/vci_spi/caba/source/src/vci_spi.cpp

@@ -633 +633 @@
         break;
     case S_XMIT:
+      {
+        bool s_clk_sample = r_spi_clk ^ r_ctrl_cpha;
         p_spi_clk = r_spi_clk ^ r_ctrl_cpol;
-        p_spi_mosi = r_spi_out;
-        break;
+        if (s_clk_sample == 0) {
+            // clock low: get data directly from shift register
+            // as r_spi_out may be delayed by one clock cycle
+            p_spi_mosi = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL;
+        } else {
+            // clock high: get data from saved value, as the shift register
+            // may have changed
+            p_spi_mosi = r_spi_out;
+        }
+        break;
+      }
     }