Ignore:
Timestamp:
Dec 5, 2013, 7:39:57 PM (11 years ago)
Author:
bouyer
Message:

In VHDL, as r_dma_count is shared between 2 FSMs we can't update it in
the same cycle as going back idle. So spend an extra cycle when resetting it
to 0.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_spi/caba/source/include/vci_spi.h

    r579 r594  
    122122    M_READ_CMD          = 2,
    123123    M_READ_RSP          = 3,
    124     M_WRITE_WAIT        = 4,
    125     M_WRITE_CMD         = 5,
    126     M_WRITE_RSP         = 6,
    127     M_WRITE_END         = 7
     124    M_READ_END          = 4,
     125    M_WRITE_WAIT        = 5,
     126    M_WRITE_CMD         = 6,
     127    M_WRITE_RSP         = 7,
     128    M_WRITE_END         = 8
    128129    };
    129130
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