Changeset 595 for trunk/modules/vci_spi/caba/source
- Timestamp:
- Dec 9, 2013, 6:51:12 PM (11 years ago)
- Location:
- trunk/modules/vci_spi/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_spi/caba/source/include/vci_spi.h
r594 r595 122 122 M_READ_CMD = 2, 123 123 M_READ_RSP = 3, 124 M_ READ_END= 4,124 M_INTR = 4, 125 125 M_WRITE_WAIT = 5, 126 126 M_WRITE_CMD = 6, -
trunk/modules/vci_spi/caba/source/src/vci_spi.cpp
r594 r595 59 59 r_spi_bsy = false; 60 60 r_dma_count = 0; 61 r_dma_error = false; 61 62 r_spi_clk_counter = 0xffff; 62 63 r_spi_clk = 0; … … 178 179 #endif 179 180 } else { 180 r_irq = r_irq & r_spi_bsy;181 r_irq = false; 181 182 } 182 183 r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; … … 417 418 r_dma_count = 0; 418 419 r_dma_error = true; 419 r_initiator_fsm = M_ READ_END;420 r_initiator_fsm = M_INTR; 420 421 #ifdef SOCLIB_MODULE_DEBUG 421 422 std::cout << "vci_bd M_READ_ERROR" << std::endl; … … 425 426 { 426 427 r_dma_count = 0; 427 r_initiator_fsm = M_ READ_END;428 r_initiator_fsm = M_INTR; 428 429 r_dma_error = false; 429 430 #ifdef SOCLIB_MODULE_DEBUG … … 440 441 } 441 442 /////////////////// 442 case M_READ_END: 443 // wait one cycle because VHDL can't update r_dma_count 444 // in the same cycle as going back IDLE 443 case M_INTR: 445 444 r_initiator_fsm = M_IDLE; 445 r_irq = true; 446 446 break; 447 447 /////////////////// … … 502 502 { 503 503 if (r_spi_fsm == S_IDLE) { // write complete 504 r_initiator_fsm = M_I DLE;504 r_initiator_fsm = M_INTR; 505 505 } 506 506 break; … … 739 739 "M_READ_CMD", 740 740 "M_READ_RSP", 741 "M_ READ_END",741 "M_INTR", 742 742 743 743 "M_WRITE_WAIT",
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