Changeset 594 for trunk/modules/vci_spi/caba/source

Timestamp:

Dec 5, 2013, 7:39:57 PM (11 years ago)

Author:

bouyer

Message:

In VHDL, as r_dma_count is shared between 2 FSMs we can't update it in
the same cycle as going back idle. So spend an extra cycle when resetting it
to 0.

Location:

trunk/modules/vci_spi/caba/source

Files:

• include/vci_spi.h (modified) (1 diff)
• src/vci_spi.cpp (modified) (4 diffs)

trunk/modules/vci_spi/caba/source/include/vci_spi.h

@@ -122 +122 @@
     M_READ_CMD          = 2,
     M_READ_RSP          = 3,
-    M_WRITE_WAIT        = 4,
-    M_WRITE_CMD         = 5,
-    M_WRITE_RSP         = 6,
-    M_WRITE_END         = 7
+    M_READ_END          = 4,
+    M_WRITE_WAIT        = 5,
+    M_WRITE_CMD         = 6,
+    M_WRITE_RSP         = 7,
+    M_WRITE_END         = 8
     };
 

trunk/modules/vci_spi/caba/source/src/vci_spi.cpp

@@ -417 +417 @@
                 r_dma_count = 0;
                 r_dma_error = true;
-                r_initiator_fsm = M_IDLE;
+                r_initiator_fsm = M_READ_END;
 #ifdef SOCLIB_MODULE_DEBUG
                 std::cout << "vci_bd M_READ_ERROR" << std::endl;
@@ -425 +425 @@
             {
                 r_dma_count = 0;
-                r_initiator_fsm = M_IDLE;
+                r_initiator_fsm = M_READ_END;
                 r_dma_error = false;
 #ifdef SOCLIB_MODULE_DEBUG
@@ -439 +439 @@
         break;
     }
+    ///////////////////
+    case M_READ_END: 
+        // wait one cycle because VHDL can't update r_dma_count
+        // in the same cycle as going back IDLE
+        r_initiator_fsm = M_IDLE;
+        break;
     ///////////////////
     case M_WRITE_WAIT:  // wait for the FIFO to be empty
@@ -733 +739 @@
                 "M_READ_CMD",
                 "M_READ_RSP",
+                "M_READ_END",
 
                 "M_WRITE_WAIT",