Changeset 594 for trunk/modules/vci_spi/caba/source
- Timestamp:
- Dec 5, 2013, 7:39:57 PM (11 years ago)
- Location:
- trunk/modules/vci_spi/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_spi/caba/source/include/vci_spi.h
r579 r594 122 122 M_READ_CMD = 2, 123 123 M_READ_RSP = 3, 124 M_WRITE_WAIT = 4, 125 M_WRITE_CMD = 5, 126 M_WRITE_RSP = 6, 127 M_WRITE_END = 7 124 M_READ_END = 4, 125 M_WRITE_WAIT = 5, 126 M_WRITE_CMD = 6, 127 M_WRITE_RSP = 7, 128 M_WRITE_END = 8 128 129 }; 129 130 -
trunk/modules/vci_spi/caba/source/src/vci_spi.cpp
r592 r594 417 417 r_dma_count = 0; 418 418 r_dma_error = true; 419 r_initiator_fsm = M_ IDLE;419 r_initiator_fsm = M_READ_END; 420 420 #ifdef SOCLIB_MODULE_DEBUG 421 421 std::cout << "vci_bd M_READ_ERROR" << std::endl; … … 425 425 { 426 426 r_dma_count = 0; 427 r_initiator_fsm = M_ IDLE;427 r_initiator_fsm = M_READ_END; 428 428 r_dma_error = false; 429 429 #ifdef SOCLIB_MODULE_DEBUG … … 439 439 break; 440 440 } 441 /////////////////// 442 case M_READ_END: 443 // wait one cycle because VHDL can't update r_dma_count 444 // in the same cycle as going back IDLE 445 r_initiator_fsm = M_IDLE; 446 break; 441 447 /////////////////// 442 448 case M_WRITE_WAIT: // wait for the FIFO to be empty … … 733 739 "M_READ_CMD", 734 740 "M_READ_RSP", 741 "M_READ_END", 735 742 736 743 "M_WRITE_WAIT",
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