- Timestamp:
- Mar 19, 2014, 11:29:23 AM (11 years ago)
- Location:
- trunk
- Files:
-
- 5 edited
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modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (modified) (3 diffs)
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modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (modified) (9 diffs)
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platforms/almos-tsar-mipsel/top.desc (modified) (1 diff)
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platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (modified) (1 diff)
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platforms/tsar_generic_xbar/top.cpp (modified) (38 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r605 r663 405 405 // instrumentation counters 406 406 uint32_t m_cpt_cycles; // Counter of cycles 407 uint32_t m_cpt_reset_count; // Cycle at which the counters were last reset 407 408 408 409 // Counters accessible in software (not yet but eventually) … … 449 450 uint32_t m_cpt_write_miss; // Number of MISS WRITE 450 451 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 451 uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write452 uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because of writes 452 453 453 454 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt … … 515 516 ~VciMemCache(); 516 517 518 void reset_counters(); 517 519 void print_stats(bool activity_counters, bool stats); 518 520 void print_trace( size_t detailed = 0 ); -
trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r649 r663 31 31 * alexandre.joannou@lip6.fr 32 32 */ 33 33 34 34 35 #include "../include/vci_mem_cache.h" … … 799 800 } 800 801 802 803 ///////////////////////////////////////// 804 tmpl(void)::reset_counters() 805 ///////////////////////////////////////// 806 { 807 m_cpt_reset_count = m_cpt_cycles; 808 m_cpt_read_local = 0; 809 m_cpt_read_remote = 0; 810 m_cpt_read_cost = 0; 811 m_cpt_write_local = 0; 812 m_cpt_write_remote = 0; 813 m_cpt_write_flits_local = 0; 814 m_cpt_write_flits_remote = 0; 815 m_cpt_write_cost = 0; 816 m_cpt_ll_local = 0; 817 m_cpt_ll_remote = 0; 818 m_cpt_ll_cost = 0; 819 m_cpt_sc_local = 0; 820 m_cpt_sc_remote = 0; 821 m_cpt_sc_cost = 0; 822 m_cpt_cas_local = 0; 823 m_cpt_cas_remote = 0; 824 m_cpt_cas_cost = 0; 825 m_cpt_update = 0; 826 m_cpt_update_local = 0; 827 m_cpt_update_remote = 0; 828 m_cpt_update_cost = 0; 829 m_cpt_minval = 0; 830 m_cpt_minval_local = 0; 831 m_cpt_minval_remote = 0; 832 m_cpt_minval_cost = 0; 833 m_cpt_binval = 0; 834 m_cpt_cleanup_local = 0; 835 m_cpt_cleanup_remote = 0; 836 m_cpt_cleanup_cost = 0; 837 m_cpt_read_miss = 0; 838 m_cpt_write_miss = 0; 839 m_cpt_write_dirty = 0; 840 m_cpt_trt_rb = 0; 841 m_cpt_trt_full = 0; 842 m_cpt_get = 0; 843 m_cpt_put = 0; 844 } 801 845 802 846 ///////////////////////////////////////// … … 812 856 std::cout << "----------------------------------" << std::dec << std::endl; 813 857 std::cout 858 << "[000] COUNTERS RESET AT CYCLE = " << m_cpt_reset_count << std::endl 814 859 << "[001] NUMBER OF CYCLES = " << m_cpt_cycles << std::endl 815 860 << std::endl … … 941 986 delete [] m_debug_data; 942 987 943 print_stats();988 //print_stats(); 944 989 } 945 990 … … 1068 1113 // Activity counters 1069 1114 m_cpt_cycles = 0; 1115 m_cpt_reset_count = 0; 1070 1116 m_cpt_read_local = 0; 1071 1117 m_cpt_read_remote = 0; … … 1206 1252 if (p_vci_tgt.cmdval) 1207 1253 { 1208 1209 1254 #if DEBUG_MEMC_TGT_CMD 1210 1255 if (m_debug) … … 3705 3750 "MEMC ERROR in WRITE_BC_DIR_READ state: Bad DIR allocation"); 3706 3751 3707 m_cpt_write_broadcast++;3708 3709 3752 // write enable signal for data buffer. 3710 3753 r_write_bc_data_we = true; … … 5509 5552 << " address = " << std::hex << r_cleanup_nline.read()*m_words*4 5510 5553 << " / way = " << std::dec << r_cleanup_way.read() 5511 << " / srcid = " << std:: dec<< r_cleanup_srcid.read()5554 << " / srcid = " << std::hex << r_cleanup_srcid.read() 5512 5555 << std::endl; 5513 5556 #endif … … 6639 6682 // <Activity Counters> 6640 6683 m_cpt_binval++; 6684 m_cpt_write_broadcast++; 6641 6685 // </Activity Counters> 6642 6686 -
trunk/platforms/almos-tsar-mipsel/top.desc
r609 r663 23 23 24 24 uses = [ 25 Uses('caba:tsar_xbar_cluster ',25 Uses('caba:tsar_xbar_cluster_almos', 26 26 vci_data_width_int = vci_cell_size_int, 27 27 vci_data_width_ext = vci_cell_size_ext, -
trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd
r609 r663 2 2 # -*- python -*- 3 3 4 Module('caba:tsar_xbar_cluster ',4 Module('caba:tsar_xbar_cluster_almos', 5 5 classname = 'soclib::caba::TsarXbarCluster', 6 6 tmpl_parameters = [ -
trunk/platforms/tsar_generic_xbar/top.cpp
r625 r663 91 91 #include "gdbserver.h" 92 92 #include "mapping_table.h" 93 #include "alloc_elems.h" 93 94 #include "tsar_xbar_cluster.h" 94 #include "alloc_elems.h" 95 96 /////////////////////////////////////////////////// 97 // OS 98 /////////////////////////////////////////////////// 99 100 //#define USE_ALMOS 1 101 #define USE_GIET 1 95 96 #define USE_ALMOS 1 97 //#define USE_GIET 102 98 103 99 #ifdef USE_ALMOS … … 113 109 #endif 114 110 111 #ifdef USE_ALMOS 112 #define PREFIX_OS "almos/" 113 #include "almos/hard_config.h" 114 #endif 115 #ifdef USE_GIET 116 #define PREFIX_OS "giet_vm/" 117 #endif 118 115 119 /////////////////////////////////////////////////// 116 120 // Parallelisation 117 121 /////////////////////////////////////////////////// 122 118 123 #define USE_OPENMP 0 119 124 … … 124 129 // cluster index (computed from x,y coordinates) 125 130 #ifdef USE_ALMOS 126 # define cluster(x,y) (y + x * Y_MAX)131 #define cluster(x,y) (y + x * Y_SIZE) 127 132 #else 128 #define cluster(x,y) (y + (x << Y_WIDTH))133 #define cluster(x,y) (y + (x << Y_WIDTH)) 129 134 #endif 130 135 … … 162 167 163 168 //////////////////////////////////////////////////////////// 164 // Main Hardware Parameters values165 //////////////////////i/////////////////////////////////////166 167 #ifdef USE_ALMOS168 #include "almos/hard_config.h"169 #define PREFIX_OS "almos/"170 #endif171 #ifdef USE_GIET172 #include "giet_vm/hard_config.h"173 #define PREFIX_OS "giet_vm/"174 #endif175 176 ////////////////////////////////////////////////////////////177 169 // Secondary Hardware Parameters 178 170 //////////////////////i///////////////////////////////////// 179 171 180 #define XMAX X_SIZE181 #define YMAX Y_SIZE182 172 183 173 #define XRAM_LATENCY 0 … … 193 183 194 184 #ifdef USE_ALMOS 195 #define FBUF_X_SIZE 512196 #define FBUF_Y_SIZE 512185 #define FBUF_X_SIZE 1024 186 #define FBUF_Y_SIZE 1024 197 187 #endif 198 188 #ifdef USE_GIET … … 224 214 225 215 #ifdef USE_ALMOS 226 #define soft_name PREFIX_OS"bootloader .bin",\216 #define soft_name PREFIX_OS"bootloader-tsar-mipsel.bin",\ 227 217 PREFIX_OS"kernel-soclib.bin@0xbfc10000:D",\ 228 218 PREFIX_OS"arch-info.bib@0xBFC08000:D" … … 236 226 //////////////////////i///////////////////////////////////// 237 227 238 #define MAX_FROZEN_CYCLES 1000000 239 228 #define MAX_FROZEN_CYCLES 100000000 240 229 241 230 … … 249 238 #define MDMA_TGTID 2 250 239 #define MTTY_TGTID 3 251 #define FBUF_TGTID 4 252 #define BDEV_TGTID 5 253 #define MNIC_TGTID 6 254 #define BROM_TGTID 7 255 #define CDMA_TGTID 8 256 #define SIMH_TGTID 9 257 240 #define BDEV_TGTID 4 241 #define MNIC_TGTID 5 242 #define BROM_TGTID 6 243 #define CDMA_TGTID 7 244 #define SIMH_TGTID 8 245 #define FBUF_TGTID 9 258 246 259 247 … … 307 295 // (Almos supports 32 bits physical addresses) 308 296 309 #define CLUSTER_IO_INC (cluster_io_id * (0x80000000ULL / (XMAX * YMAX) * 2)) 310 311 #define MEMC_MAX_SIZE (0x80000000 / (XMAX * YMAX)) 297 #define CLUSTER_IO_INC (cluster_io_id * (0x80000000ULL / (X_SIZE * Y_SIZE) * 2)) 298 #define MEMC_MAX_SIZE (0x40000000 / (X_SIZE * Y_SIZE)) 312 299 313 300 #define BROM_BASE 0x00BFC00000 … … 315 302 316 303 #define MEMC_BASE 0x0000000000 317 #define MEMC_SIZE min(0x0 2000000, MEMC_MAX_SIZE)304 #define MEMC_SIZE min(0x04000000, MEMC_MAX_SIZE) 318 305 319 306 #define XICU_BASE MEMC_MAX_SIZE + (XICU_TGTID << 19) … … 325 312 #define BDEV_BASE MEMC_MAX_SIZE + (BDEV_TGTID << 19) + (CLUSTER_IO_INC) 326 313 #define BDEV_SIZE 0x0000001000 // 4 Kbytes 327 314 328 315 #define MTTY_BASE MEMC_MAX_SIZE + (MTTY_TGTID << 19) + (CLUSTER_IO_INC) 329 316 #define MTTY_SIZE 0x0000001000 // 4 Kbytes 330 317 331 318 #define FBUF_BASE MEMC_MAX_SIZE + (FBUF_TGTID << 19) + (CLUSTER_IO_INC) 332 319 #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) // Should be 0x80000 333 320 334 321 #define MNIC_BASE MEMC_MAX_SIZE + (MNIC_TGTID << 19) + (CLUSTER_IO_INC) 335 322 #define MNIC_SIZE 0x0000080000 336 323 337 324 #define CDMA_BASE MEMC_MAX_SIZE + (CDMA_TGTID << 19) + (CLUSTER_IO_INC) 338 325 #define CDMA_SIZE (0x0000004000 * NB_CMA_CHANNELS) 339 326 340 327 #define SIMH_BASE MEMC_MAX_SIZE + (SIMH_TGTID << 19) + (CLUSTER_IO_INC) 341 328 #define SIMH_SIZE 0x0000001000 342 343 #endif 344 329 #endif 345 330 346 331 bool stop_called = false; … … 354 339 355 340 #ifdef USE_GIET 356 char soft_name[256] = soft_pathname; // pathname to binary code 357 #endif 358 uint64_t ncycles = 0xFFFFFFFFFFFFFFFF; // simulated cycles 359 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image 360 char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file 361 char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file 362 ssize_t threads_nr = 1; // simulator's threads number 363 bool debug_ok = false; // trace activated 364 size_t debug_period = 1; // trace period 365 size_t debug_memc_id = 0; // index of memc to be traced 366 size_t debug_proc_id = 0; // index of proc to be traced 367 uint32_t debug_from = 0; // trace start cycle 368 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 341 char soft_name[256] = soft_pathname; // pathname to binary code 342 #endif 343 const int64_t max_cycles = 5000000; // Maximum number of cycles simulated in one sc_start call 344 int64_t ncycles = 0x7FFFFFFFFFFFFFFF; // simulated cycles 345 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image 346 char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file 347 char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file 348 ssize_t threads_nr = 1; // simulator's threads number 349 bool debug_ok = false; // trace activated 350 size_t debug_period = 1; // trace period 351 size_t debug_memc_id = 0; // index of memc to be traced 352 size_t debug_proc_id = 0; // index of proc to be traced 353 int64_t debug_from = 0; // trace start cycle 354 int64_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 369 355 size_t cluster_io_id; // index of cluster containing IOs 370 struct timeval t1,t2; 371 uint64_t ms1,ms2; 356 int64_t reset_counters = -1; 357 int64_t dump_counters = -1; 358 bool do_reset_counters = false; 359 bool do_dump_counters = false; 360 struct timeval t1, t2; 361 uint64_t ms1, ms2; 372 362 373 363 ////////////// command line arguments ////////////////////// … … 378 368 if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) 379 369 { 380 ncycles = ( uint64_t) strtol(argv[n + 1], NULL, 0);370 ncycles = (int64_t) strtol(argv[n + 1], NULL, 0); 381 371 } 382 372 else if ((strcmp(argv[n], "-SOFT") == 0) && (n + 1 < argc)) … … 396 386 { 397 387 debug_ok = true; 398 debug_from = ( uint32_t) strtol(argv[n + 1], NULL, 0);388 debug_from = (int64_t) strtol(argv[n + 1], NULL, 0); 399 389 } 400 390 else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) 401 391 { 402 392 debug_memc_id = (size_t) strtol(argv[n + 1], NULL, 0); 403 404 #ifdef USE_ALMOS 405 assert((debug_memc_id < (XMAX * YMAX)) && 406 "debug_memc_id larger than XMAX * YMAX" ); 393 #ifdef USE_ALMOS 394 assert((debug_memc_id < (X_SIZE * Y_SIZE)) && 395 "debug_memc_id larger than X_SIZE * Y_SIZE" ); 407 396 #else 408 397 size_t x = debug_memc_id >> Y_WIDTH; 409 398 size_t y = debug_memc_id & ((1<<Y_WIDTH)-1); 410 399 411 assert( (x <= X MAX) and (y <= YMAX) &&400 assert( (x <= X_SIZE) and (y <= Y_SIZE) && 412 401 "MEMCID parameter refers a not valid memory cache"); 413 402 #endif … … 416 405 { 417 406 debug_proc_id = (size_t) strtol(argv[n + 1], NULL, 0); 418 419 #ifdef USE_ALMOS 420 assert((debug_proc_id < (XMAX * YMAX * NB_PROCS_MAX)) && 421 "debug_proc_id larger than XMAX * YMAX * NB_PROCS"); 407 #ifdef USE_ALMOS 408 assert((debug_proc_id < (X_SIZE * Y_SIZE * NB_PROCS_MAX)) && 409 "debug_proc_id larger than X_SIZE * Y_SIZE * NB_PROCS"); 422 410 #else 423 411 size_t cluster_xy = debug_proc_id / NB_PROCS_MAX ; … … 425 413 size_t y = cluster_xy & ((1<<Y_WIDTH)-1); 426 414 427 assert( (x <= X MAX) and (y <= YMAX) &&415 assert( (x <= X_SIZE) and (y <= Y_SIZE) && 428 416 "PROCID parameter refers a not valid processor"); 429 417 #endif … … 436 424 else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc)) 437 425 { 438 frozen_cycles = ( uint32_t) strtol(argv[n + 1], NULL, 0);426 frozen_cycles = (int64_t) strtol(argv[n + 1], NULL, 0); 439 427 } 440 428 else if ((strcmp(argv[n], "-PERIOD") == 0) && (n + 1 < argc)) 441 429 { 442 430 debug_period = (size_t) strtol(argv[n + 1], NULL, 0); 431 } 432 else if ((strcmp(argv[n], "--reset-counters") == 0) && (n + 1 < argc)) 433 { 434 reset_counters = (int64_t) strtol(argv[n + 1], NULL, 0); 435 do_reset_counters = true; 436 } 437 else if ((strcmp(argv[n], "--dump-counters") == 0) && (n + 1 < argc)) 438 { 439 dump_counters = (int64_t) strtol(argv[n + 1], NULL, 0); 440 do_dump_counters = true; 443 441 } 444 442 else … … 462 460 463 461 // checking hardware parameters 464 assert( ( (X MAX == 1) or (XMAX == 2) or (XMAX== 4) or465 (X MAX == 8) or (XMAX== 16) ) and466 "The X MAXparameter must be 1, 2, 4, 8 or 16" );467 468 assert( ( (Y MAX == 1) or (YMAX == 2) or (YMAX== 4) or469 (Y MAX == 8) or (YMAX== 16) ) and470 "The Y MAXparameter must be 1, 2, 4, 8 or 16" );462 assert( ( (X_SIZE == 1) or (X_SIZE == 2) or (X_SIZE == 4) or 463 (X_SIZE == 8) or (X_SIZE == 16) ) and 464 "The X_SIZE parameter must be 1, 2, 4, 8 or 16" ); 465 466 assert( ( (Y_SIZE == 1) or (Y_SIZE == 2) or (Y_SIZE == 4) or 467 (Y_SIZE == 8) or (Y_SIZE == 16) ) and 468 "The Y_SIZE parameter must be 1, 2, 4, 8 or 16" ); 471 469 472 470 assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or … … 495 493 496 494 std::cout << std::endl; 497 std::cout << " - X MAX = " << XMAX<< std::endl;498 std::cout << " - Y MAX = " << YMAX<< std::endl;495 std::cout << " - X_SIZE = " << X_SIZE << std::endl; 496 std::cout << " - Y_SIZE = " << Y_SIZE << std::endl; 499 497 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; 500 498 std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; … … 505 503 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; 506 504 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; 507 std::cout << "[PROCS] " << NB_PROCS_MAX * XMAX * YMAX << std::endl;508 505 509 506 std::cout << std::endl; … … 537 534 #endif 538 535 539 #ifdef USE_ALMOS 540 541 if (XMAX == 1) x_width = 0; 542 else if (XMAX == 2) x_width = 1; 543 else if (XMAX <= 4) x_width = 2; 544 else if (XMAX <= 8) x_width = 3; 536 // Define parameters depending on mesh size 537 size_t x_width; 538 size_t y_width; 539 540 #ifdef USE_ALMOS 541 if (X_SIZE == 1) x_width = 0; 542 else if (X_SIZE == 2) x_width = 1; 543 else if (X_SIZE <= 4) x_width = 2; 544 else if (X_SIZE <= 8) x_width = 3; 545 545 else x_width = 4; 546 546 547 if (Y MAX== 1) y_width = 0;548 else if (Y MAX== 2) y_width = 1;549 else if (Y MAX<= 4) y_width = 2;550 else if (Y MAX<= 8) y_width = 3;547 if (Y_SIZE == 1) y_width = 0; 548 else if (Y_SIZE == 2) y_width = 1; 549 else if (Y_SIZE <= 4) y_width = 2; 550 else if (Y_SIZE <= 8) y_width = 3; 551 551 else y_width = 4; 552 552 553 553 #else 554 555 554 size_t x_width = X_WIDTH; 556 555 size_t y_width = Y_WIDTH; … … 559 558 "Up to 256 clusters"); 560 559 561 assert( (X MAX <= (1 << X_WIDTH)) and (YMAX<= (1 << Y_WIDTH)) and560 assert( (X_SIZE <= (1 << X_WIDTH)) and (Y_SIZE <= (1 << Y_WIDTH)) and 562 561 "The X_WIDTH and Y_WIDTH parameter are insufficient"); 563 562 564 563 #endif 565 566 564 567 565 // index of cluster containing IOs 568 566 cluster_io_id = 0x00bfc00000ULL >> (vci_address_width - x_width - y_width); 567 569 568 570 569 ///////////////////// … … 578 577 0x00FF800000); 579 578 580 for (size_t x = 0; x < X MAX; x++)579 for (size_t x = 0; x < X_SIZE; x++) 581 580 { 582 for (size_t y = 0; y < Y MAX; y++)581 for (size_t y = 0; y < Y_SIZE; y++) 583 582 { 584 583 sc_uint<vci_address_width> offset; … … 628 627 0xFFFF000000ULL); 629 628 630 for (size_t x = 0; x < X MAX; x++)629 for (size_t x = 0; x < X_SIZE; x++) 631 630 { 632 for (size_t y = 0; y < Y MAX; y++)631 for (size_t y = 0; y < Y_SIZE ; y++) 633 632 { 634 633 … … 655 654 // Horizontal inter-clusters DSPIN signals 656 655 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc = 657 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X MAX-1, YMAX, 3);656 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE, 3); 658 657 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec = 659 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X MAX-1, YMAX, 3);658 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE, 3); 660 659 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc = 661 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X MAX-1, YMAX, 2);660 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE, 2); 662 661 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec = 663 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X MAX-1, YMAX, 2);662 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE, 2); 664 663 665 664 // Vertical inter-clusters DSPIN signals 666 665 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc = 667 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X MAX, YMAX-1, 3);666 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1, 3); 668 667 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec = 669 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X MAX, YMAX-1, 3);668 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1, 3); 670 669 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc = 671 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X MAX, YMAX-1, 2);670 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1, 2); 672 671 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec = 673 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X MAX, YMAX-1, 2);672 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1, 2); 674 673 675 674 // Mesh boundaries DSPIN signals 676 675 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in = 677 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in" , X MAX, YMAX, 4, 3);676 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in" , X_SIZE, Y_SIZE, 4, 3); 678 677 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out = 679 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", X MAX, YMAX, 4, 3);678 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", X_SIZE, Y_SIZE, 4, 3); 680 679 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in = 681 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in" , X MAX, YMAX, 4, 2);680 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in" , X_SIZE, Y_SIZE, 4, 2); 682 681 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out = 683 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", X MAX, YMAX, 4, 2);682 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", X_SIZE, Y_SIZE, 4, 2); 684 683 685 684 … … 700 699 dspin_rsp_width, 701 700 vci_param_int, 702 vci_param_ext>* clusters[X MAX][YMAX];701 vci_param_ext>* clusters[X_SIZE][Y_SIZE]; 703 702 704 703 #if USE_OPENMP … … 707 706 #pragma omp for 708 707 #endif 709 for (size_t i = 0; i < (X MAX * YMAX); i++)708 for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) 710 709 { 711 size_t x = i / Y MAX;712 size_t y = i % Y MAX;710 size_t x = i / Y_SIZE; 711 size_t y = i % Y_SIZE; 713 712 714 713 #if USE_OPENMP … … 768 767 loader, 769 768 frozen_cycles, 770 debug_from 769 debug_from, 771 770 debug_ok and (cluster(x,y) == debug_memc_id), 772 771 debug_ok and (cluster(x,y) == debug_proc_id) … … 786 785 787 786 // Clock & RESET 788 for (size_t x = 0; x < (X MAX); x++){789 for (size_t y = 0; y < Y MAX; y++){787 for (size_t x = 0; x < (X_SIZE); x++){ 788 for (size_t y = 0; y < Y_SIZE; y++){ 790 789 clusters[x][y]->p_clk (signal_clk); 791 790 clusters[x][y]->p_resetn (signal_resetn); … … 794 793 795 794 // Inter Clusters horizontal connections 796 if (X MAX> 1){797 for (size_t x = 0; x < (X MAX-1); x++){798 for (size_t y = 0; y < Y MAX; y++){795 if (X_SIZE > 1){ 796 for (size_t x = 0; x < (X_SIZE-1); x++){ 797 for (size_t y = 0; y < Y_SIZE; y++){ 799 798 for (size_t k = 0; k < 3; k++){ 800 799 clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]); … … 816 815 817 816 // Inter Clusters vertical connections 818 if (Y MAX> 1) {819 for (size_t y = 0; y < (Y MAX-1); y++){820 for (size_t x = 0; x < X MAX; x++){817 if (Y_SIZE > 1) { 818 for (size_t y = 0; y < (Y_SIZE-1); y++){ 819 for (size_t x = 0; x < X_SIZE; x++){ 821 820 for (size_t k = 0; k < 3; k++){ 822 821 clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]); … … 838 837 839 838 // East & West boundary cluster connections 840 for (size_t y = 0; y < Y MAX; y++)839 for (size_t y = 0; y < Y_SIZE; y++) 841 840 { 842 841 for (size_t k = 0; k < 3; k++) … … 844 843 clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in[0][y][WEST][k]); 845 844 clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]); 846 clusters[X MAX-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in[XMAX-1][y][EAST][k]);847 clusters[X MAX-1][y]->p_cmd_out[EAST][k] (signal_dspin_false_cmd_out[XMAX-1][y][EAST][k]);845 clusters[X_SIZE-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in[X_SIZE-1][y][EAST][k]); 846 clusters[X_SIZE-1][y]->p_cmd_out[EAST][k] (signal_dspin_false_cmd_out[X_SIZE-1][y][EAST][k]); 848 847 } 849 848 … … 852 851 clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in[0][y][WEST][k]); 853 852 clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]); 854 clusters[X MAX-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in[XMAX-1][y][EAST][k]);855 clusters[X MAX-1][y]->p_rsp_out[EAST][k] (signal_dspin_false_rsp_out[XMAX-1][y][EAST][k]);853 clusters[X_SIZE-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in[X_SIZE-1][y][EAST][k]); 854 clusters[X_SIZE-1][y]->p_rsp_out[EAST][k] (signal_dspin_false_rsp_out[X_SIZE-1][y][EAST][k]); 856 855 } 857 856 } 858 857 859 858 // North & South boundary clusters connections 860 for (size_t x = 0; x < X MAX; x++)859 for (size_t x = 0; x < X_SIZE; x++) 861 860 { 862 861 for (size_t k = 0; k < 3; k++) … … 864 863 clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in[x][0][SOUTH][k]); 865 864 clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]); 866 clusters[x][Y MAX-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in[x][YMAX-1][NORTH][k]);867 clusters[x][Y MAX-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][YMAX-1][NORTH][k]);865 clusters[x][Y_SIZE-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in[x][Y_SIZE-1][NORTH][k]); 866 clusters[x][Y_SIZE-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][Y_SIZE-1][NORTH][k]); 868 867 } 869 868 … … 872 871 clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in[x][0][SOUTH][k]); 873 872 clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]); 874 clusters[x][Y MAX-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in[x][YMAX-1][NORTH][k]);875 clusters[x][Y MAX-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][YMAX-1][NORTH][k]);873 clusters[x][Y_SIZE-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in[x][Y_SIZE-1][NORTH][k]); 874 clusters[x][Y_SIZE-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][Y_SIZE-1][NORTH][k]); 876 875 } 877 876 } … … 888 887 889 888 // network boundaries signals 890 for (size_t x = 0; x < X MAX; x++){891 for (size_t y = 0; y < Y MAX; y++){889 for (size_t x = 0; x < X_SIZE ; x++){ 890 for (size_t y = 0; y < Y_SIZE ; y++){ 892 891 for (size_t a = 0; a < 4; a++){ 893 892 for (size_t k = 0; k < 3; k++){ … … 911 910 signal_resetn = true; 912 911 913 if (gettimeofday(&t1, NULL) != 0) 914 { 915 perror("gettimeofday"); 916 return EXIT_FAILURE; 917 } 918 919 for (uint64_t n = 1; n < ncycles && !stop_called; n++) 920 { 921 // Monitor a specific address for L1 & L2 caches 922 //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL); 923 //clusters[1][0]->memc->copies_monitor(0x800002C000ULL); 924 925 if( (n % 5000000) == 0) 912 if (debug_ok) { 913 #if USE_OPENMP 914 assert(false && "OPEN MP should not be used with debug because of its traces"); 915 #endif 916 917 if (gettimeofday(&t1, NULL) != 0) { 918 perror("gettimeofday"); 919 return EXIT_FAILURE; 920 } 921 922 for (int64_t n = 1; n < ncycles && !stop_called; n++) 926 923 { 927 928 if (gettimeofday(&t2, NULL) != 0) 929 { 924 // Monitor a specific address for L1 & L2 caches 925 //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL); 926 //clusters[1][0]->memc->copies_monitor(0x800002C000ULL); 927 928 if ((n % max_cycles) == 0) 929 { 930 931 if (gettimeofday(&t2, NULL) != 0) 932 { 933 perror("gettimeofday"); 934 return EXIT_FAILURE; 935 } 936 937 ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; 938 ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; 939 std::cerr << "platform clock frequency " << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl; 940 941 if (gettimeofday(&t1, NULL) != 0) 942 { 943 perror("gettimeofday"); 944 return EXIT_FAILURE; 945 } 946 } 947 948 949 if (n == reset_counters) { 950 for (size_t x = 0; x < (X_SIZE); x++) { 951 for (size_t y = 0; y < Y_SIZE; y++) { 952 clusters[x][y]->memc->reset_counters(); 953 } 954 } 955 } 956 957 if (n == dump_counters) { 958 for (size_t x = 0; x < (X_SIZE); x++) { 959 for (size_t y = 0; y < Y_SIZE; y++) { 960 clusters[x][y]->memc->print_stats(true, false); 961 } 962 } 963 } 964 965 if (debug_ok and (n > debug_from) and (n % debug_period == 0)) 966 { 967 std::cout << "****************** cycle " << std::dec << n ; 968 std::cout << " ************************************************" << std::endl; 969 970 // trace proc[debug_proc_id] 971 size_t l = debug_proc_id % NB_PROCS_MAX ; 972 size_t y = (debug_proc_id / NB_PROCS_MAX) % Y_SIZE ; 973 size_t x = debug_proc_id / (Y_SIZE * NB_PROCS_MAX) ; 974 975 std::ostringstream proc_signame; 976 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 977 std::ostringstream p2m_signame; 978 p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; 979 std::ostringstream m2p_signame; 980 m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; 981 std::ostringstream p_cmd_signame; 982 p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ; 983 std::ostringstream p_rsp_signame; 984 p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ; 985 986 //clusters[x][y]->wi_proc[l]->print_trace(); 987 //clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); 988 //clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); 989 //clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); 990 //clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str()); 991 //clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str()); 992 993 //clusters[x][y]->xbar_rsp_d->print_trace(); 994 //clusters[x][y]->xbar_cmd_d->print_trace(); 995 //clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); 996 //clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); 997 //clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); 998 //clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); 999 1000 // trace memc[debug_memc_id] 1001 x = debug_memc_id / Y_SIZE; 1002 y = debug_memc_id % Y_SIZE; 1003 1004 std::ostringstream smemc; 1005 smemc << "[SIG]MEMC_" << x << "_" << y; 1006 std::ostringstream sxram; 1007 sxram << "[SIG]XRAM_" << x << "_" << y; 1008 std::ostringstream sm2p; 1009 sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; 1010 std::ostringstream sp2m; 1011 sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; 1012 std::ostringstream m_cmd_signame; 1013 m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ; 1014 std::ostringstream m_rsp_signame; 1015 m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ; 1016 1017 //clusters[x][y]->memc->print_trace(); 1018 //clusters[x][y]->wt_memc->print_trace(); 1019 //clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); 1020 //clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); 1021 //clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); 1022 //clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); 1023 //clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(m_cmd_signame.str()); 1024 //clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(m_rsp_signame.str()); 1025 1026 // trace replicated peripherals 1027 //clusters[1][1]->mdma->print_trace(); 1028 //clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1"); 1029 //clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1"); 1030 1031 1032 // trace external peripherals 1033 //size_t io_x = cluster_io_id / Y_SIZE; 1034 //size_t io_y = cluster_io_id % Y_SIZE; 1035 1036 //clusters[io_x][io_y]->brom->print_trace(); 1037 //clusters[io_x][io_y]->wt_brom->print_trace(); 1038 //clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM"); 1039 //clusters[io_x][io_y]->signal_dspin_cmd_brom_t.print_trace("[SIG]BROM CMD"); 1040 //clusters[io_x][io_y]->signal_dspin_rsp_brom_t.print_trace("[SIG]BROM RSP"); 1041 1042 //clusters[io_x][io_y]->bdev->print_trace(); 1043 //clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); 1044 //clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 1045 } 1046 1047 sc_start(sc_core::sc_time(1, SC_NS)); 1048 } 1049 } 1050 else { 1051 int64_t n = 0; 1052 while (!stop_called) { 1053 if (gettimeofday(&t1, NULL) != 0) { 930 1054 perror("gettimeofday"); 931 1055 return EXIT_FAILURE; 932 1056 } 933 1057 int64_t nb_cycles = max_cycles; 1058 if (do_reset_counters) { 1059 nb_cycles = min(nb_cycles, reset_counters - n); 1060 } 1061 if (do_dump_counters) { 1062 nb_cycles = min(nb_cycles, dump_counters - n); 1063 } 1064 1065 sc_start(sc_core::sc_time(nb_cycles, SC_NS)); 1066 n += nb_cycles; 1067 1068 if (do_reset_counters && n == reset_counters) { 1069 // Reseting counters 1070 for (size_t x = 0; x < (X_SIZE); x++) { 1071 for (size_t y = 0; y < Y_SIZE; y++) { 1072 clusters[x][y]->memc->reset_counters(); 1073 } 1074 } 1075 do_reset_counters = false; 1076 } 1077 1078 if (do_dump_counters && n == dump_counters) { 1079 // Dumping counters 1080 for (size_t x = 0; x < (X_SIZE); x++) { 1081 for (size_t y = 0; y < Y_SIZE; y++) { 1082 clusters[x][y]->memc->print_stats(true, false); 1083 } 1084 } 1085 do_dump_counters = false; 1086 } 1087 1088 1089 if (gettimeofday(&t2, NULL) != 0) { 1090 perror("gettimeofday"); 1091 return EXIT_FAILURE; 1092 } 934 1093 ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; 935 1094 ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; 936 std::cerr << "platform clock frequency " << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl; 937 938 if (gettimeofday(&t1, NULL) != 0) 939 { 940 perror("gettimeofday"); 941 return EXIT_FAILURE; 942 } 943 } 944 945 if (debug_ok and (n > debug_from) and (n % debug_period == 0)) 946 { 947 std::cout << "****************** cycle " << std::dec << n ; 948 std::cout << " ************************************************" << std::endl; 949 950 // trace proc[debug_proc_id] 951 size_t l = debug_proc_id % NB_PROCS_MAX ; 952 size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ; 953 size_t x = (debug_proc_id / ((1 << y_width) * NB_PROCS_MAX)) % XMAX ; 954 955 std::ostringstream proc_signame; 956 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 957 std::ostringstream p2m_signame; 958 p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; 959 std::ostringstream m2p_signame; 960 m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; 961 std::ostringstream p_cmd_signame; 962 p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ; 963 std::ostringstream p_rsp_signame; 964 p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ; 965 966 clusters[x][y]->proc[l]->print_trace(); 967 clusters[x][y]->wi_proc[l]->print_trace(); 968 clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); 969 clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); 970 clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); 971 clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str()); 972 clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str()); 973 974 clusters[x][y]->xbar_rsp_d->print_trace(); 975 clusters[x][y]->xbar_cmd_d->print_trace(); 976 clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); 977 clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); 978 clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); 979 clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); 980 981 // trace memc[debug_memc_id] 982 x = debug_memc_id / YMAX; 983 y = debug_memc_id % YMAX; 984 985 std::ostringstream smemc; 986 smemc << "[SIG]MEMC_" << x << "_" << y; 987 std::ostringstream sxram; 988 sxram << "[SIG]XRAM_" << x << "_" << y; 989 std::ostringstream sm2p; 990 sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; 991 std::ostringstream sp2m; 992 sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; 993 std::ostringstream m_cmd_signame; 994 m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ; 995 std::ostringstream m_rsp_signame; 996 m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ; 997 998 clusters[x][y]->memc->print_trace(); 999 clusters[x][y]->wt_memc->print_trace(); 1000 clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); 1001 clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); 1002 clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); 1003 clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); 1004 clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(m_cmd_signame.str()); 1005 clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(m_rsp_signame.str()); 1006 1007 // trace replicated peripherals 1008 // clusters[1][1]->mdma->print_trace(); 1009 // clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1"); 1010 // clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1"); 1011 1012 1013 // trace external peripherals 1014 size_t io_x = cluster_io_id >> y_width; 1015 size_t io_y = cluster_io_id & ((1 << x_width) - 1); 1016 1017 clusters[io_x][io_y]->brom->print_trace(); 1018 clusters[io_x][io_y]->wt_brom->print_trace(); 1019 clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM"); 1020 clusters[io_x][io_y]->signal_dspin_cmd_brom_t.print_trace("[SIG]BROM CMD"); 1021 clusters[io_x][io_y]->signal_dspin_rsp_brom_t.print_trace("[SIG]BROM RSP"); 1022 1023 // clusters[io_x][io_y]->bdev->print_trace(); 1024 // clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); 1025 // clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 1026 } 1027 1028 sc_start(sc_core::sc_time(1, SC_NS)); 1095 std::cerr << "cycle " << n << " platform clock frequency " << (double) nb_cycles / (double) (ms2 - ms1) << "Khz" << std::endl; 1096 } 1029 1097 } 1030 1098 1031 1099 1032 1100 // Free memory 1033 for (size_t i = 0; i < (X MAX * YMAX); i++)1101 for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) 1034 1102 { 1035 size_t x = i / Y MAX;1036 size_t y = i % Y MAX;1103 size_t x = i / Y_SIZE; 1104 size_t y = i % Y_SIZE; 1037 1105 delete clusters[x][y]; 1038 1106 } 1039 1107 1040 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_inc, X MAX - 1, YMAX, 3);1041 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_dec, X MAX - 1, YMAX, 3);1042 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_inc, X MAX - 1, YMAX, 2);1043 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_dec, X MAX - 1, YMAX, 2);1044 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_inc, X MAX, YMAX- 1, 3);1045 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_dec, X MAX, YMAX- 1, 3);1046 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_inc, X MAX, YMAX- 1, 2);1047 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_dec, X MAX, YMAX- 1, 2);1048 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_in, X MAX, YMAX, 4, 3);1049 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_out, X MAX, YMAX, 4, 3);1050 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_in, X MAX, YMAX, 4, 2);1051 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_out, X MAX, YMAX, 4, 2);1108 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_inc, X_SIZE - 1, Y_SIZE, 3); 1109 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_dec, X_SIZE - 1, Y_SIZE, 3); 1110 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_inc, X_SIZE - 1, Y_SIZE, 2); 1111 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_dec, X_SIZE - 1, Y_SIZE, 2); 1112 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_inc, X_SIZE, Y_SIZE - 1, 3); 1113 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_dec, X_SIZE, Y_SIZE - 1, 3); 1114 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_inc, X_SIZE, Y_SIZE - 1, 2); 1115 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_dec, X_SIZE, Y_SIZE - 1, 2); 1116 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_in, X_SIZE, Y_SIZE, 4, 3); 1117 dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_false_cmd_out, X_SIZE, Y_SIZE, 4, 3); 1118 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_in, X_SIZE, Y_SIZE, 4, 2); 1119 dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_false_rsp_out, X_SIZE, Y_SIZE, 4, 2); 1052 1120 1053 1121 return EXIT_SUCCESS;
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