- Timestamp:
- Mar 26, 2014, 10:49:53 AM (11 years ago)
- Location:
- trunk/platforms/tsar_generic_leti
- Files:
-
- 2 edited
-
top.cpp (modified) (44 diffs)
-
tsar_leti_cluster/caba/source/src/tsar_leti_cluster.cpp (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_leti/top.cpp
r630 r664 1 1 ///////////////////////////////////////////////////////////////////////// 2 // File: top.cpp 2 // File: top.cpp (for tsar_generic_leti) 3 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 … … 33 33 // 34 34 // Each processor receive 4 consecutive IRQ lines from the local XICU. 35 // 35 36 // In all clusters, the MEMC IRQ line (signaling a late write error) 36 37 // is connected to XICU HWI[8] 37 // 38 // The cluster 0 contains two more peripherals: 38 // The cluster (0,0) contains two "internal" peripherals: 39 39 // - one block device controller, whose IRQ is connected to XICU HWI[9]. 40 40 // - one single channel TTY controller, whose IRQ is connected to XICU HWI[10]. … … 43 43 // that must be considered as an extension of this top.cpp file. 44 44 // 45 // Besides the hardware components contained in clusters, externalperipherals45 // Besides the hardware components in clusters, "external" peripherals 46 46 // are connected to an external IO bus (implemented as a vci_local_crossbar): 47 47 // - one disk controller … … 50 50 // - one multi-channel tty controller 51 51 // - one frame buffer controller 52 // - one 16channels iopic controller52 // - one 32 channels iopic controller 53 53 // 54 54 // This IOBUS is connected to the north port of the DIR_CMD 55 // and DIR_RSP routers, in cluster(X_SIZE-1, Y_SIZE- 1).55 // and DIR_RSP routers, in cluster(X_SIZE-1, Y_SIZE-2). 56 56 // For all external peripherals, the hardware interrupts (HWI) are 57 // translated to software interrupts (SWI) by the iopic component: 58 // - IRQ_MNIC_RX[1:0] connected to IOPIC HWI[1:0] 59 // - IRQ_MNIC_TX[1:0] connected to IOPIC HWI[3:2] 60 // - IRQ_CDMA[3:0] connected to IOPIC HWI[7:4] 61 // - IRQ_BDEV connected to IOPIC HWI[9] 62 // - IRQ_MTTY[3:0] connected to IOPIC HWI[15:12] 57 // translated to write interrupts (WTI) by the iopic component: 58 // - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] 59 // - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] 60 // - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] 61 // - IOPIC HWI[8] connected to IRQ_BDEV 62 // - IOPIC HWI[15:9] unused (grounded) 63 // - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]] 64 // - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]] 63 65 //////////////////////////////////////////////////////////////////////////// 64 66 // The following parameters must be defined in the hard_config.h file : … … 68 70 // - Y_SIZE : number of clusters in a column 69 71 // - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4) 70 // - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster ( 8max)71 // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster ( 16max)72 // - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (4 max) 73 // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max) 72 74 // - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max) 73 // - USE_EXT_IO : use external peripherals if non zero74 75 // 75 76 // Some other hardware parameters are not used when compiling the OS, … … 126 127 #include "alloc_elems.h" 127 128 128 /////////////////////////////////////////////////// 129 // OS 130 /////////////////////////////////////////////////// 131 132 #define USE_GIET_VM 0 133 #define USE_GIET_TSAR 1 129 ////////////////////////////////////////////////////////////////////////////////////////// 130 // Parameters depending on the OS and software application 131 // - path to hard_config file 132 // - path to binary code for the RAM loader 133 // - path to disk image for RAMDISK loader 134 // - path to disk image for IOC device 135 ////////////////////////////////////////////////////////////////////////////////////////// 136 137 #define USE_GIET_VM 1 138 #define USE_GIET_TSAR 0 134 139 135 140 #if ( USE_GIET_VM and USE_GIET_TSAR ) … … 139 144 #if ( (not USE_GIET_VM) and (not USE_GIET_TSAR) ) 140 145 #error "You need to specify one OS" 146 #endif 147 148 #if USE_GIET_TSAR 149 #include "../../softs/soft_transpose_giet/hard_config.h" 150 #define BINARY_PATH_FOR_LOADER "../../softs/soft_transpose_giet/bin.soft" 151 #define RAMDISK_PATH_FOR_LOADER "../../softs/soft_transpose_giet/images.raw@0x00800000:" 152 #define DISK_IMAGE_PATH_FOR_IOC "../../softs/soft_transpose_giet/images.raw" 153 #endif 154 155 #if USE_GIET_VM 156 #include "../../../giet_vm/hard_config.h" 157 #define BINARY_PATH_FOR_LOADER "../../softs/tsar_boot/preloader.elf" 158 #define RAMDISK_PATH_FOR_LOADER "../../../giet_vm/hdd/virt_hdd.dmg@0x02000000:" 159 #define DISK_IMAGE_PATH_FOR_IOC "../../../giet_vm/hdd/virt_hdd.dmg" 141 160 #endif 142 161 … … 181 200 #define vci_wrplen_width 1 182 201 183 //////////////////////////////////////////////////////////// 184 // Main Hardware Parameters values 185 //////////////////////i///////////////////////////////////// 186 187 #include "../../softs/soft_transpose_giet/hard_config.h" 188 189 //////////////////////////////////////////////////////////// 202 203 ///////////////////////////////////////////////////////////////////////////////////////// 190 204 // Secondary Hardware Parameters 191 ////////////////////// i/////////////////////////////////////205 ///////////////////////////////////////////////////////////////////////////////////////// 192 206 193 207 #define RESET_ADDRESS 0x0 194 208 209 #define MAX_TTY_CHANNELS 8 210 #define MAX_CMA_CHANNELS 4 211 #define MAX_NIC_CHANNELS 2 212 195 213 #define XRAM_LATENCY 0 214 #define XRAM_SIZE 0x04000000 // 64 Mbytes per cluster 196 215 197 216 #define MEMC_WAYS 16 … … 207 226 #define FBUF_Y_SIZE 128 208 227 209 #define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/images.raw"210 211 228 #define NIC_MAC4 0XBABEF00D 212 229 #define NIC_MAC2 0xBEEF 213 #define NIC_RX_NAME ". ./../softs/soft_hello_giet/fake"214 #define NIC_TX_NAME ". ./../softs/soft_hello_giet/fake"230 #define NIC_RX_NAME "./fake" 231 #define NIC_TX_NAME "./fake" 215 232 216 233 #define NORTH 0 … … 219 236 #define WEST 3 220 237 221 //////////////////////////////////////////////////////////// 222 // Arguments for the SoCLib loader 223 //////////////////////i///////////////////////////////////// 224 225 #define elf_loader "../../softs/soft_transpose_giet/bin.soft" 226 #define ramdisk_loader "../../softs/soft_transpose_giet/images.raw@0x00800000:" 227 228 //////////////////////////////////////////////////////////// 238 /////////////////////////////////////////////////////////////////////////////////////// 229 239 // DEBUG Parameters default values 230 ////////////////////// i/////////////////////////////////////240 /////////////////////////////////////////////////////////////////////////////////////// 231 241 232 242 #define MAX_FROZEN_CYCLES 10000 233 243 234 //////////////////////////////////////////////////////////////////// 244 /////////////////////////////////////////////////////////////////////////////////////// 235 245 // LOCAL TGTID & SRCID definition 236 246 // For all components: global TGTID = global SRCID = cluster_index 237 //////////////////////////////////////////////////////////////////// 238 239 #define MEMC_TGTID 0240 #define XICU_TGTID 1241 #define MTTY_TGTID 2242 #define BDEV_TGTID 3243 #define FBUF_TGTID 4244 #define MNIC_TGTID 5245 #define CDMA_TGTID 6246 #define IOPI_TGTID 7247 248 #define BDEV_SRCID NB_PROCS_MAX249 #define CDMA_SRCID NB_PROCS_MAX + 1250 #define IOPI_SRCID NB_PROCS_MAX + 2251 252 ///////////////////////////////////////////////////////////////////// 247 /////////////////////////////////////////////////////////////////////////////////////// 248 249 #define MEMC_TGTID 0 250 #define XICU_TGTID 1 251 #define MTTY_TGTID 2 252 #define BDEV_TGTID 3 253 #define FBUF_TGTID 4 254 #define MNIC_TGTID 5 255 #define CDMA_TGTID 6 256 #define IOPI_TGTID 7 257 258 #define BDEV_SRCID NB_PROCS_MAX 259 #define CDMA_SRCID NB_PROCS_MAX + 1 260 #define IOPI_SRCID NB_PROCS_MAX + 2 261 262 ////////////////////////////////////////////////////////////////////////////////////// 253 263 // Physical segments definition 254 ///////////////////////////////////////////////////////////////////// 264 ////////////////////////////////////////////////////////////////////////////////////// 255 265 // - 3 segments are replicated in all clusters 256 266 // - 2 segments are replicated in cluster[0,0] & [X_SIZE-1,Y_SIZE-1] 257 // - 4 segments are only in cluster [X_SIZE-1,Y_SIZE ]267 // - 4 segments are only in cluster [X_SIZE-1,Y_SIZE-1] 258 268 // The following values are for segments in cluster 0, 259 269 // and these 32 bits values must be concatenate with the cluster 260 270 // index (on 8 bits) to obtain the 40 bits address. 261 ///////////////////////////////////////////////////////////////////// 262 263 // in cluster [0,0] & [X_SIZE-1,Y_SIZE ]271 ////////////////////////////////////////////////////////////////////////////////////// 272 273 // in cluster [0,0] & [X_SIZE-1,Y_SIZE-1] 264 274 265 275 #define MTTY_BASE 0xF4000000 … … 269 279 #define BDEV_SIZE 0x00001000 // 4 Kbytes 270 280 271 // in cluster [X_SIZE-1,Y_SIZE ]281 // in cluster [X_SIZE-1,Y_SIZE-1] 272 282 273 283 #define FBUF_BASE 0xF3000000 … … 286 296 287 297 #define MEMC_BASE 0x00000000 288 #define MEMC_SIZE 0x01000000 // 16 Mbytes per cluster298 #define MEMC_SIZE XRAM_SIZE 289 299 290 300 #define MCFG_BASE 0xE0000000 … … 336 346 size_t y = trace_memc_id & ((1<<Y_WIDTH)-1); 337 347 338 assert( (x < = X_SIZE) and (y <= Y_SIZE) &&348 assert( (x < X_SIZE) and (y < (Y_SIZE-1)) and 339 349 "MEMCID parameter refers a not valid memory cache"); 340 350 } … … 346 356 size_t x = cluster_xy >> Y_WIDTH; 347 357 size_t y = cluster_xy & ((1<<Y_WIDTH)-1); 348 349 assert( (x <= X_SIZE) and (y <= Y_SIZE) && 358 size_t l = trace_proc_id % NB_PROCS_MAX ; 359 360 assert( (x < X_SIZE) and (y < (Y_SIZE-1)) and l < NB_PROCS_MAX and 350 361 "PROCID parameter refers a not valid processor"); 351 362 } … … 383 394 "The Y_SIZE parameter cannot be larger than 16" ); 384 395 385 assert( (NB_PROCS_MAX <= 8) and396 assert( (NB_PROCS_MAX <= 4) and 386 397 "The NB_PROCS_MAX parameter cannot be larger than 4" ); 387 398 388 assert( (NB_CMA_CHANNELS <= 4) and399 assert( (NB_CMA_CHANNELS <= MAX_CMA_CHANNELS) and 389 400 "The NB_CMA_CHANNELS parameter cannot be larger than 4" ); 390 401 391 assert( (NB_TTY_CHANNELS <= 4) and392 "The NB_TTY_CHANNELS parameter cannot be larger than 4" );393 394 assert( (NB_NIC_CHANNELS <= 2) and402 assert( (NB_TTY_CHANNELS <= MAX_TTY_CHANNELS) and 403 "The NB_TTY_CHANNELS parameter cannot be larger than 8" ); 404 405 assert( (NB_NIC_CHANNELS <= MAX_NIC_CHANNELS) and 395 406 "The NB_NIC_CHANNELS parameter cannot be larger than 2" ); 396 407 … … 415 426 std::cout << " - MAX_CYCLES = " << ncycles << std::endl; 416 427 std::cout << " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl; 417 std::cout << " - SOFT_ FILENAME = " << elf_loader<< std::endl;418 std::cout << " - RAMDISK_FILENAME = " << ramdisk_loader<< std::endl;428 std::cout << " - SOFT_PATH_NAME = " << BINARY_PATH_FOR_LOADER << std::endl; 429 std::cout << " - DISK_IMAGE_PATH = " << DISK_IMAGE_PATH_FOR_IOC << std::endl; 419 430 420 431 std::cout << std::endl; … … 462 473 for (size_t x = 0; x < X_SIZE; x++) 463 474 { 464 for (size_t y = 0; y < Y_SIZE; y++)475 for (size_t y = 0; y < (Y_SIZE-1) ; y++) 465 476 { 466 477 sc_uint<vci_address_width> offset; … … 484 495 } 485 496 486 // segments in cluster(0,0)497 // segments for peripherals in cluster(0,0) 487 498 maptabd.add(Segment("seg_tty0", MTTY_BASE, MTTY_SIZE, 488 499 IntTab(cluster(0,0),MTTY_TGTID), false)); … … 491 502 IntTab(cluster(0,0),BDEV_TGTID), false)); 492 503 493 // segments in cluster_io (X_SIZE-1,Y_SIZE)504 // segments for peripherals in cluster_io (X_SIZE-1,Y_SIZE-1) 494 505 sc_uint<vci_address_width> offset; 495 offset = ((sc_uint<vci_address_width>)cluster(X_SIZE-1,Y_SIZE )) << 32;506 offset = ((sc_uint<vci_address_width>)cluster(X_SIZE-1,Y_SIZE-1)) << 32; 496 507 497 508 maptabd.add(Segment("seg_mtty", MTTY_BASE + offset, MTTY_SIZE, 498 IntTab(cluster(X_SIZE-1, Y_SIZE ),MTTY_TGTID), false));509 IntTab(cluster(X_SIZE-1, Y_SIZE-1),MTTY_TGTID), false)); 499 510 500 511 maptabd.add(Segment("seg_fbuf", FBUF_BASE + offset, FBUF_SIZE, 501 IntTab(cluster(X_SIZE-1, Y_SIZE ),FBUF_TGTID), false));512 IntTab(cluster(X_SIZE-1, Y_SIZE-1),FBUF_TGTID), false)); 502 513 503 514 maptabd.add(Segment("seg_bdev", BDEV_BASE + offset, BDEV_SIZE, 504 IntTab(cluster(X_SIZE-1, Y_SIZE ),BDEV_TGTID), false));515 IntTab(cluster(X_SIZE-1, Y_SIZE-1),BDEV_TGTID), false)); 505 516 506 517 maptabd.add(Segment("seg_mnic", MNIC_BASE + offset, MNIC_SIZE, 507 IntTab(cluster(X_SIZE-1, Y_SIZE ),MNIC_TGTID), false));518 IntTab(cluster(X_SIZE-1, Y_SIZE-1),MNIC_TGTID), false)); 508 519 509 520 maptabd.add(Segment("seg_cdma", CDMA_BASE + offset, CDMA_SIZE, 510 IntTab(cluster(X_SIZE-1, Y_SIZE ),CDMA_TGTID), false));521 IntTab(cluster(X_SIZE-1, Y_SIZE-1),CDMA_TGTID), false)); 511 522 512 523 maptabd.add(Segment("seg_iopi", IOPI_BASE + offset, IOPI_SIZE, 513 IntTab(cluster(X_SIZE-1, Y_SIZE ),IOPI_TGTID), false));524 IntTab(cluster(X_SIZE-1, Y_SIZE-1),IOPI_TGTID), false)); 514 525 515 526 std::cout << maptabd << std::endl; … … 526 537 for (size_t x = 0; x < X_SIZE; x++) 527 538 { 528 for (size_t y = 0; y < Y_SIZE; y++)539 for (size_t y = 0; y < (Y_SIZE-1) ; y++) 529 540 { 530 541 sc_uint<vci_address_width> offset; … … 552 563 sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; 553 564 sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; 554 sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS]; 565 sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS]; 566 // sc_signal<bool> signal_irq_mtty_tx[NB_TTY_CHANNELS]; 555 567 sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS]; 556 568 sc_signal<bool> signal_irq_false; … … 558 570 // Horizontal inter-clusters DSPIN signals 559 571 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc = 560 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE );572 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE-1); 561 573 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec = 562 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE );574 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE-1); 563 575 564 576 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc = 565 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE );577 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE-1); 566 578 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec = 567 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE );579 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE-1); 568 580 569 581 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc = 570 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE-1, Y_SIZE );582 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE-1, Y_SIZE-1); 571 583 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec = 572 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE-1, Y_SIZE );584 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE-1, Y_SIZE-1); 573 585 574 586 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc = 575 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE-1, Y_SIZE );587 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE-1, Y_SIZE-1); 576 588 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec = 577 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE-1, Y_SIZE );589 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE-1, Y_SIZE-1); 578 590 579 591 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc = 580 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE-1, Y_SIZE );592 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE-1, Y_SIZE-1); 581 593 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec = 582 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE-1, Y_SIZE );594 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE-1, Y_SIZE-1); 583 595 584 596 // Vertical inter-clusters DSPIN signals 585 597 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc = 586 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE- 1);598 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-2); 587 599 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec = 588 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE- 1);600 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-2); 589 601 590 602 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc = 591 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE- 1);603 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-2); 592 604 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec = 593 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE- 1);605 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-2); 594 606 595 607 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc = 596 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE- 1);608 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE-2); 597 609 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec = 598 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE- 1);610 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE-2); 599 611 600 612 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc = 601 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE- 1);613 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE-2); 602 614 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec = 603 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE- 1);615 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE-2); 604 616 605 617 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc = 606 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE- 1);618 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE-2); 607 619 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec = 608 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE- 1);620 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE-2); 609 621 610 622 // Mesh boundaries DSPIN signals (Most of those signals are not used...) 611 623 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in = 612 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE , 4);624 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE-1, 4); 613 625 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out = 614 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE , 4);626 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE-1, 4); 615 627 616 628 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in = 617 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE , 4);629 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE-1, 4); 618 630 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out = 619 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE , 4);631 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE-1, 4); 620 632 621 633 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in = 622 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE , 4);634 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE-1, 4); 623 635 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out = 624 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE , 4);636 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE-1, 4); 625 637 626 638 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in = 627 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE , 4);639 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE-1, 4); 628 640 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out = 629 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE , 4);641 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE-1, 4); 630 642 631 643 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in = 632 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE , 4);644 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE-1, 4); 633 645 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out = 634 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE , 4);646 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE-1, 4); 635 647 636 648 // VCI signals for iobus and peripherals … … 658 670 //////////////////////////// 659 671 660 soclib::common::Loader loader( elf_loader, ramdisk_loader ); 672 #if USE_IOC_RDK 673 soclib::common::Loader loader( BINARY_PATH_FOR_LOADER, RAMDISK_PATH_FOR_LOADER ); 674 #else 675 soclib::common::Loader loader( BINARY_PATH_FOR_LOADER ); 676 #endif 661 677 662 678 /////////////////////////// … … 667 683 proc_iss::set_loader( loader ); 668 684 669 //////////////////////////// 670 // Clusters construction671 //////////////////////////// 685 ////////////////////////////////////////////////////////////// 686 // mesh construction: only (X_SIZE) * (Y_SIZE-1) clusters 687 ////////////////////////////////////////////////////////////// 672 688 673 689 TsarLetiCluster<dspin_cmd_width, 674 690 dspin_rsp_width, 675 691 vci_param_int, 676 vci_param_ext>* clusters[X_SIZE][Y_SIZE ];692 vci_param_ext>* clusters[X_SIZE][Y_SIZE-1]; 677 693 678 694 #if USE_OPENMP … … 681 697 #pragma omp for 682 698 #endif 683 for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++)699 for (size_t i = 0; i < (X_SIZE * (Y_SIZE-1)); i++) 684 700 { 685 size_t x = i / Y_SIZE;686 size_t y = i % Y_SIZE;701 size_t x = i / (Y_SIZE-1); 702 size_t y = i % (Y_SIZE-1); 687 703 688 704 #if USE_OPENMP … … 695 711 std::cout << std::endl; 696 712 713 std::ostringstream cluster_name; 714 cluster_name << "cluster_" << std::dec << x << "_" << y; 715 697 716 clusters[x][y] = new TsarLetiCluster<dspin_cmd_width, 698 717 dspin_rsp_width, … … 700 719 vci_param_ext> 701 720 ( 702 "cluster",721 cluster_name.str().c_str(), 703 722 NB_PROCS_MAX, 704 723 x, … … 715 734 MTTY_TGTID, 716 735 BDEV_TGTID, 717 BDEV_IMAGE_NAME,736 DISK_IMAGE_PATH_FOR_IOC, 718 737 MEMC_WAYS, 719 738 MEMC_SETS, … … 742 761 ////////////////////////////////////////////////////////////////// 743 762 // IO bus and external peripherals in cluster[X_SIZE-1,Y_SIZE] 763 // - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC 764 // - 3 local initiators : IOC, CMA, PIC 765 // There is no PROC, no MEMC and no XICU in this cluster, 766 // but the crossbar has (NB_PROCS_MAX + 3) intiators and 767 // 8 targets, in order to use the same SRCID and TGTID space 768 // (same mapping table for the internal components, 769 // and for the external peripherals) 744 770 ////////////////////////////////////////////////////////////////// 745 771 746 size_t cluster_io = cluster(X_SIZE-1, Y_SIZE); 772 std::cout << std::endl; 773 std::cout << " Building IO cluster (external peripherals)" << std::endl; 774 std::cout << std::endl; 775 776 size_t cluster_io = cluster(X_SIZE-1, Y_SIZE-1); 747 777 748 778 //////////// vci_local_crossbar … … 771 801 IntTab(cluster_io, BDEV_SRCID), 772 802 IntTab(cluster_io, BDEV_TGTID), 773 BDEV_IMAGE_NAME,803 DISK_IMAGE_PATH_FOR_IOC, 774 804 512, // block size 775 805 64 ); // burst size … … 820 850 IntTab(cluster_io, IOPI_SRCID), 821 851 IntTab(cluster_io, IOPI_TGTID), 822 16 ); 852 32, 853 20000000 ); 823 854 824 855 ////////////// vci_dspin wrappers … … 909 940 for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) 910 941 { 911 mtty->p_irq[i] (signal_irq_mtty [i]);942 mtty->p_irq[i] (signal_irq_mtty_rx[i]); 912 943 } 913 944 … … 915 946 916 947 // iopic 948 // NB_NIC_CHANNELS <= 2 949 // NB_CMA_CHANNELS <= 4 950 // NB_TTY_CHANNELS <= 8 917 951 iopic->p_clk (signal_clk); 918 952 iopic->p_resetn (signal_resetn); 919 953 iopic->p_vci_target (signal_vci_tgt_iopi); 920 954 iopic->p_vci_initiator (signal_vci_ini_iopi); 921 for ( size_t i=0 ; i< 16; i++)955 for ( size_t i=0 ; i<32 ; i++) 922 956 { 923 957 if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]); … … 926 960 else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false); 927 961 else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]); 928 else if(i < 9) iopic->p_hwi[i] (signal_irq_false); 929 else if(i == 9) iopic->p_hwi[i] (signal_irq_bdev); 930 else if(i < 12) iopic->p_hwi[i] (signal_irq_false); 931 else if(i < 12+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty[i-12]); 962 else if(i < 8) iopic->p_hwi[i] (signal_irq_false); 963 else if(i == 8) iopic->p_hwi[i] (signal_irq_bdev); 964 else if(i < 16) iopic->p_hwi[i] (signal_irq_false); 965 else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]); 966 else if(i < 24) iopic->p_hwi[i] (signal_irq_false); 967 else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_false); 968 // else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_tx[i-24]); 932 969 else iopic->p_hwi[i] (signal_irq_false); 933 970 } 971 972 std::cout << " - IOPIC connected" << std::endl; 934 973 935 974 // vci/dspin wrappers … … 937 976 wi_iobus->p_resetn (signal_resetn); 938 977 wi_iobus->p_vci (signal_vci_cmd_to_noc); 939 wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE- 1][NORTH]);940 wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE- 1][NORTH]);978 wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-2][NORTH]); 979 wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-2][NORTH]); 941 980 942 981 // vci/dspin wrappers … … 944 983 wt_iobus->p_resetn (signal_resetn); 945 984 wt_iobus->p_vci (signal_vci_cmd_from_noc); 946 wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE- 1][NORTH]);947 wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE- 1][NORTH]);985 wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-2][NORTH]); 986 wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-2][NORTH]); 948 987 949 988 // Clock & RESET for clusters 950 989 for (size_t x = 0; x < (X_SIZE); x++) 951 990 { 952 for (size_t y = 0; y < Y_SIZE; y++)991 for (size_t y = 0; y < (Y_SIZE-1); y++) 953 992 { 954 993 clusters[x][y]->p_clk (signal_clk); … … 962 1001 for (size_t x = 0; x < (X_SIZE-1); x++) 963 1002 { 964 for (size_t y = 0; y < Y_SIZE; y++)1003 for (size_t y = 0; y < (Y_SIZE-1); y++) 965 1004 { 966 1005 clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]); … … 994 1033 995 1034 // Inter Clusters vertical connections 996 if (Y_SIZE > 1)997 { 998 for (size_t y = 0; y < (Y_SIZE- 1); y++)1035 if (Y_SIZE > 2) 1036 { 1037 for (size_t y = 0; y < (Y_SIZE-2); y++) 999 1038 { 1000 1039 for (size_t x = 0; x < X_SIZE; x++) … … 1030 1069 1031 1070 // East & West boundary cluster connections 1032 for (size_t y = 0; y < Y_SIZE; y++)1071 for (size_t y = 0; y < (Y_SIZE-1); y++) 1033 1072 { 1034 1073 clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]); … … 1058 1097 } 1059 1098 1099 std::cout << std::endl << "West & East boundaries connections done" << std::endl; 1100 1060 1101 // North & South boundary clusters connections 1061 1102 for (size_t x = 0; x < X_SIZE; x++) … … 1063 1104 clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]); 1064 1105 clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]); 1065 clusters[x][Y_SIZE- 1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]);1066 clusters[x][Y_SIZE- 1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]);1106 clusters[x][Y_SIZE-2]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-2][NORTH]); 1107 clusters[x][Y_SIZE-2]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-2][NORTH]); 1067 1108 1068 1109 clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]); 1069 1110 clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]); 1070 clusters[x][Y_SIZE- 1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]);1071 clusters[x][Y_SIZE- 1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]);1111 clusters[x][Y_SIZE-2]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-2][NORTH]); 1112 clusters[x][Y_SIZE-2]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-2][NORTH]); 1072 1113 1073 1114 clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]); 1074 1115 clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]); 1075 clusters[x][Y_SIZE- 1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]);1076 clusters[x][Y_SIZE- 1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]);1116 clusters[x][Y_SIZE-2]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-2][NORTH]); 1117 clusters[x][Y_SIZE-2]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-2][NORTH]); 1077 1118 1078 1119 clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]); 1079 1120 clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]); 1080 clusters[x][Y_SIZE- 1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]);1081 clusters[x][Y_SIZE- 1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]);1121 clusters[x][Y_SIZE-2]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-2][NORTH]); 1122 clusters[x][Y_SIZE-2]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-2][NORTH]); 1082 1123 1083 1124 clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]); 1084 1125 clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]); 1085 clusters[x][Y_SIZE-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]); 1086 clusters[x][Y_SIZE-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]); 1087 } 1088 1089 std::cout << std::endl << "North, South, West, East connections done" << std::endl; 1126 clusters[x][Y_SIZE-2]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-2][NORTH]); 1127 clusters[x][Y_SIZE-2]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-2][NORTH]); 1128 } 1129 1130 std::cout << std::endl << "North & South boundaries connections done" << std::endl; 1131 1090 1132 std::cout << std::endl; 1091 1133 … … 1102 1144 for (size_t x = 0; x < X_SIZE ; x++) 1103 1145 { 1104 for (size_t y = 0; y < Y_SIZE ; y++)1146 for (size_t y = 0; y < Y_SIZE-1 ; y++) 1105 1147 { 1106 1148 for (size_t face = 0; face < 4; face++) 1107 1149 { 1108 if ( (x != X_SIZE-1) or (y != Y_SIZE- 1) or (face != NORTH) )1150 if ( (x != X_SIZE-1) or (y != Y_SIZE-2) or (face != NORTH) ) 1109 1151 { 1110 1152 signal_dspin_bound_cmd_in [x][y][face].write = false; … … 1137 1179 } 1138 1180 1181 // set default values for VCI signals connected to unused ports on iobus 1182 signal_vci_tgt_memc.rspval = false; 1183 signal_vci_tgt_xicu.rspval = false; 1184 for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) signal_vci_ini_proc[p].cmdval = false; 1185 1139 1186 sc_start(sc_core::sc_time(1, SC_NS)); 1140 1187 signal_resetn = true; … … 1146 1193 } 1147 1194 1148 for (uint64_t n = 1; n < ncycles && !stop_called; n++) 1149 { 1150 // Monitor a specific address for L1 & L2 caches 1151 // clusters[0][0]->proc[0]->cache_monitor(0x0000010000ULL); 1152 // clusters[0][0]->memc->cache_monitor(0x0000030000ULL); 1153 1154 if( (n % 5000000) == 0) 1155 { 1156 1157 if (gettimeofday(&t2, NULL) != 0) 1158 { 1159 perror("gettimeofday"); 1160 return EXIT_FAILURE; 1161 } 1162 1163 ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; 1164 ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; 1165 std::cerr << "platform clock frequency " 1166 << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl; 1167 1168 if (gettimeofday(&t1, NULL) != 0) 1169 { 1170 perror("gettimeofday"); 1171 return EXIT_FAILURE; 1172 } 1173 } 1174 1175 if ( trace_ok and (n > trace_from) ) 1176 { 1177 std::cout << "****************** cycle " << std::dec << n ; 1178 std::cout << " ************************************************" << std::endl; 1179 1180 // trace proc[trace_proc_id] 1181 size_t l = trace_proc_id % NB_PROCS_MAX ; 1182 size_t x = (trace_proc_id / NB_PROCS_MAX) >> Y_WIDTH ; 1183 size_t y = (trace_proc_id / NB_PROCS_MAX) & ((1<<Y_WIDTH) - 1); 1184 1185 std::ostringstream proc_signame; 1186 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 1187 std::ostringstream xicu_signame; 1188 xicu_signame << "[SIG]XICU_" << x << "_" << y ; 1189 1190 clusters[x][y]->proc[l]->print_trace(0x1); 1191 clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); 1192 1193 clusters[x][y]->xicu->print_trace(0); 1194 clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str()); 1195 1196 if ( clusters[x][y]->signal_proc_irq[0].read() ) 1197 std::cout << " IRQ_PROC active in cluster " << cluster(x,y) << std::endl; 1198 1199 if ( signal_irq_bdev.read() ) 1200 std::cout << " IRQ_BDEV in cluster_io active" << std::endl; 1201 1202 // trace memc[trace_memc_id] and xram[trace_memc_id] 1203 x = trace_memc_id >> Y_WIDTH; 1204 y = trace_memc_id & ((1<<Y_WIDTH) - 1); 1205 1206 std::ostringstream smemc; 1207 smemc << "[SIG]MEMC_" << x << "_" << y; 1208 std::ostringstream sxram; 1209 sxram << "[SIG]XRAM_" << x << "_" << y; 1210 1211 clusters[x][y]->memc->print_trace(); 1212 clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); 1213 clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); 1195 // variable used for IRQ trace 1196 bool prev_irq_bdev = false; 1197 bool prev_irq_mtty_rx[8]; 1198 bool prev_irq_proc[16][16][4]; 1199 1200 for( size_t x = 0 ; x<8 ; x++ ) prev_irq_mtty_rx[x] = false; 1201 1202 for( size_t x = 0 ; x<16 ; x++ ) 1203 for( size_t y = 0 ; y<16 ; y++ ) 1204 for( size_t i = 0 ; i<4 ; i++ ) prev_irq_proc[x][y][i] = false; 1205 1206 for (uint64_t n = 1; n < ncycles && !stop_called; n++) 1207 { 1208 // Monitor a specific address for L1 & L2 caches 1209 // clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL); 1210 // clusters[1][1]->memc->cache_monitor(0x110002c078ULL); 1211 1212 // stats display 1213 if( (n % 5000000) == 0) 1214 { 1215 1216 if (gettimeofday(&t2, NULL) != 0) 1217 { 1218 perror("gettimeofday"); 1219 return EXIT_FAILURE; 1220 } 1221 1222 ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; 1223 ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; 1224 std::cerr << "platform clock frequency " 1225 << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl; 1226 1227 if (gettimeofday(&t1, NULL) != 0) 1228 { 1229 perror("gettimeofday"); 1230 return EXIT_FAILURE; 1231 } 1232 } 1233 1234 // trace display 1235 if ( trace_ok and (n > trace_from) ) 1236 { 1237 std::cout << "****************** cycle " << std::dec << n ; 1238 std::cout << " ************************************************" << std::endl; 1239 1240 size_t l = 0; 1241 size_t x = 0; 1242 size_t y = 0; 1243 1244 if ( trace_proc_ok ) 1245 { 1246 l = trace_proc_id % NB_PROCS_MAX ; 1247 x = (trace_proc_id / NB_PROCS_MAX) >> Y_WIDTH ; 1248 y = (trace_proc_id / NB_PROCS_MAX) & ((1<<Y_WIDTH) - 1); 1249 1250 std::ostringstream proc_signame; 1251 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 1252 clusters[x][y]->proc[l]->print_trace(); 1253 clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); 1254 1255 std::ostringstream xicu_signame; 1256 xicu_signame << "[SIG]XICU_" << x << "_" << y ; 1257 clusters[x][y]->xicu->print_trace(0); 1258 clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str()); 1259 } 1260 1261 if ( trace_memc_ok ) 1262 { 1263 x = trace_memc_id >> Y_WIDTH; 1264 y = trace_memc_id & ((1<<Y_WIDTH) - 1); 1265 1266 std::ostringstream smemc; 1267 smemc << "[SIG]MEMC_" << x << "_" << y; 1268 std::ostringstream sxram; 1269 sxram << "[SIG]XRAM_" << x << "_" << y; 1270 1271 clusters[x][y]->memc->print_trace(); 1272 clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); 1273 clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); 1274 } 1275 1276 // trace coherence signals 1277 // clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]"); 1278 // clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]"); 1279 // clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]"); 1280 // clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]"); 1281 1282 // clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]"); 1283 // clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]"); 1284 // clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]"); 1285 // clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]"); 1286 1287 // trace xbar(s) m2p 1288 // clusters[0][0]->xbar_m2p->print_trace(); 1289 // clusters[1][0]->xbar_m2p->print_trace(); 1290 // clusters[0][1]->xbar_m2p->print_trace(); 1291 // clusters[1][1]->xbar_m2p->print_trace(); 1214 1292 1215 // trace coherence signals 1216 // clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]"); 1217 // clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]"); 1218 // clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]"); 1219 // clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]"); 1220 1221 // clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]"); 1222 // clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]"); 1223 // clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]"); 1224 // clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]"); 1225 1226 // trace xbar(s) m2p 1227 // clusters[0][0]->xbar_m2p->print_trace(); 1228 // clusters[1][0]->xbar_m2p->print_trace(); 1229 // clusters[0][1]->xbar_m2p->print_trace(); 1230 // clusters[1][1]->xbar_m2p->print_trace(); 1293 // trace router(s) m2p 1294 // clusters[0][0]->router_m2p->print_trace(); 1295 // clusters[1][0]->router_m2p->print_trace(); 1296 // clusters[0][1]->router_m2p->print_trace(); 1297 // clusters[1][1]->router_m2p->print_trace(); 1231 1298 1232 // trace router(s) m2p 1233 // clusters[0][0]->router_m2p->print_trace(); 1234 // clusters[1][0]->router_m2p->print_trace(); 1235 // clusters[0][1]->router_m2p->print_trace(); 1236 // clusters[1][1]->router_m2p->print_trace(); 1299 // trace external ioc 1300 bdev->print_trace(); 1301 signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); 1302 signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 1303 1304 // trace external iopic 1305 iopic->print_trace(); 1306 signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); 1307 signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); 1308 1309 // trace internal tty 1310 // clusters[0][0]->mtty->print_trace(); 1311 // clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY"); 1312 1313 } // end trace 1314 1315 if (0) 1316 { 1317 // trace BDV interrupts events 1318 if ( signal_irq_bdev.read() != prev_irq_bdev ) 1319 { 1320 prev_irq_bdev = signal_irq_bdev.read(); 1321 std::cout << std::dec << "@@@ IRQ_BDEV = " << signal_irq_bdev.read() 1322 << " at cycle " << n << std::endl; 1323 } 1237 1324 1238 // trace external peripherals 1239 bdev->print_trace(); 1240 signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); 1241 signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 1242 1243 iopic->print_trace(); 1244 signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); 1245 signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); 1246 1247 clusters[0][0]->mtty->print_trace(); 1248 clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY"); 1249 } // end trace 1250 1251 sc_start(sc_core::sc_time(1, SC_NS)); 1252 } 1253 1254 1255 // Free memory 1256 for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) 1257 { 1258 size_t x = i / Y_SIZE; 1259 size_t y = i % Y_SIZE; 1260 delete clusters[x][y]; 1261 } 1262 1263 return EXIT_SUCCESS; 1325 // trace TTY interrupts events 1326 for ( size_t x = 0 ; x < 8 ; x++ ) 1327 { 1328 if ( signal_irq_mtty_rx[x].read() != prev_irq_mtty_rx[x] ) 1329 { 1330 prev_irq_mtty_rx[x] = signal_irq_mtty_rx[x].read(); 1331 std::cout << std::dec << "@@@ IRQ_MTTY["<<x<<"] = " 1332 << signal_irq_mtty_rx[x].read() 1333 << " at cycle " << n << std::endl; 1334 } 1335 } 1336 1337 // trace processor interrupts events 1338 for ( size_t x = 0 ; x < 2 ; x++ ) 1339 for ( size_t y = 0 ; y < 2 ; y++ ) 1340 for ( size_t i = 0 ; i < 4 ; i++ ) 1341 { 1342 if ( clusters[x][y]->signal_proc_irq[i] != prev_irq_proc[x][y][i] ) 1343 { 1344 prev_irq_proc[x][y][i] = clusters[x][y]->signal_proc_irq[i]; 1345 std::cout << std::dec << "@@@ IRQ_PROC["<<x<<","<<y<<","<<i<<"] = " 1346 << clusters[x][y]->signal_proc_irq[i] 1347 << " at cycle " << n << std::endl; 1348 } 1349 } 1350 1351 // trace VCI transactions on IOPIC and XCU(0,0) 1352 signal_vci_tgt_iopi.print_trace("@@@ IOPI_TGT"); 1353 signal_vci_ini_iopi.print_trace("@@@ IOPI_INI"); 1354 clusters[0][0]->signal_vci_tgt_xicu.print_trace("@@@ XCU_0_0"); 1355 } 1356 1357 sc_start(sc_core::sc_time(1, SC_NS)); 1358 } 1359 // Free memory 1360 for (size_t i = 0 ; i < (X_SIZE * (Y_SIZE-1)) ; i++) 1361 { 1362 size_t x = i / (Y_SIZE-1); 1363 size_t y = i % (Y_SIZE-1); 1364 delete clusters[x][y]; 1365 } 1366 1367 return EXIT_SUCCESS; 1264 1368 } 1265 1369 -
trunk/platforms/tsar_generic_leti/tsar_leti_cluster/caba/source/src/tsar_leti_cluster.cpp
r628 r664 312 312 4,4); // input & output fifo depths 313 313 314 // backup BDV and TTY peripherals in cluster(0,0) 314 315 if ((x_id == 0) and (y_id == 0)) 315 316 { … … 341 342 IntTab(cluster_xy, tgtid_mtty), 342 343 mtd, 343 " tty_0_0", NULL );344 "backup", NULL ); 344 345 345 346 wt_mtty = new VciDspinTargetWrapper<vci_param_int,
Note: See TracChangeset
for help on using the changeset viewer.
