Changeset 675 for branches/MESI/modules/vci_cc_vcache_wrapper/caba
- Timestamp:
- Apr 11, 2014, 3:09:22 PM (11 years ago)
- Location:
- branches/MESI/modules/vci_cc_vcache_wrapper/caba/source
- Files:
-
- 2 edited
-
include/vci_cc_vcache_wrapper.h (modified) (3 diffs)
-
src/vci_cc_vcache_wrapper.cpp (modified) (19 diffs)
Legend:
- Unmodified
- Added
- Removed
-
branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r670 r675 133 133 DCACHE_MISS_DATA_UPDT, 134 134 DCACHE_MISS_DIR_UPDT, 135 DCACHE_MISS_BACKOFF, 135 136 // handling processor unc, ll and sc requests 136 137 DCACHE_UNC_WAIT, … … 470 471 sc_signal<bool> r_dcache_miss_updt; // cc updt request matching a miss 471 472 sc_signal<bool> r_dcache_miss_clack; // waiting for a cleanup acknowledge 473 474 475 sc_signal<size_t> r_dcache_count_backoff; // selected set for cache update 476 sc_signal<size_t> r_dcache_count_begin; // selected set for cache update 472 477 473 478 // handling coherence requests … … 620 625 sc_signal<size_t> r_cc_receive_dcache_srcid; // cc_receive to dcache set 621 626 sc_signal<size_t> r_cc_receive_brdcast; // is brdcast 627 sc_signal<bool> r_cc_receive_dcache_is_shared; // the line state in memcache 622 628 623 629 /////////////////////////////////// -
branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r674 r675 106 106 "DCACHE_MISS_DATA_UPDT", 107 107 "DCACHE_MISS_DIR_UPDT", 108 "DCACHE_MISS_BACKOFF", 108 109 109 110 "DCACHE_UNC_WAIT", … … 385 386 r_vci_rsp_data_error("r_vci_rsp_data_error"), 386 387 r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth 387 r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth388 r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 16), // 2 words depth 388 389 // r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth 389 390 r_cc_send_data_fifo("r_cc_send_data_fifo", 16), … … 872 873 r_dcache_xtn_flush_data_cpt = 0; 873 874 r_dcache_cc_inval_data_cpt = 0; 875 r_dcache_count_backoff = 0; 876 r_dcache_count_begin = 0; 874 877 875 878 r_dcache_cleanup_victim_req = false; … … 2295 2298 { 2296 2299 2300 //#if 1 2301 // // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE 2302 // if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) { 2303 // std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl; 2304 // raise(SIGINT); 2305 // } 2306 //#endif 2307 2297 2308 if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated 2298 2309 { … … 2439 2450 } 2440 2451 // coherence request (from CC_RECEIVE FSM) 2441 else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_miss_updt.read())2452 else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) 2442 2453 { 2443 2454 r_dcache_fsm = DCACHE_CC_CHECK; … … 2449 2460 else if ( m_dreq.valid ) 2450 2461 { 2451 r_dcache_miss_updt = false;2452 2462 // register processor request and DCACHE response 2453 2463 r_dcache_save_vaddr = m_dreq.addr; … … 3121 3131 3122 3132 // coherence request (from CC_RECEIVE FSM) 3123 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_miss_updt.read())3133 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) 3124 3134 { 3125 3135 r_dcache_fsm = DCACHE_CC_CHECK; … … 3128 3138 } 3129 3139 3130 r_dcache_miss_updt = false;3131 3140 uint32_t entry; 3132 3141 size_t way; … … 3437 3446 3438 3447 // coherence request (from CC_RECEIVE FSM) 3439 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_miss_updt.read())3448 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) 3440 3449 { 3441 3450 r_dcache_fsm = DCACHE_CC_CHECK; … … 3444 3453 } 3445 3454 3446 r_dcache_miss_updt = false;3447 3455 uint32_t pte_flags = 0; 3448 3456 uint32_t pte_ppn = 0; … … 4747 4755 4748 4756 // coherence request (from CC_RECEIVE FSM) 4749 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() and not r_dcache_miss_ updt.read())4757 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() and not r_dcache_miss_inval.read() and not r_dcache_miss_updt.read()) 4750 4758 { 4751 4759 r_dcache_fsm = DCACHE_CC_CHECK; … … 4754 4762 } 4755 4763 4756 if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge4764 if ( not r_dcache_miss_clack.read() and not r_dcache_cc_send_req.read()) // waiting cleanup acknowledge 4757 4765 { 4758 4766 if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup 4759 4767 { 4760 if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent 4761 { 4762 r_dcache_miss_inval = false; 4763 // request cleanup 4764 r_dcache_cc_send_req = true; 4765 r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); 4766 r_dcache_cc_send_way = r_dcache_miss_way.read(); 4767 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4768 r_dcache_cc_line_dirty = false; // in case of miss inval, the cleanup is not with data. 4769 r_dcache_cc_line_no_shared = r_dcache_rsp_state.read(); // the miss read rsp contents the state of this line 4768 r_dcache_miss_inval = false; 4769 // request cleanup 4770 r_dcache_cc_send_req = true; 4771 r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); 4772 r_dcache_cc_send_way = r_dcache_miss_way.read(); 4773 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4774 r_dcache_cc_line_dirty = false; // in case of miss inval, the cleanup is not with data. 4775 r_dcache_cc_line_no_shared = r_dcache_rsp_state.read(); // the miss read rsp contents the state of this line 4770 4776 4771 4777 #ifdef INSTRUMENTATION 4772 4778 m_cpt_dcache_dir_write++; 4773 4779 #endif 4774 r_dcache.write_dir( r_dcache_save_paddr.read(), 4775 r_dcache_miss_way.read(), 4776 r_dcache_miss_set.read(), 4777 CACHE_SLOT_STATE_ZOMBI ); 4780 r_dcache.write_dir( r_dcache_save_paddr.read(), 4781 r_dcache_miss_way.read(), 4782 r_dcache_miss_set.read(), 4783 CACHE_SLOT_STATE_ZOMBI ); 4784 4778 4785 #if DEBUG_DCACHE 4779 4786 if ( m_debug_activated ) … … 4784 4791 << " / SET = " << r_dcache_miss_set.read() << std::endl; 4785 4792 #endif 4793 4794 if( not r_dcache_miss_updt.read()) 4795 { 4796 r_dcache_fsm = DCACHE_MISS_BACKOFF; 4797 r_dcache_count_backoff = r_dcache_count_backoff.read() + 1; 4798 r_dcache_count_begin = 0; 4786 4799 } 4787 else 4788 break; 4800 break; 4801 } 4802 else if( r_dcache_miss_updt.read()) 4803 { 4804 r_dcache_miss_updt = false; 4805 r_cc_receive_dcache_req = false; 4806 r_dcache_cc_send_req = true; 4807 r_dcache_cc_send_multi_ack_miss = true; 4808 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4809 r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); 4810 r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; 4811 4812 r_dcache_fsm = DCACHE_MISS_BACKOFF; 4813 r_dcache_count_backoff = r_dcache_count_backoff.read() + 1; 4814 r_dcache_count_begin = 0; 4789 4815 } 4790 4816 else // switch slot to VALID state … … 4794 4820 m_cpt_dcache_dir_write++; 4795 4821 #endif 4796 4822 r_dcache_count_backoff = 0; 4797 4823 size_t way = r_dcache_miss_way.read(); 4798 4824 size_t set = r_dcache_miss_set.read(); … … 4822 4848 #endif 4823 4849 // reset directory extension 4824 4825 } 4850 if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; 4851 else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; 4852 else r_dcache_fsm = DCACHE_IDLE; 4853 } 4854 } 4855 break; 4856 } 4857 ///////////////////// 4858 case DCACHE_MISS_BACKOFF: 4859 { 4860 size_t count_max = r_dcache_count_backoff.read() << 4; 4861 r_dcache_count_begin = r_dcache_count_begin.read() + 1; 4862 if(r_dcache_count_begin.read() == count_max) 4863 { 4826 4864 if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; 4827 4865 else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; 4828 4866 else r_dcache_fsm = DCACHE_IDLE; 4829 4867 } 4830 break; 4831 } 4868 break; 4869 #if DEBUG_DCACHE 4870 if ( m_debug_activated ) 4871 std::cout << " <PROC " << name() 4872 << " DCACHE_MISS_BACKOFF> operation back off" 4873 << std::endl; 4874 #endif 4875 4876 } 4877 4832 4878 ///////////////////// 4833 4879 case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read … … 5245 5291 { 5246 5292 5247 if(r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST and r_dcache_read_for_modify.read() and 5248 r_cc_receive_dcache_srcid.read() == m_srcid and (r_dcache_miss_type.read() == PROC_MISS)) 5249 { 5293 if(r_dcache_read_for_modify.read() and(r_dcache_miss_type.read() == PROC_MISS) and (r_cc_receive_dcache_type.read() != CC_TYPE_UPDT) and (state == CACHE_SLOT_STATE_SHARED)) 5294 { 5295 r_dcache_fsm = DCACHE_CC_INVAL; 5296 } 5297 else if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) 5298 { 5299 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5300 r_dcache_miss_updt = true; 5301 r_dcache_miss_inval = true; 5302 } 5303 else 5304 { 5305 r_dcache_miss_inval = true; 5250 5306 r_cc_receive_dcache_req = false; 5251 5307 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5252 }5253 else if(r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST and5254 r_dcache_read_for_modify.read() and5255 r_cc_receive_dcache_srcid.read() != m_srcid and5256 (r_dcache_miss_type.read() == PROC_MISS) and5257 (state == CACHE_SLOT_STATE_SHARED))5258 {5259 r_dcache_fsm = DCACHE_CC_INVAL;5260 }5261 else if(r_cc_receive_dcache_type.read() == CC_TYPE_INVAL and r_dcache_read_for_modify.read() and5262 (r_dcache_miss_type.read() == PROC_MISS) and5263 (state == CACHE_SLOT_STATE_SHARED))5264 {5265 r_dcache_fsm = DCACHE_CC_INVAL;5266 }5267 else5268 {5269 r_dcache_miss_inval = false;5270 r_dcache_miss_updt = true;5271 r_dcache_fsm = r_dcache_fsm_cc_save.read();5272 5308 } 5273 5309 // signaling matching … … 5622 5658 } // end switch r_dcache_fsm 5623 5659 5624 //if(r_dcache_miss_updt.read())5625 //std::cout << " <PROC " << name()5626 // << " miss updt " << r_dcache_miss_updt.read() << std::endl;5627 5628 //std::cout << " <PROC " << name()5629 // << " get cache state " << r_dcache.get_cache_state(2,0) << std::endl;5630 5631 5660 ///////////////// llsc update /////////////////////////////////////////////////////// 5632 5661 if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1; … … 6267 6296 r_cc_receive_dcache_srcid = DspinDhccpParam::dspin_get(receive_data, 6268 6297 DspinDhccpParam::BROADCAST_SRCID); 6298 6299 r_cc_receive_dcache_inval_is_config = DspinDhccpParam::dspin_get(receive_data, 6300 DspinDhccpParam::BRDCAST_IS_CONFIG); 6301 6302 r_cc_receive_dcache_is_shared = DspinDhccpParam::dspin_get(receive_data, 6303 DspinDhccpParam::BRDCAST_IS_SHARED); 6304 6269 6305 r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE; 6270 6306 } … … 6316 6352 r_cc_receive_dcache_inval_is_config = DspinDhccpParam::dspin_get(receive_data, 6317 6353 DspinDhccpParam::MULTI_INVAL_IS_CONFIG); 6354 6355 r_cc_receive_dcache_is_shared = DspinDhccpParam::dspin_get(receive_data, 6356 DspinDhccpParam::MULTI_INVAL_IS_SHARED); 6318 6357 } 6319 6358 break;
Note: See TracChangeset
for help on using the changeset viewer.
