Changeset 677 for branches/MESI/modules/vci_cc_vcache_wrapper/caba
- Timestamp:
- Apr 14, 2014, 2:15:01 PM (11 years ago)
- File:
-
- 1 edited
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branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r675 r677 2298 2298 { 2299 2299 2300 //#if 12301 //// @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE2302 //if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) {2303 //std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl;2304 //raise(SIGINT);2305 //}2306 //#endif2300 #if 1 2301 // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE 2302 if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) { 2303 std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl; 2304 raise(SIGINT); 2305 } 2306 #endif 2307 2307 2308 2308 if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated … … 4616 4616 4617 4617 // coherence request (from CC_RECEIVE FSM) 4618 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() and not r_dcache_miss_updt.read())4618 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() ) 4619 4619 { 4620 4620 r_dcache_fsm = DCACHE_CC_CHECK; … … 4755 4755 4756 4756 // coherence request (from CC_RECEIVE FSM) 4757 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() and not r_dcache_miss_inval.read() and not r_dcache_miss_updt.read())4757 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() ) 4758 4758 { 4759 4759 r_dcache_fsm = DCACHE_CC_CHECK; … … 4762 4762 } 4763 4763 4764 if ( not r_dcache_miss_clack.read() and not r_dcache_cc_send_req.read()) // waiting cleanup acknowledge4764 if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge 4765 4765 { 4766 4766 if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup 4767 4767 { 4768 r_dcache_miss_inval = false; 4769 // request cleanup 4770 r_dcache_cc_send_req = true; 4771 r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); 4772 r_dcache_cc_send_way = r_dcache_miss_way.read(); 4773 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4774 r_dcache_cc_line_dirty = false; // in case of miss inval, the cleanup is not with data. 4775 r_dcache_cc_line_no_shared = r_dcache_rsp_state.read(); // the miss read rsp contents the state of this line 4768 if(not r_dcache_cc_send_req.read()) 4769 { 4770 r_dcache_miss_inval = false; 4771 // request cleanup 4772 r_dcache_cc_send_req = true; 4773 r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); 4774 r_dcache_cc_send_way = r_dcache_miss_way.read(); 4775 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4776 r_dcache_cc_line_dirty = false; // in case of miss inval, the cleanup is not with data. 4777 r_dcache_cc_line_no_shared = r_dcache_rsp_state.read(); // the miss read rsp contents the state of this line 4776 4778 4777 4779 #ifdef INSTRUMENTATION 4778 4780 m_cpt_dcache_dir_write++; 4779 4781 #endif 4780 r_dcache.write_dir( r_dcache_save_paddr.read(),4781 r_dcache_miss_way.read(),4782 r_dcache_miss_set.read(),4783 CACHE_SLOT_STATE_ZOMBI );4782 r_dcache.write_dir( r_dcache_save_paddr.read(), 4783 r_dcache_miss_way.read(), 4784 r_dcache_miss_set.read(), 4785 CACHE_SLOT_STATE_ZOMBI ); 4784 4786 4785 4787 #if DEBUG_DCACHE … … 4792 4794 #endif 4793 4795 4794 if( not r_dcache_miss_updt.read())4795 {4796 4796 r_dcache_fsm = DCACHE_MISS_BACKOFF; 4797 4797 r_dcache_count_backoff = r_dcache_count_backoff.read() + 1; 4798 4798 r_dcache_count_begin = 0; 4799 4799 } 4800 break; 4801 } 4802 else if( r_dcache_miss_updt.read()) 4803 { 4804 r_dcache_miss_updt = false; 4805 r_cc_receive_dcache_req = false; 4806 r_dcache_cc_send_req = true; 4807 r_dcache_cc_send_multi_ack_miss = true; 4808 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4809 r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); 4810 r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; 4811 4812 r_dcache_fsm = DCACHE_MISS_BACKOFF; 4813 r_dcache_count_backoff = r_dcache_count_backoff.read() + 1; 4814 r_dcache_count_begin = 0; 4800 else 4801 { 4802 break; 4803 } 4815 4804 } 4816 4805 else // switch slot to VALID state … … 5293 5282 if(r_dcache_read_for_modify.read() and(r_dcache_miss_type.read() == PROC_MISS) and (r_cc_receive_dcache_type.read() != CC_TYPE_UPDT) and (state == CACHE_SLOT_STATE_SHARED)) 5294 5283 { 5295 r_dcache_fsm = DCACHE_CC_INVAL; 5284 r_dcache_miss_clack = true; 5285 r_dcache_fsm = DCACHE_CC_INVAL; 5296 5286 } 5297 5287 else if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) 5298 5288 { 5299 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5300 r_dcache_miss_updt = true; 5289 assert((state == CACHE_SLOT_STATE_INVALID) or (state == CACHE_SLOT_STATE_ZOMBI) && " CC_UPDT WITH A NO INVALID STATE"); 5290 5291 r_dcache_cc_send_multi_ack_miss = true; 5301 5292 r_dcache_miss_inval = true; 5293 r_dcache_fsm = DCACHE_CC_UPDT; 5302 5294 } 5303 5295 else … … 5389 5381 r_dcache_cc_send_multi_ack_miss = false; 5390 5382 } 5391 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL or r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit inval5383 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval 5392 5384 { 5393 5385 r_dcache_fsm = DCACHE_CC_INVAL; … … 6327 6319 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, 6328 6320 DspinDhccpParam::BROADCAST_NLINE); 6329 r_cc_receive_dcache_type = CC_TYPE_ BRDCAST;6321 r_cc_receive_dcache_type = CC_TYPE_INVAL; 6330 6322 // request icache to handle the BROADCAST 6331 6323 r_cc_receive_icache_req = true;
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