Changeset 680 for branches/MESI/modules/vci_cc_vcache_wrapper

Timestamp:

Apr 17, 2014, 11:12:35 AM (11 years ago)

Author:

haoliu

Message:

MESI Bug fixed

File:

• branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (6 diffs)

branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -388 +388 @@
       r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 16),       // 2 words depth
 //      r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2),    // 2 words depth
-      r_cc_send_data_fifo("r_cc_send_data_fifo", 16),
+      r_cc_send_data_fifo("r_cc_send_data_fifo", 2),
 
       r_cc_send_fsm("r_cc_send_fsm"),
@@ -2298 +2298 @@
         {
 
-#if 1
-            // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE
-            if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) {
-                std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl;
-                raise(SIGINT);
-            }
-#endif
+//#if 1
+//            // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE
+//            if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) {
+//                std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl;
+//                raise(SIGINT);
+//            }
+//#endif
 
             if ( r_mmu_mode.read() & DATA_TLB_MASK )  // DTLB activated
@@ -5279 +5279 @@
           ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)))
         {
-
-            if(r_dcache_read_for_modify.read() and(r_dcache_miss_type.read() == PROC_MISS) and (r_cc_receive_dcache_type.read() != CC_TYPE_UPDT) and (state == CACHE_SLOT_STATE_SHARED))
+            
+            if(r_dcache_read_for_modify.read() and(r_dcache_miss_type.read() == PROC_MISS) and 
+              (r_cc_receive_dcache_type.read() != CC_TYPE_UPDT) and (state == CACHE_SLOT_STATE_SHARED))
             {
                 r_dcache_miss_clack = true;
                 r_dcache_fsm        = DCACHE_CC_INVAL;
             }
+            else if(r_dcache_read_for_modify.read() and (r_dcache_miss_type.read() == PROC_MISS) and 
+                   (r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) and (state == CACHE_SLOT_STATE_INVALID) and
+                   (r_cc_receive_dcache_srcid.read() == m_srcid))
+            {
+                r_cc_receive_dcache_req = false;
+                r_dcache_fsm            = r_dcache_fsm_cc_save.read();
+            }   
             else if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
             {
@@ -5344 +5352 @@
     std::cout << "  <PROC " << name()
               << " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
+              << " state =" << state
+              << " r_receive_srcid = " << std::hex << r_cc_receive_dcache_srcid.read()
+              << " m_proc_id = " << std::hex << m_proc_id
               << " PADDR = " << std::hex << paddr << std::endl;
 }
@@ -5381 +5392 @@
                 r_dcache_cc_send_multi_ack_miss = false;
             }
-            else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval
+            else if ( r_cc_receive_dcache_type.read() != CC_TYPE_UPDT ) // hit inval
             {
                 r_dcache_fsm           = DCACHE_CC_INVAL;
@@ -6319 +6330 @@
                 r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,
                                              DspinDhccpParam::BROADCAST_NLINE);
-                r_cc_receive_dcache_type = CC_TYPE_INVAL;
+                r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
                 // request icache to handle the BROADCAST
                 r_cc_receive_icache_req = true;