Changeset 682 for branches/MESI/modules/vci_cc_vcache_wrapper
- Timestamp:
- Apr 23, 2014, 4:45:19 PM (11 years ago)
- File:
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- 1 edited
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branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r680 r682 1297 1297 // we request a VCI transaction 1298 1298 r_icache_fsm = ICACHE_MISS_SELECT; 1299 #if DEBUG_ICACHE 1300 if ( m_debug_activated or m_ireq.addr == 0x11020 ) 1301 std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache" 1302 << " : PADDR = " << std::hex << paddr << std::endl; 1303 #endif 1304 r_icache_miss_req = true; 1299 r_icache_miss_req = true; 1305 1300 } 1306 1301 else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup … … 2832 2827 m_drsp.rdata = cache_rdata; 2833 2828 #if DEBUG_DCACHE 2834 if ( m_debug_activated or m_drsp.rdata == 0x11020)2829 if ( m_debug_activated ) 2835 2830 std::cout << " <PROC " << name() << " DCACHE_IDLE>" 2836 2831 << " READ HIT in dcache" … … 2978 2973 } 2979 2974 #if DEBUG_DCACHE 2980 if ( m_debug_activated or m_dreq.wdata == 0x11020)2975 if ( m_debug_activated ) 2981 2976 std::cout << " <PROC " << name() << " DCACHE_IDLE>" 2982 2977 << " WRITE REQ "
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