Changeset 680 for branches/MESI/modules/vci_mem_cache/caba/source/include
- Timestamp:
- Apr 17, 2014, 11:12:35 AM (11 years ago)
- Location:
- branches/MESI/modules/vci_mem_cache/caba/source/include
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/MESI/modules/vci_mem_cache/caba/source/include/update_tab.h
r677 r680 27 27 addr_t nline; // The identifier of the cache line 28 28 size_t count; // The number of acknowledge responses to receive 29 bool is_change; // multi ack miss req sends this bit to 1 29 bool type; // for a command read or write 30 bool is_changed; // multi ack miss req sends this bit to 1 30 31 31 32 UpdateTabEntry() … … 41 42 nline = 0; 42 43 count = 0; 43 is_change = 0; 44 type = 0; 45 is_changed = 0; 44 46 } 45 47 … … 54 56 addr_t i_nline, 55 57 size_t i_count, 56 size_t i_is_change) 58 bool i_type, 59 bool i_is_changed) 57 60 { 58 61 valid = i_valid; … … 66 69 nline = i_nline; 67 70 count = i_count; 68 is_change = i_is_change; 71 type = i_type; 72 is_changed = i_is_changed; 69 73 } 70 74 … … 81 85 nline = source.nline; 82 86 count = source.count; 83 is_change = source.is_change; 87 type = source.type; 88 is_changed = source.is_changed; 84 89 } 85 90 … … 99 104 nline = 0; 100 105 count = 0; 101 is_change = 0; 106 type = 0; 107 is_changed = 0; 102 108 } 103 109 … … 119 125 nline = source.nline; 120 126 count = source.count; 121 is_change = source.is_change; 127 type = source.type; 128 is_changed = source.is_changed; 122 129 } 123 130 … … 136 143 << " / trdid = " << trdid 137 144 << " / pktid = " << pktid 145 << " / type = " << type 146 << " / is_changed = " << is_changed 138 147 << " / nline = " << nline << std::endl; 139 148 } … … 227 236 const addr_t nline, 228 237 const size_t count, 238 const bool type, 229 239 size_t &index, 230 const bool is_change =false)240 const bool is_changed=false) 231 241 { 232 242 for ( size_t i=0 ; i<size_tab ; i++ ) … … 244 254 tab[i].nline = (addr_t) nline; 245 255 tab[i].count = (size_t) count; 246 tab[i].is_change = is_change; 256 tab[i].type = type; 257 tab[i].is_changed = is_changed; 247 258 index = i; 248 259 return true; … … 464 475 { 465 476 assert(index<size_tab && "Bad Update Tab Entry"); 466 tab[index].is_change = true; 467 } 468 469 size_t is_change(const size_t index) 470 { 471 assert(index<size_tab && "Bad Update Tab Entry"); 472 return tab[index].is_change; 477 tab[index].is_changed = true; 478 } 479 480 bool is_changed(const size_t index) 481 { 482 assert(index<size_tab && "Bad Update Tab Entry"); 483 return tab[index].is_changed; 484 } 485 486 bool is_read(const size_t index) 487 { 488 assert(index<size_tab && "Bad Update Tab Entry"); 489 return tab[index].type; 473 490 } 474 491 }; -
branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r677 r680 1024 1024 sc_signal<size_t> r_cleanup_locked_index; // ivt index 1025 1025 sc_signal<bool> r_cleanup_locked_is_updt; 1026 sc_signal<bool> r_cleanup_locked_is_change; 1026 sc_signal<bool> r_cleanup_locked_is_changed; 1027 sc_signal<bool> r_cleanup_locked_is_read; 1027 1028 1028 1029 sc_signal<size_t> r_cleanup_miss_srcid; // srcid of write rsp
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