Changeset 677 for branches/MESI/modules/vci_mem_cache/caba/source/include
- Timestamp:
- Apr 14, 2014, 2:15:01 PM (11 years ago)
- Location:
- branches/MESI/modules/vci_mem_cache/caba/source/include
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/MESI/modules/vci_mem_cache/caba/source/include/update_tab.h
r670 r677 27 27 addr_t nline; // The identifier of the cache line 28 28 size_t count; // The number of acknowledge responses to receive 29 bool is_change; // multi ack miss req sends this bit to 1 29 30 30 31 UpdateTabEntry() 31 32 { 32 valid = false; 33 update = false; 34 brdcast = false; 35 rsp = false; 36 ack = false; 37 srcid = 0; 38 trdid = 0; 39 pktid = 0; 40 nline = 0; 41 count = 0; 33 valid = false; 34 update = false; 35 brdcast = false; 36 rsp = false; 37 ack = false; 38 srcid = 0; 39 trdid = 0; 40 pktid = 0; 41 nline = 0; 42 count = 0; 43 is_change = 0; 42 44 } 43 45 … … 51 53 size_t i_pktid, 52 54 addr_t i_nline, 53 size_t i_count) 54 { 55 valid = i_valid; 56 update = i_update; 57 brdcast = i_brdcast; 58 rsp = i_rsp; 59 ack = i_ack; 60 srcid = i_srcid; 61 trdid = i_trdid; 62 pktid = i_pktid; 63 nline = i_nline; 64 count = i_count; 55 size_t i_count, 56 size_t i_is_change) 57 { 58 valid = i_valid; 59 update = i_update; 60 brdcast = i_brdcast; 61 rsp = i_rsp; 62 ack = i_ack; 63 srcid = i_srcid; 64 trdid = i_trdid; 65 pktid = i_pktid; 66 nline = i_nline; 67 count = i_count; 68 is_change = i_is_change; 65 69 } 66 70 67 71 UpdateTabEntry(const UpdateTabEntry &source) 68 72 { 69 valid = source.valid; 70 update = source.update; 71 brdcast = source.brdcast; 72 rsp = source.rsp; 73 ack = source.ack; 74 srcid = source.srcid; 75 trdid = source.trdid; 76 pktid = source.pktid; 77 nline = source.nline; 78 count = source.count; 73 valid = source.valid; 74 update = source.update; 75 brdcast = source.brdcast; 76 rsp = source.rsp; 77 ack = source.ack; 78 srcid = source.srcid; 79 trdid = source.trdid; 80 pktid = source.pktid; 81 nline = source.nline; 82 count = source.count; 83 is_change = source.is_change; 79 84 } 80 85 … … 84 89 void init() 85 90 { 86 valid = false; 87 update = false; 88 brdcast= false; 89 rsp = false; 90 ack = false; 91 srcid = 0; 92 trdid = 0; 93 pktid = 0; 94 nline = 0; 95 count = 0; 91 valid = false; 92 update = false; 93 brdcast = false; 94 rsp = false; 95 ack = false; 96 srcid = 0; 97 trdid = 0; 98 pktid = 0; 99 nline = 0; 100 count = 0; 101 is_change = 0; 96 102 } 97 103 … … 103 109 void copy(const UpdateTabEntry &source) 104 110 { 105 valid = source.valid; 106 update = source.update; 107 brdcast= source.brdcast; 108 rsp = source.rsp; 109 ack = source.ack ; 110 srcid = source.srcid; 111 trdid = source.trdid; 112 pktid = source.pktid; 113 nline = source.nline; 114 count = source.count; 111 valid = source.valid; 112 update = source.update; 113 brdcast = source.brdcast; 114 rsp = source.rsp; 115 ack = source.ack; 116 srcid = source.srcid; 117 trdid = source.trdid; 118 pktid = source.pktid; 119 nline = source.nline; 120 count = source.count; 121 is_change = source.is_change; 115 122 } 116 123 … … 220 227 const addr_t nline, 221 228 const size_t count, 222 size_t &index) 229 size_t &index, 230 const bool is_change=false) 223 231 { 224 232 for ( size_t i=0 ; i<size_tab ; i++ ) … … 236 244 tab[i].nline = (addr_t) nline; 237 245 tab[i].count = (size_t) count; 246 tab[i].is_change = is_change; 238 247 index = i; 239 248 return true; … … 452 461 } 453 462 463 void change(const size_t index) 464 { 465 assert(index<size_tab && "Bad Update Tab Entry"); 466 tab[index].is_change = true; 467 } 468 469 size_t is_change(const size_t index) 470 { 471 assert(index<size_tab && "Bad Update Tab Entry"); 472 return tab[index].is_change; 473 } 454 474 }; 455 475 -
branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r675 r677 161 161 MULTI_ACK_HEAP_LOCK, 162 162 MULTI_ACK_HEAP_WRITE, 163 MULTI_ACK_ WAIT163 MULTI_ACK_IVT_CHANGE 164 164 }; 165 165 … … 1024 1024 sc_signal<size_t> r_cleanup_locked_index; // ivt index 1025 1025 sc_signal<bool> r_cleanup_locked_is_updt; 1026 sc_signal<bool> r_cleanup_locked_is_change; 1026 1027 1027 1028 sc_signal<size_t> r_cleanup_miss_srcid; // srcid of write rsp … … 1029 1030 sc_signal<size_t> r_cleanup_miss_pktid; // pktid of write rsp 1030 1031 sc_signal<size_t> r_cleanup_miss_index; // ivt index 1031 sc_signal<bool> r_cleanup_miss_is_updt;1032 1032 sc_signal<bool> r_cleanup_miss_need_rsp; // write response required 1033 1033 sc_signal<bool> r_cleanup_miss_need_ack; // config acknowledge required
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