Changeset 682 for branches/MESI/modules/vci_mem_cache
- Timestamp:
- Apr 23, 2014, 4:45:19 PM (11 years ago)
- File:
-
- 1 edited
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branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r680 r682 3184 3184 << " / count = " <<std::dec << entry.count 3185 3185 << " / copy = " <<std::dec << entry.owner.srcid 3186 << " / is_inst = " << entry.owner.inst 3186 3187 << " / is_cnt = " << entry.is_cnt << std::endl; 3187 3188 if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl; … … 5954 5955 5955 5956 } 5956 if (!r_xram_rsp_victim_coherent.read())5957 {5958 addr_t min = r_xram_rsp_victim_nline.read()*m_words*4 ;5959 addr_t max = r_xram_rsp_victim_nline.read()*m_words*4 + (m_words - 1)*4;5960 m_llsc_table.sw(min, max);5961 }5957 // if (!r_xram_rsp_victim_coherent.read()) 5958 // { 5959 // addr_t min = r_xram_rsp_victim_nline.read()*m_words*4 ; 5960 // addr_t max = r_xram_rsp_victim_nline.read()*m_words*4 + (m_words - 1)*4; 5961 // m_llsc_table.sw(min, max); 5962 // } 5962 5963 #if DEBUG_MEMC_XRAM_RSP 5963 5964 if(m_debug) … … 6759 6760 // (r_cas_to_cleanup_nline.read() == r_cleanup_nline.read()); 6760 6761 6761 size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS; 6762 //size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS; 6763 //size_t match_sc_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_SC; 6762 6764 6763 6765 bool match_ll = ((r_cleanup_locked_pktid.read() & 0x07) == TYPE_LL); … … 6772 6774 if( not r_cleanup_contains_data.read() ) 6773 6775 { 6776 if(r_write_to_cleanup_req.read() and r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) 6777 //update the line with the data saved in write_to_cleanup_data table if the cleanup without data 6778 { 6779 for (size_t word = 0; word < m_words; word ++) 6780 { 6781 m_cache_data.write(way, set, word, r_write_to_cleanup_data[word].read(), r_write_to_cleanup_be[word].read()); 6782 } 6783 //addr_t min = r_cleanup_nline.read()*m_words*4 ; 6784 //addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; 6785 //m_llsc_table.sw(min, max); 6786 } 6787 6774 6788 size_t set = m_y[(addr_t)(cleanup_address)]; 6775 6789 m_cache_data.read_line(way, set, r_cleanup_data); … … 6781 6795 m_cache_data.write(way, set, word, r_cleanup_data[word].read(), 0xF); 6782 6796 } 6783 addr_t min = r_cleanup_nline.read()*m_words*4 ; 6784 addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; 6785 m_llsc_table.sw(min, max); 6797 6798 if((r_cleanup_locked_pktid.read() & 0x7) != TYPE_SC) 6799 { 6800 addr_t min = r_cleanup_nline.read()*m_words*4 ; 6801 addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; 6802 m_llsc_table.sw(min, max); 6803 } 6786 6804 } 6787 6805 … … 6823 6841 else // cas, getm, one copy updated in dir 6824 6842 { 6825 if(match_cas_inval)6826 {6827 entry.state = ENTRY_SHARED;6828 entry.count = 0;6829 }6830 elseif(r_cleanup_locked_is_read.read())6843 // if(match_cas_inval or match_sc_inval) 6844 // { 6845 // entry.state = ENTRY_SHARED; 6846 // entry.count = 0; 6847 // } 6848 if(r_cleanup_locked_is_read.read()) 6831 6849 { 6832 6850 entry.state = ENTRY_EXCLUSIVE; … … 6867 6885 if(r_cleanup_to_tgt_rsp_req.read()) break; 6868 6886 6869 size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS;6887 //size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS; 6870 6888 6871 6889 r_cleanup_to_tgt_rsp_req = true; … … 6906 6924 } 6907 6925 6908 if(r_write_to_cleanup_req.read() )6926 if(r_write_to_cleanup_req.read() and r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) 6909 6927 r_write_to_cleanup_req = false; 6910 6928 … … 7370 7388 std::vector<be_t> (m_words,0), 7371 7389 data_vector); 7390 7391 addr_t min = r_cleanup_nline.read()*m_words*4 ; 7392 addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; 7393 m_llsc_table.sw(min, max); 7372 7394 } 7373 7395 //std::cout << "cleanup with a non coherent ligne in trt index = " << index << std::endl; … … 11756 11778 DspinDhccpParam::dspin_set( 11757 11779 flit, 11758 DspinDhccpParam::TYPE_MULTI_INVAL_DATA,11780 multi_inval_type, 11759 11781 DspinDhccpParam::M2P_TYPE); 11760 11782 }
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