Changeset 730 for trunk/platforms

Timestamp:

Jun 29, 2014, 1:51:52 PM (10 years ago)

Author:

alain

Message:

Introducing distributed page_tables and kernel code in arch.py for the
tsar_generic_iob platform.

Location:

trunk/platforms/tsar_generic_iob

Files:

• arch.py (modified) (4 diffs)
• non_distributed_arch.py (added)
• top.cpp (modified) (7 diffs)

trunk/platforms/tsar_generic_iob/arch.py

@@ -12 +12 @@
 #  physical space segmentation) and the mapping of all kernel objects (global vsegs).
 #  This platform includes 6 external peripherals, accessible through two IO_Bridge
-# components located in cluster [0,0] and cluster [x_size-1, y_size-1].
-# Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA.
+#  components located in cluster [0,0] and cluster [x_size-1, y_size-1].
+#  Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA.
 #
 #  The "constructor" parameters are:
@@ -113 +113 @@
 
     boot_mapping_vbase   = 0x00000000      # ident
-    boot_mapping_size    = 0x00010000      # 64 Kbytes
-
-    boot_code_vbase      = 0x00010000      # ident
+    boot_mapping_size    = 0x00040000      # 256 Kbytes
+
+    boot_code_vbase      = 0x00040000      # ident
     boot_code_size       = 0x00020000      # 128 Kbytes 
   
-    boot_data_vbase      = 0x00030000      # ident
+    boot_data_vbase      = 0x00060000      # ident
     boot_data_size       = 0x00010000      # 64 Kbytes
 
-    boot_buffer_vbase    = 0x00040000      # ident
+    boot_buffer_vbase    = 0x00070000      # ident
     boot_buffer_size     = 0x00060000      # 384 Kbytes
 
-    boot_stack_vbase     = 0x000A0000      # ident
+    boot_stack_vbase     = 0x000D0000      # ident
     boot_stack_size      = 0x00050000      # 320 Kbytes
 
@@ -218 +218 @@
                 mapping.addProc( x, y, p )
 
-    ### global vsegs for boot_loader / identity mapping
-
-    mapping.addGlobal( 'seg_boot_mapping'  , boot_mapping_vbase  , boot_mapping_size  , 'C_W_', 
-                       vtype = 'BLOB'  , x = 0, y = 0, pseg = 'RAM', identity = True )
-
-    mapping.addGlobal( 'seg_boot_code'     , boot_code_vbase     , boot_code_size     , 'CXW_', 
-                       vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True )
-
-    mapping.addGlobal( 'seg_boot_data'     , boot_data_vbase     , boot_data_size     , 'C_W_', 
-                       vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True )
-
-    mapping.addGlobal( 'seg_boot_buffer'   , boot_buffer_vbase   , boot_buffer_size   , 'C_W_', 
-                       vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True )
-
-    mapping.addGlobal( 'seg_boot_stack'    , boot_stack_vbase    , boot_stack_size    , 'C_W_', 
-                       vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True )
-
-    ### global vsegs for kernel   
-
-    mapping.addGlobal( 'seg_kernel_code'   , kernel_code_vbase   , kernel_code_size   , 'CXW_', 
-                       vtype = 'ELF'   , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' )
-
-    mapping.addGlobal( 'seg_kernel_data'   , kernel_data_vbase   , kernel_data_size   , 'C_W_', 
-                       vtype = 'ELF'   , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' )
-
-    mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_', 
-                       vtype = 'ELF'   , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' )
-
-    mapping.addGlobal( 'seg_kernel_init'   , kernel_init_vbase   , kernel_init_size   , 'CXW_', 
-                       vtype = 'ELF'   , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' )
+    ### global vsegs for boot_loader / identity mapping 
+
+    mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size,
+                       'C_W_', vtype = 'BLOB'  , x = 0, y = 0, pseg = 'RAM',
+                       identity = True )
+
+    mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size,
+                       'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
+                       identity = True )
+
+    mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size,
+                       'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
+                       identity = True )
+
+    mapping.addGlobal( 'seg_boot_buffer', boot_buffer_vbase, boot_buffer_size,
+                       'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
+                       identity = True )
+
+    mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size,
+                       'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
+                       identity = True )
+
+    ### local global vsegs for kernel / same virtual address / different physical address
+
+    for x in xrange( x_size ):
+        for y in xrange( y_size ):
+            cluster_xy = (x << y_width) + y;
+
+            mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size,
+                               'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM',
+                               binpath = 'build/kernel/kernel.elf', local = True )
+
+            mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size,
+                               'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM',
+                               binpath = 'build/kernel/kernel.elf', local = True )
+
+    ### shared global vsegs for kernel
+
+    mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, 
+                       'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 
+                       binpath = 'build/kernel/kernel.elf', local = False )
+
+    mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size,
+                       '__W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 
+                       binpath = 'build/kernel/kernel.elf', local = False )
 
     ### global vsegs for external peripherals / identity mapping
 
     mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', identity = True )
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', 
+                       identity = True )
 
     mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', identity = True )
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'BDV',
+                       identity = True )
 
     mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', identity = True )
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'TTY',
+                       identity = True )
 
     mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', identity = True )
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'NIC',
+                       identity = True )
 
     mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', identity = True )
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'CMA',
+                       identity = True )
 
     mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', identity = True )
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'FBF',
+                       identity = True )
 
     mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', identity = True )
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'PIC',
+                       identity = True )
 
     mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', 
-                       vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', identity = True )
-
-    ### Global vsegs for replicated peripherals, and for schedulers 
-    ### name is indexed by (x,y), base address is incremented by (cluster_xy * peri_increment)
+                       vtype = 'PERI', x = 0, y = 0, pseg = 'ROM',
+                       identity = True )
+
+    ### global vsegs for internal peripherals, and for schedulers 
+    ### name is indexed by (x,y) / vbase address is incremented by (cluster_xy * peri_increment)
 
     for x in xrange( x_size ):
@@ -303 +326 @@
 if __name__ == '__main__':
 
-    mapping = genmap( x_size    = 2,
-                      y_size    = 2,
-                      nb_procs  = 2,
-                      nb_ttys   = 1,
-                      nb_nics   = 2, 
-                      fbf_width = 128,
-                      x_io      = 0,
-                      y_io      = 0 )
+    mapping = arch( x_size    = 2,
+                    y_size    = 2,
+                    nb_procs  = 2 )
 
 #   print mapping.netbsd_dts()

trunk/platforms/tsar_generic_iob/top.cpp

@@ -11 +11 @@
 // - BROM : boot ROM
 // - FBUF : Frame Buffer
-// - MTTY : multi TTY (up to 15 channels)
+// - MTTY : multi TTY (one channel)
 // - MNIC : Network controller (up to 2 channels)
 // - CDMA : Chained Buffer DMA controller (up to 4 channels)
-// - BDEV : Dlock Device controler (1 channel)
+// - BDEV : Dlock Device controler (one channel)
 // - IOPI : HWI to SWI translator.
 //
@@ -39 +39 @@
 // external IOPIC component, that must be configured by the OS to route
 // these WTI ITQS to one or several internal XICU components.
-// The total number of channels for the external peripherals (MTTY, MNIC, CDMA
-// IOC or HBA) is limited by the IOPIC 32 HWI inputs:..
 // - IOPIC HWI[1:0]     connected to IRQ_NIC_RX[1:0]
 // - IOPIC HWI[3:2]     connected to IRQ_NIC_TX[1:0]
 // - IOPIC HWI[7:4]     connected to IRQ_CMA_TX[3:0]]
 // - IOPIC HWI[8]       connected to IRQ_BDEV
-// - IOPIC HWI[15:9]    unused       (grounded)
-// - IOPIC HWI[23:16]   connected to IRQ_TTY_RX[7:0]]
-// - IOPIC HWI[31:24]   connected to IRQ_TTY_TX[7:0]]   TBD
+// - IOPIC HWI[9]       connected to IRQ_TTY_RX[0]
 //
-// Besides the external peripherals, each cluster contains on XICU component,
+// Besides the external peripherals, each cluster contains one XICU component,
 // and one multi channels DMA component.
 // The XICU component is mainly used to handle WTI IRQs, as only 2 HWI IRQs
@@ -232 +228 @@
 //////////////////////i/////////////////////////////////////
 
-#define MAX_FROZEN_CYCLES     200000
+#define MAX_FROZEN_CYCLES     20000000
 
 /////////////////////////////////////////////////////////
@@ -1428 +1424 @@
 
         // Monitor a specific address for one L2 cache
-        // clusters[0][0]->memc->cache_monitor( 0x170000ULL);
+        // clusters[0][0]->memc->cache_monitor( 0x1542c0ULL, true );   // single word monitoring
 
         // Monitor a specific address for one XRAM
@@ -1445 +1441 @@
                 size_t x          = cluster_xy >> 4;
                 size_t y          = cluster_xy & 0xF;
-
-                clusters[x][y]->proc[l]->print_trace(1);
+  
+                clusters[x][y]->proc[l]->print_trace(0x40);
                 std::ostringstream proc_signame;
                 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
@@ -1511 +1507 @@
 //              clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI");
 
-                signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI");
-                signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT");
+//              signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI");
+//              signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT");
 
 //              cdma->print_trace();
@@ -1528 +1524 @@
                 signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
 
-                mnic->print_trace();
-                signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT");
+//              mnic->print_trace();
+//              signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT");
 
 //              fbuf->print_trace();