Changeset 730 for trunk/platforms/tsar_generic_iob
- Timestamp:
- Jun 29, 2014, 1:51:52 PM (10 years ago)
- Location:
- trunk/platforms/tsar_generic_iob
- Files:
-
- 1 added
- 2 edited
-
arch.py (modified) (4 diffs)
-
non_distributed_arch.py (added)
-
top.cpp (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_iob/arch.py
r714 r730 12 12 # physical space segmentation) and the mapping of all kernel objects (global vsegs). 13 13 # This platform includes 6 external peripherals, accessible through two IO_Bridge 14 # components located in cluster [0,0] and cluster [x_size-1, y_size-1].15 # Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA.14 # components located in cluster [0,0] and cluster [x_size-1, y_size-1]. 15 # Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA. 16 16 # 17 17 # The "constructor" parameters are: … … 113 113 114 114 boot_mapping_vbase = 0x00000000 # ident 115 boot_mapping_size = 0x000 10000 # 64Kbytes116 117 boot_code_vbase = 0x000 10000 # ident115 boot_mapping_size = 0x00040000 # 256 Kbytes 116 117 boot_code_vbase = 0x00040000 # ident 118 118 boot_code_size = 0x00020000 # 128 Kbytes 119 119 120 boot_data_vbase = 0x000 30000 # ident120 boot_data_vbase = 0x00060000 # ident 121 121 boot_data_size = 0x00010000 # 64 Kbytes 122 122 123 boot_buffer_vbase = 0x000 40000 # ident123 boot_buffer_vbase = 0x00070000 # ident 124 124 boot_buffer_size = 0x00060000 # 384 Kbytes 125 125 126 boot_stack_vbase = 0x000 A0000 # ident126 boot_stack_vbase = 0x000D0000 # ident 127 127 boot_stack_size = 0x00050000 # 320 Kbytes 128 128 … … 218 218 mapping.addProc( x, y, p ) 219 219 220 ### global vsegs for boot_loader / identity mapping 221 222 mapping.addGlobal( 'seg_boot_mapping' , boot_mapping_vbase , boot_mapping_size , 'C_W_', 223 vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', identity = True ) 224 225 mapping.addGlobal( 'seg_boot_code' , boot_code_vbase , boot_code_size , 'CXW_', 226 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 227 228 mapping.addGlobal( 'seg_boot_data' , boot_data_vbase , boot_data_size , 'C_W_', 229 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 230 231 mapping.addGlobal( 'seg_boot_buffer' , boot_buffer_vbase , boot_buffer_size , 'C_W_', 232 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 233 234 mapping.addGlobal( 'seg_boot_stack' , boot_stack_vbase , boot_stack_size , 'C_W_', 235 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 236 237 ### global vsegs for kernel 238 239 mapping.addGlobal( 'seg_kernel_code' , kernel_code_vbase , kernel_code_size , 'CXW_', 240 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 241 242 mapping.addGlobal( 'seg_kernel_data' , kernel_data_vbase , kernel_data_size , 'C_W_', 243 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 244 245 mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_', 246 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 247 248 mapping.addGlobal( 'seg_kernel_init' , kernel_init_vbase , kernel_init_size , 'CXW_', 249 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 220 ### global vsegs for boot_loader / identity mapping 221 222 mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, 223 'C_W_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', 224 identity = True ) 225 226 mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, 227 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 228 identity = True ) 229 230 mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, 231 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 232 identity = True ) 233 234 mapping.addGlobal( 'seg_boot_buffer', boot_buffer_vbase, boot_buffer_size, 235 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 236 identity = True ) 237 238 mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, 239 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 240 identity = True ) 241 242 ### local global vsegs for kernel / same virtual address / different physical address 243 244 for x in xrange( x_size ): 245 for y in xrange( y_size ): 246 cluster_xy = (x << y_width) + y; 247 248 mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size, 249 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', 250 binpath = 'build/kernel/kernel.elf', local = True ) 251 252 mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size, 253 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', 254 binpath = 'build/kernel/kernel.elf', local = True ) 255 256 ### shared global vsegs for kernel 257 258 mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, 259 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 260 binpath = 'build/kernel/kernel.elf', local = False ) 261 262 mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, 263 '__W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 264 binpath = 'build/kernel/kernel.elf', local = False ) 250 265 251 266 ### global vsegs for external peripherals / identity mapping 252 267 253 268 mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 254 vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', identity = True ) 269 vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', 270 identity = True ) 255 271 256 272 mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 257 vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', identity = True ) 273 vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', 274 identity = True ) 258 275 259 276 mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 260 vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', identity = True ) 277 vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', 278 identity = True ) 261 279 262 280 mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 263 vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', identity = True ) 281 vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', 282 identity = True ) 264 283 265 284 mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 266 vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', identity = True ) 285 vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', 286 identity = True ) 267 287 268 288 mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 269 vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', identity = True ) 289 vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', 290 identity = True ) 270 291 271 292 mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 272 vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', identity = True ) 293 vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', 294 identity = True ) 273 295 274 296 mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', 275 vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', identity = True ) 276 277 ### Global vsegs for replicated peripherals, and for schedulers 278 ### name is indexed by (x,y), base address is incremented by (cluster_xy * peri_increment) 297 vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', 298 identity = True ) 299 300 ### global vsegs for internal peripherals, and for schedulers 301 ### name is indexed by (x,y) / vbase address is incremented by (cluster_xy * peri_increment) 279 302 280 303 for x in xrange( x_size ): … … 303 326 if __name__ == '__main__': 304 327 305 mapping = genmap( x_size = 2, 306 y_size = 2, 307 nb_procs = 2, 308 nb_ttys = 1, 309 nb_nics = 2, 310 fbf_width = 128, 311 x_io = 0, 312 y_io = 0 ) 328 mapping = arch( x_size = 2, 329 y_size = 2, 330 nb_procs = 2 ) 313 331 314 332 # print mapping.netbsd_dts() -
trunk/platforms/tsar_generic_iob/top.cpp
r718 r730 11 11 // - BROM : boot ROM 12 12 // - FBUF : Frame Buffer 13 // - MTTY : multi TTY ( up to 15 channels)13 // - MTTY : multi TTY (one channel) 14 14 // - MNIC : Network controller (up to 2 channels) 15 15 // - CDMA : Chained Buffer DMA controller (up to 4 channels) 16 // - BDEV : Dlock Device controler ( 1channel)16 // - BDEV : Dlock Device controler (one channel) 17 17 // - IOPI : HWI to SWI translator. 18 18 // … … 39 39 // external IOPIC component, that must be configured by the OS to route 40 40 // these WTI ITQS to one or several internal XICU components. 41 // The total number of channels for the external peripherals (MTTY, MNIC, CDMA42 // IOC or HBA) is limited by the IOPIC 32 HWI inputs:..43 41 // - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] 44 42 // - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] 45 43 // - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] 46 44 // - IOPIC HWI[8] connected to IRQ_BDEV 47 // - IOPIC HWI[15:9] unused (grounded) 48 // - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]] 49 // - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]] TBD 45 // - IOPIC HWI[9] connected to IRQ_TTY_RX[0] 50 46 // 51 // Besides the external peripherals, each cluster contains on XICU component,47 // Besides the external peripherals, each cluster contains one XICU component, 52 48 // and one multi channels DMA component. 53 49 // The XICU component is mainly used to handle WTI IRQs, as only 2 HWI IRQs … … 232 228 //////////////////////i///////////////////////////////////// 233 229 234 #define MAX_FROZEN_CYCLES 200000 230 #define MAX_FROZEN_CYCLES 20000000 235 231 236 232 ///////////////////////////////////////////////////////// … … 1428 1424 1429 1425 // Monitor a specific address for one L2 cache 1430 // clusters[0][0]->memc->cache_monitor( 0x1 70000ULL);1426 // clusters[0][0]->memc->cache_monitor( 0x1542c0ULL, true ); // single word monitoring 1431 1427 1432 1428 // Monitor a specific address for one XRAM … … 1445 1441 size_t x = cluster_xy >> 4; 1446 1442 size_t y = cluster_xy & 0xF; 1447 1448 clusters[x][y]->proc[l]->print_trace( 1);1443 1444 clusters[x][y]->proc[l]->print_trace(0x40); 1449 1445 std::ostringstream proc_signame; 1450 1446 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; … … 1511 1507 // clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); 1512 1508 1513 1514 1509 // signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); 1510 // signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); 1515 1511 1516 1512 // cdma->print_trace(); … … 1528 1524 signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 1529 1525 1530 1531 1526 // mnic->print_trace(); 1527 // signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); 1532 1528 1533 1529 // fbuf->print_trace();
Note: See TracChangeset
for help on using the changeset viewer.
