Changeset 742 for branches/fault_tolerance/modules
- Timestamp:
- Jul 9, 2014, 5:36:08 PM (11 years ago)
- Location:
- branches/fault_tolerance/modules
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
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branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h
r724 r742 33 33 // contain 32 bits words. It supports VCI addresss lartger than 32 bits. 34 34 // 35 // This component can perform data transfers between one single file belonging36 // to the host system and a buffer in the memory of the virtual prototype.37 // The file name is an argument of the constructor.35 // This component can perform data transfers between one single file (belonging 36 // to the host system) and a buffer in the memory of the virtual prototype. 37 // The name of the file containing the disk image is a constructor argument. 38 38 // This component has a DMA capability, and is both a target and an initiator. 39 39 // The block size (bytes), and the burst size (bytes) must be power of 2. … … 54 54 // - BLOCK_DEVICE_SIZE 0x18 (read-only) Number of addressable blocks. 55 55 // - BLOCK_DEVICE_BLOCK_SIZE 0x1C (read_only) Block size in bytes. 56 // - BLOCK_DEVICE_BUFFER_EXT 0x20 (read _only)Memory buffer base address (MSB bits)56 // - BLOCK_DEVICE_BUFFER_EXT 0x20 (read/write) Memory buffer base address (MSB bits) 57 57 // 58 58 // The following operations codes are supported: -
branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r724 r742 342 342 bool m_debug_dcache_fsm; 343 343 bool m_debug_cmd_fsm; 344 uint32_t m_previous_status; 345 344 346 345 347 /////////////////////////////// -
branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r724 r742 476 476 { 477 477 // b0 : write buffer trace 478 // b1 : dump processor registers 478 479 // b2 : dcache trace 479 480 // b3 : icache trace 480 481 // b4 : dtlb trace 481 482 // b5 : itlb trace 483 // b6 : SR (ISS register 32) 482 484 483 485 std::cout << std::dec << "PROC " << name() << std::endl; … … 509 511 r_wbuf.printTrace((mode>>1)&1); 510 512 } 513 if(mode & 0x02) 514 { 515 r_iss.dump(); 516 } 511 517 if(mode & 0x04) 512 518 { … … 528 534 std::cout << " Instruction TLB" << std::endl; 529 535 r_itlb.printTrace(); 536 } 537 if(mode & 0x40) 538 { 539 uint32_t status = r_iss.debugGetRegisterValue( 32 ); 540 std::cout << name(); 541 if ( status != m_previous_status ) std::cout << " NEW "; 542 std::cout << " status = " << std::hex << status << " " << std::endl; 543 m_previous_status = status; 530 544 } 531 545 } -
branches/fault_tolerance/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp
r724 r742 736 736 { 737 737 assert( p_vci_tgt_iox.eop.read() and 738 (p_vci_tgt_iox.cmd == vci_param_int::CMD_WRITE) and738 (p_vci_tgt_iox.cmd.read() == vci_param_int::CMD_WRITE) and 739 739 "ERROR in VCI_IOB illegal VCI WTI command from IOX network"); 740 740 -
branches/fault_tolerance/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r725 r742 3940 3940 if (m_debug) 3941 3941 std::cout << " <MEMC " << name() << " WRITE_BC_DIR_INVAL> Inval DIR and register in TRT:" 3942 << " address = " << r_write_address.read() << std::endl;3942 << " address = " << std::hex << r_write_address.read() << std::endl; 3943 3943 #endif 3944 3944 r_write_fsm = WRITE_BC_CC_SEND;
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