- Timestamp:
- Jul 9, 2014, 5:36:08 PM (10 years ago)
- Location:
- branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
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branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r724 r742 342 342 bool m_debug_dcache_fsm; 343 343 bool m_debug_cmd_fsm; 344 uint32_t m_previous_status; 345 344 346 345 347 /////////////////////////////// -
branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r724 r742 476 476 { 477 477 // b0 : write buffer trace 478 // b1 : dump processor registers 478 479 // b2 : dcache trace 479 480 // b3 : icache trace 480 481 // b4 : dtlb trace 481 482 // b5 : itlb trace 483 // b6 : SR (ISS register 32) 482 484 483 485 std::cout << std::dec << "PROC " << name() << std::endl; … … 509 511 r_wbuf.printTrace((mode>>1)&1); 510 512 } 513 if(mode & 0x02) 514 { 515 r_iss.dump(); 516 } 511 517 if(mode & 0x04) 512 518 { … … 528 534 std::cout << " Instruction TLB" << std::endl; 529 535 r_itlb.printTrace(); 536 } 537 if(mode & 0x40) 538 { 539 uint32_t status = r_iss.debugGetRegisterValue( 32 ); 540 std::cout << name(); 541 if ( status != m_previous_status ) std::cout << " NEW "; 542 std::cout << " status = " << std::hex << status << " " << std::endl; 543 m_previous_status = status; 530 544 } 531 545 }
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