Changeset 744 for trunk/softs/giet_tsar/reset.S
- Timestamp:
- Jul 10, 2014, 11:23:57 AM (10 years ago)
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- 1 edited
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trunk/softs/giet_tsar/reset.S
r743 r744 5 5 ********************************************************************************* 6 6 * This is a boot code for a generic multi-clusters / multi-processors 7 * TSAR architecture (up to 256 clusters / up to 4 processors per cluster). 7 * TSAR architecture (up to 256 clusters / up to 4 processors per cluster). 8 8 * The physical address is 40 bits, and the 8 MSB bits A[39:32] define the 9 9 * cluster index. 10 10 * 11 * As we don't want to use the virtual memory, the physical address is 11 * As we don't want to use the virtual memory, the physical address is 12 12 * equal to the virtual address (identity mapping) and all processors stacks 13 * and code segments are allocated in the physical memory bank in cluster 0. 13 * and code segments are allocated in the physical memory bank in cluster 0. 14 14 * 15 15 * Both the reset base address and the kernel base address must be redefined … … 22 22 * There is two sets of peripherals: 23 23 * 24 * 1) A block device and a single channel TTY controller are available 24 * 1) A block device and a single channel TTY controller are available 25 25 * in cluster(0,0). 26 26 * 27 * 2) Other peripherals (including another Blockdevice, a multi-channels TTY 27 * 2) Other peripherals (including another Blockdevice, a multi-channels TTY 28 28 * contrÃŽler, a Frame buffer) are located in cluster_io. 29 29 * For those externals peripherals, hardware interrupts (HWI) are translated … … 37 37 * - Only processor 0 initializes the IOPIC component. 38 38 * - Each processor initializes its private XCU mask. 39 * - Each processor initializes the Status Register (SR) 39 * - Each processor initializes the Status Register (SR) 40 40 * - Each processor jumps to the same main address in kernel mode... 41 41 ********************************************************************************/ … … 56 56 .extern main 57 57 58 .globl reset 58 .globl reset 59 59 .ent reset 60 60 .align 2 … … 95 95 96 96 la $26, _interrupt_vector /* interrupt vector address */ 97 la $27, _mmc_isr 97 la $27, _mmc_isr 98 98 sw $27, 32($26) /* interrupt_vector[8] <= _mmc_isr */ 99 la $27, _ioc_isr 99 la $27, _ioc_isr 100 100 sw $27, 36($26) /* interrupt_vector[9] <= _ioc_isr */ 101 la $27, _tty_isr 101 la $27, _tty_isr 102 102 sw $27, 40($26) /* interrupt_vector[10] <= _tty_isr */ 103 103 … … 129 129 130 130 #endif 131 131 132 132 reset_xcu: 133 133 … … 149 149 150 150 /* initializes SR register */ 151 li $26, 0x0000FF01 151 li $26, 0x0000FF01 152 152 mtc0 $26, $12 /* SR <= kernel mode / IRQ enable */ 153 153
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