Changeset 745 for branches/fault_tolerance/softs/giet_tsar/reset.S
- Timestamp:
- Jul 10, 2014, 11:42:14 AM (10 years ago)
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branches/fault_tolerance/softs/giet_tsar/reset.S (modified) (8 diffs)
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branches/fault_tolerance/softs/giet_tsar/reset.S
r724 r745 1 1 /******************************************************************************** 2 * 3 * 4 * 2 * File : reset.S 3 * Author : Alain Greiner 4 * Date : 15/01/2014 5 5 ********************************************************************************* 6 6 * This is a boot code for a generic multi-clusters / multi-processors 7 * TSAR architecture (up to 256 clusters / up to 4 processors per cluster). 7 * TSAR architecture (up to 256 clusters / up to 4 processors per cluster). 8 8 * The physical address is 40 bits, and the 8 MSB bits A[39:32] define the 9 9 * cluster index. 10 10 * 11 * As we don't want to use the virtual memory, the physical address is 11 * As we don't want to use the virtual memory, the physical address is 12 12 * equal to the virtual address (identity mapping) and all processors stacks 13 * and code segments are allocated in the physical memory bank in cluster 0. 13 * and code segments are allocated in the physical memory bank in cluster 0. 14 14 * 15 15 * Both the reset base address and the kernel base address must be redefined … … 22 22 * There is two sets of peripherals: 23 23 * 24 * 1) A block device and a single channel TTY controller are available 24 * 1) A block device and a single channel TTY controller are available 25 25 * in cluster(0,0). 26 26 * 27 * 2) Other peripherals (including another Blockdevice, a multi-channels TTY 27 * 2) Other peripherals (including another Blockdevice, a multi-channels TTY 28 28 * contrÃŽler, a Frame buffer) are located in cluster_io. 29 29 * For those externals peripherals, hardware interrupts (HWI) are translated … … 34 34 * - Each processor initializes the stack pointer ($29) depending on proc_id. 35 35 * - Each processor initializes the CP0 EBASE register 36 * 36 * - Only processor 0 initializes the Interrupt vector. 37 37 * - Only processor 0 initializes the IOPIC component. 38 38 * - Each processor initializes its private XCU mask. 39 * - Each processor initializes the Status Register (SR)40 * 39 * - Each processor initializes the Status Register (SR) 40 * - Each processor jumps to the same main address in kernel mode... 41 41 ********************************************************************************/ 42 42 … … 44 44 #include "mips32_registers.h" 45 45 46 46 .section .reset,"ax",@progbits 47 47 48 .externseg_stack_base49 .externseg_xcu_base48 .extern seg_stack_base 49 .extern seg_xcu_base 50 50 .extern seg_pic_base 51 51 .extern seg_kcode_base 52 53 54 52 .extern _interrupt_vector 53 .extern _ioc_isr 54 .extern _mmc_isr 55 55 .extern _tty_isr 56 56 .extern main 57 57 58 .globl reset 59 .entreset60 .align258 .globl reset 59 .ent reset 60 .align 2 61 61 62 62 reset: 63 63 .set noreorder 64 64 65 65 /* each proc computes proc_id, lpid, cluster_xy */ 66 66 mfc0 $26, CP0_PROCID 67 andi $26, $26, 0x3FF 67 andi $26, $26, 0x3FF /* at most 1024 processors */ 68 68 move $10, $26 /* $10 <= proc_id */ 69 69 li $27, NB_PROCS_MAX … … 73 73 74 74 /* each proc initializes stack pointer (64K per processor) */ 75 srl $8, $12, Y_WIDTH /* $8 <= x */ 76 li $9, Y_SIZE 77 mul $8, $8, $9 /* $8 <= x * Y_SIZE */ 78 andi $13, $12, (1<<Y_WIDTH)-1 79 addu $8, $8, $13 /* $8 <= x * Y_SIZE + y */ 80 mul $8, $8, $27 /* $8 <= (x*Y_SIZE+y)*NB_PROCS_MAX */ 81 addu $10, $11, $8 /* $10 <= (x*Y_SIZE+y)*NB_PROCS_MAX + lpid */ 82 75 83 la $27, seg_stack_base 76 addi $26, $10, 1 84 addi $26, $10, 1 /* $26 <= (proc_id + 1) */ 77 85 sll $26, $26, 14 /* $26 <= (proc_id + 1) * 16K */ 78 addu $29, $27, $26 86 addu $29, $27, $26 /* $29 <= seg_stack_base(proc_id) */ 79 87 80 88 /* each proc initializes CP0 EBASE register */ … … 83 91 84 92 /* only proc (0,0,0) initializes interrupt vector for IOC, TTY, MMC */ 85 bne 93 bne $10, $0, reset_xcu 86 94 nop 87 95 88 96 la $26, _interrupt_vector /* interrupt vector address */ 89 la $27, _mmc_isr 97 la $27, _mmc_isr 90 98 sw $27, 32($26) /* interrupt_vector[8] <= _mmc_isr */ 91 la $27, _ioc_isr 99 la $27, _ioc_isr 92 100 sw $27, 36($26) /* interrupt_vector[9] <= _ioc_isr */ 93 la $27, _tty_isr 101 la $27, _tty_isr 94 102 sw $27, 40($26) /* interrupt_vector[10] <= _tty_isr */ 95 103 96 104 /* only proc (0,0,0) initializes IOPIC : IOPIC_ADDRESS[i] <= &XICU[0].WTI_REG[i] */ 97 105 98 li $26, USE_EXT_IO 99 beq $26, $0, reset_xcu /* IOPIC not initialised if not USE_EXT_IO */ 106 #if USE_IOPIC 100 107 101 108 li $20, X_SIZE … … 120 127 121 128 mtc2 $0, CP2_PADDR_EXT /* CP2_PADDR_EXT <= zero */ 122 129 130 #endif 131 123 132 reset_xcu: 124 133 … … 140 149 141 150 /* initializes SR register */ 142 li $26, 0x0000FF01143 mtc0 $26, $12 151 li $26, 0x0000FF01 152 mtc0 $26, $12 /* SR <= kernel mode / IRQ enable */ 144 153 145 154 /* jumps to main in kernel mode */ 146 la 155 la $26, main 147 156 jr $26 148 157 nop 149 158 150 .end 159 .end reset 151 160 152 161 .set reorder
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